Philips
Semiconductors
74LVT16373A
3.3V LVT 16-bit transparent D-type latch
(3-State)
Product specification
Supersedes data of 1994 Dec 15
IC23 Data Handbook
1998 Feb 19
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
74LVT16373A
3.3V 16-bit transparent D-type latch (3-State)
2
1998 Feb 19
853-1780 18989
FEATURES
16-bit transparent latch
3-State buffers
Output capability: +64mA/-32mA
TTL input and output switching levels
Input and output interface capability to systems at 5V supply
Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
Live insertion/extraction permitted
Power-up reset
Power-up 3-State
No bus current loading when output is tied to 5V bus
Latch-up protection exceeds 500mA per JEDEC Std 17
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
DESCRIPTION
The 74LVT16373A is a high-performance BiCMOS product
designed for V
CC
operation at 3.3V.
This device is a 16-bit transparent D-type latch with non-inverting
3-State bus compatible outputs. The device can be used as two
8-bit latches or one 16-bit latch. When enable (E) input is High, the
Q outputs follow the data (D) inputs. When enable is taken Low, the
Q outputs are latched at the levels of the D inputs one setup time
prior to the High-to-Low transition.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
T
amb
= 25
C
TYPICAL
UNIT
t
PLH
t
PHL
Propagation delay
nDx to nQx
C
L
= 50pF;
V
CC
= 3.3V
1.9
ns
C
IN
Input capacitance
V
I
= 0V or 3.0V
3
pF
C
OUT
Output capacitance
Outputs disabled; V
O
= 0V or 3.0V
9
pF
I
CCZ
Total supply current
Outputs disabled; V
CC
= 3.6V
70
A
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
48-Pin Plastic SSOP Type III
40
C to +85
C
74LVT16373A DL
VT16373A DL
SOT370-1
48-Pin Plastic TSSOP Type II
40
C to +85
C
74LVT16373A DGG
VT16373A DGG
SOT362-1
LOGIC SYMBOL
3
2
1Q0 1Q1 1Q2
6
5
1Q3
47
46
44
43
1D0 1D1 1D2 1D3
48
1
9
8
1Q4 1Q5 1Q6
12
11
1Q7
41
40
38
37
1D4 1D5 1D6 1D7
1LE
1OE
14
13
17
16
36
35
33
32
25
24
20
19
23
22
30
29
27
26
2Q0 2Q1 2Q2 2Q3
2D0 2D21 2D2 2D3
2Q4 2Q5 2Q6 2Q7
2D4 2D5 2D6 2D7
2LE
2OE
SA00044
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
47, 46, 44, 43, 41, 40, 38, 37,
36, 35, 33, 32, 30, 29, 27, 26
1D0 1D7
2D0 2D7
Data inputs
2, 3, 5, 6, 8, 9, 11, 12, 13,
14, 16, 17, 19, 20, 22, 23
1Q0 1Q7
2Q0 2Q7
Data outputs
1, 24
1OE, 2OE
Output enable
inputs
(active-Low)
48, 25
1E, 2E
Enable inputs
(active-High)
4, 10, 15, 21, 28, 34, 39, 45
GND
Ground (0V)
7, 18, 31, 42
V
CC
Positive
supply voltage
Philips Semiconductors
Product specification
74LVT16373A
3.3V 16-bit transparent D-type latch (3-State)
1998 Feb 19
3
LOGIC SYMBOL (IEEE/IEC)
48
1EN
1
46
44
43
41
40
38
37
36
C3
2EN
C4
2
1
24
25
47
35
33
32
30
29
27
26
3
2
5
6
8
9
11
12
13
14
16
17
19
20
22
23
SW00010
1OE
1LE
2OE
2LE
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q8
1D8
2Q6
2Q7
3D
4D
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Q0
1Q1
GND
1Q2
1Q3
1Q4
1Q5
GND
1Q6
1Q7
2Q0
2Q1
GND
2Q3
VCC
2Q4
VCC
2Q2
2Q5
GND
2Q7
2OE
2Q6
1LE
1D0
1D1
GND
1D2
1D3
1D4
1D5
GND
1D6
1D7
2D0
2D1
GND
2D3
VCC
2D4
VCC
2D2
2D5
GND
2D7
2LE
2D6
SA00043
LOGIC DIAGRAM
E
Q
D
nD0
nQ0
E
Q
D
nD1
E
Q
D
nD2
E
Q
D
nD3
E
Q
D
nD4
E
Q
D
nD5
E
Q
D
nD6
E
Q
D
nD7
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
nLE
nOE
SA00046
Philips Semiconductors
Product specification
74LVT16373A
3.3V 16-bit transparent D-type latch (3-State)
1998 Feb 19
4
FUNCTION TABLE
INPUTS
INTERNAL
OUTPUTS
OPERATING MODE
nOE
nE
nDx
REGISTER
nQ0 nQ7
OPERATING MODE
L
L
H
H
L
H
L
H
L
H
Enable and read register
L
L
l
h
L
H
L
H
Latch and read register
L
L
X
NC
NC
Hold
H
H
L
H
X
nDx
NC
nDx
Z
Z
Disable outputs
H = High voltage level
h
= High voltage level one set-up time prior to the High-to-Low E transition
L
= Low voltage level
l
= Low voltage level one set-up time prior to the High-to-Low E transition
NC= No change
X = Don't care
Z = High impedance "off " state
= High-to-Low E transition
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
CC
DC supply voltage
0.5 to +4.6
V
I
IK
DC input diode current
V
I
< 0
50
mA
V
I
DC input voltage
3
0.5 to +7.0
V
I
OK
DC output diode current
V
O
< 0
50
mA
V
OUT
DC output voltage
3
Output in Off or High state
0.5 to +7.0
V
I
O
DC output current
Output in Low state
128
mA
I
OUT
DC output current
Output in High state
64
mA
T
stg
Storage temperature range
65 to +150
C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN
MAX
UNIT
V
CC
DC supply voltage
2.7
3.6
V
V
I
Input voltage
0
5.5
V
V
IH
High-level input voltage
2.0
V
V
IL
Input voltage
0.8
V
I
OH
High-level output current
32
mA
I
OL
Low-level output current
32
mA
Low-level output current; current duty cycle
50%; f
1kHz
64
t/
v
Input transition rise or fall rate; Outputs enabled
10
ns/V
T
amb
Operating free-air temperature range
40
+85
C
Philips Semiconductors
Product specification
74LVT16373A
3.3V 16-bit transparent D-type latch (3-State)
1998 Feb 19
5
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40
C to +85
C
UNIT
MIN
TYP
1
MAX
V
IK
Input clamp voltage
V
CC
= 2.7V; I
IK
= 18mA
.85
1.2
V
V
CC
= 2.7 to 3.6V; I
OH
= 100
A
V
CC
-0.2
V
CC
V
OH
High-level output voltage
V
CC
= 2.7V; I
OH
= 8mA
2.4
2.5
V
V
CC
= 3.0V; I
OH
= 32mA
2.0
2.3
V
CC
= 2.7V; I
OL
= 100
A
0.07
0.2
V
CC
= 2.7V; I
OL
= 24mA
0.3
0.5
V
OL
Lowlevel output voltage
V
CC
= 3.0V; I
OL
= 16mA
0.25
0.4
V
V
CC
= 3.0V; I
OL
= 32mA
0.3
0.5
V
CC
= 3.0V; I
OL
= 64mA
0.4
0.55
V
RST
Power-up output Low voltage
5
V
CC
= 3.6V; I
O
= 1mA; V
I
= GND or V
CC
0.1
0.55
V
V
CC
= 3.6V; V
I
= V
CC
or GND
Control pins
0.1
1
I
I
Input leakage current
V
CC
= 0 or 3.6V; V
I
= 5.5V
0.4
10
A
I
I
In ut leakage current
V
CC
= 3.6V; V
I
= V
CC
Data pins
4
0.1
1
A
V
CC
= 3.6V; V
I
= 0
Data ins
4
-0.4
-5
I
OFF
Output off current
V
CC
= 0V; V
I
or V
O
= 0 to 4.5V
0.1
100
A
7
V
CC
= 3V; V
I
= 0.8V
75
135
I
HOLD
Bus Hold current D inputs
7
V
CC
= 3V; V
I
= 2.0V
75
-135
A
V
CC
= 0V to 3.6V; V
CC
= 3.6V
500
I
EX
Current into an output in the
High state when V
O
> V
CC
V
O
= 5.5V; V
CC
= 3.0V
50
125
A
I
PU/PD
Power up/down 3-State output
current
3
V
CC
1.2V; V
O
= 0.5V to V
CC
; V
I
= GND or V
CC
;
OE/OE = Don't care
1
100
A
I
OZH
3-State output High current
V
CC
= 3.6V; V
O
= 3.0V; V
I
= V
IH
or V
IL
0.5
5
A
I
OZL
3-State output Low current
V
CC
= 3.6V; V
O
= 0.5V; V
I
= V
IH
or V
IL
0.5
5
A
I
CCH
V
CC
= 3.6V; Outputs High, V
I
= GND or V
CC,
I
O =
0
0.07
0.12
I
CCL
Quiescent supply current
V
CC
= 3.6V; Outputs Low, V
I
= GND or V
CC,
I
O =
0
4.0
6
mA
I
CCZ
V
CC
= 3.6V; Outputs Disabled; V
I
= GND or V
CC,
I
O =
0
6
0.07
0.12
I
CC
Additional supply current per
input pin
2
V
CC
= 3V to 3.6V; One input at V
CC
-0.6V,
Other inputs at V
CC
or GND
0.1
0.2
mA
NOTES:
1. All typical values are at V
CC
= 3.3V and T
amb
= 25
C.
2. This is the increase in supply current for each input at the specified voltage level other than V
CC
or GND.
3. This parameter is valid for any V
CC
between 0V and 1.2V with a transition time of up to 10msec. From V
CC
= 1.2V to V
CC
= 3.3V
0.3V a
transition time of 100
sec is permitted. This parameter is valid for T
amb
= 25
C only.
4. Unused pins at V
CC
or GND.
5. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
6. I
CCZ
is measured with outputs pulled to V
CC
or GND.
7. This is the bus hold overdrive current required to force the input to the opposite logic state.
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