Philips
Semiconductors
74LVT273
3.3V Octal D flip-flop
Product specification
Supersedes data of 1994 May 11
IC23 Data Handbook
1998 Feb 19
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
74LVT273
3.3V Octal D flip-flop
2
1998 Feb 19
853-1740 18985
FEATURES
Eight edge-triggered D-type flip-flops
Buffered common clock
Buffered asynchronous Master Reset
Output capability: +64mA/32mA
TTL input and output switching levels
Input and output interface capability to systems at 5V supply
Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
Power-up reset
Live insertion/extraction permitted
No bus current loading when output is tied to 5V bus
Latchup protection exceeds 500 mA per JEDEC Std 17
ESD protection exceeds 2000V per Mil Std 883 Method 3015 and
200V per Machine Model.
DESCRIPTION
The LVT273 is a high-performance BiCMOS product designed for
V
CC
operation at 3.3V.
This device has eight edge-triggered D-type flip-flops with individual
D inputs and Q outputs. The common buffered Clock (CP) and
Master Reset (MR) inputs load and reset (clear) all flip-flops
simultaneously.
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop's Q output.
All outputs will be forced Low independent of Clock or Data inputs
by a Low voltage level on the MR input. The device is useful for
applications where the true output only is required and the CP and
MR are common elements.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
T
amb
= 25
C; GND = 0V
TYPICAL
UNIT
t
PLH
t
PHL
Propagation delay
CP to Qn
C
L
= 50pF; V
CC
= 3.3V
3.5
3.5
ns
C
IN
Input capacitance
V
I
= 0V or 3.0V
4
pF
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
20-Pin Plastic SOL
40
C to +85
C
74LVT273 D
74LVT273 D
SOT163-1
20-Pin Plastic SSOP Type II
40
C to +85
C
74LVT273 DB
74LVT273 DB
SOT339-1
20-Pin Plastic TSSOP Type I
40
C to +85
C
74LVT273 PW
74LVT273PW DH
SOT360-1
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MR
Q0
D0
D1
Q1
Q2
D2
D3
Q3
Q4
GND
D4
D5
Q5
Q6
D6
D7
Q7
VCC
CP
SV00017
LOGIC SYMBOL
3
4
7
8
13
14
18
17
D0 D1 D2 D3 D4 D5 D6 D7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2
5
6
9
12
15 16
19
1
11
MR
CP
SV00018
Philips Semiconductors
Product specification
74LVT273
3.3V Octal D flip-flop
1998 Feb 19
3
LOGIC SYMBOL (IEEE/IEC)
11
3
2
4
5
7
6
8
9
C1
13
12
14
15
17
16
18
19
1
R
1D
SV00019
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING
MR
CP
D
n
Q0 Q7
OPERATING
MODE
L
X
X
L
Reset (clear)
H
h
H
Load "1"
H
l
L
Load "0"
H
L
X
Q
0
Retain state
H = High voltage level
h
= High voltage level one set-up time prior to the Low-to-High
clock transition
L
= Low voltage level
l
= Low voltage level one set-up time prior to the Low-to-High
clock transition
X = Don't care
= Low-to-High clock transition
Q
0
= Output as it was
PIN DESCRIPTION
PIN NUMBER
SYMBOL
NAME AND FUNCTION
11
CP
Clock pulse input (active rising edge)
3, 4, 7, 8, 13, 14, 17, 18
D0 D7
Data inputs
2, 5, 6, 9, 12, 15, 16, 19
Q0 Q7
Data outputs
1
MR
Master Reset input (active-Low)
10
GND
Ground (0V)
20
V
CC
Positive supply voltage
LOGIC DIAGRAM
CP
Q
RD
D
3
D0
Q0
CP
Q
RD
D
4
D1
CP
Q
RD
D
7
D2
CP
Q
RD
D
8
D3
CP
Q
RD
D
13
D4
CP
Q
RD
D
14
D5
CP
Q
RD
D
17
D6
CP
Q
RD
D
18
D7
2
Q1
5
Q2
6
Q3
9
Q4
12
Q5
15
Q6
16
Q7
19
11
1
CP
MR
SV00020
Philips Semiconductors
Product specification
74LVT273
3.3V Octal D flip-flop
1998 Feb 19
4
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
CC
DC supply voltage
0.5 to +4.6
V
I
IK
DC input diode current
V
I
< 0
50
mA
V
I
DC input voltage
3
0.5 to +7.0
V
I
OK
DC output diode current
V
O
< 0
50
mA
V
OUT
DC output voltage
3
output in Off or High state
0.5 to +7.0
V
I
O
DC output current
Output in Low state
128
mA
I
OUT
DC output current
Output in High State
64
mA
T
stg
Storage temperature range
65 to 150
C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN
MAX
UNIT
V
CC
DC supply voltage
2.7
3.6
V
V
I
Input voltage
0
5.5
V
V
IH
High-level input voltage
2.0
V
V
IL
Low-level Input voltage
0.8
V
I
OH
High-level output current
32
mA
I
OL
Low-level output current
64
mA
t/
v
Input transition rise or fall rate; Outputs enabled
10
ns/V
T
amb
Operating free-air temperature range
40
+85
C
Philips Semiconductors
Product specification
74LVT273
3.3V Octal D flip-flop
1998 Feb 19
5
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40
C to +85
C
UNIT
MIN
TYP
1
MAX
V
IK
Input clamp voltage
V
CC
= 2.7V; I
IK
= 18mA
0.9
1.2
V
V
CC
= 2.7 to 3.6V; I
OH
= 100
A
V
CC
-0.2
V
CC
0.1
V
OH
High-level output voltage
V
CC
= 2.7V; I
OH
= 8mA
2.4
2.5
V
V
CC
= 3.0V; I
OH
= 32mA
2.0
2.2
V
CC
= 2.7V; I
OL
= 100
A
0.1
0.2
V
CC
= 2.7V; I
OL
= 24mA
0.3
0.5
V
OL
Low-level output voltage
V
CC
= 3.0V; I
OL
= 16mA
0.25
0.4
V
V
CC
= 3.0V; I
OL
= 32mA
0.3
0.5
V
CC
= 3.0V; I
OL
= 64mA
0.4
0.55
V
RST
Power-up output low voltage
4
V
CC
= 3.6V; I
O
= 1mA; V
I
= GND or V
CC
0.13
0.55
V
V
CC
= 0 or 3.6V; V
I
= 5.5V
1
10
I
I
t l
k
t
V
CC
= 3.6V; V
I
= V
CC
or GND
Control pins
0.1
1
A
I
I
Input leakage current
V
CC
= 3.6V; V
I
= V
CC
Data pins
3
0.1
1
A
V
CC
= 3.6V; V
I
= 0
Data pins
3
1
-5
I
OFF
Output off current
V
CC
= 0V; V
I
or V
O
= 0 to 4.5V
1
100
A
5
V
CC
= 3V; V
I
= 0.8V
75
150
I
HOLD
Bus Hold current A inputs
5
V
CC
= 3V; V
I
= 2.0V
75
150
A
V
CC
= 0V to 3.6V; V
CC
= 3.6V
500
I
EX
Current into an output in the
High state when V
O
> V
CC
V
O
= 5.5V; V
CC
= 3.0V
60
125
A
I
CCH
Quiescent supply current
V
CC
= 3.6V; Outputs High, V
I
= GND or V
CC,
I
O =
0
0.13
0.19
I
CCL
Quiescent supply current
V
CC
= 3.6V; Outputs Low, V
I
= GND or V
CC,
I
O =
0
3
12
mA
I
CC
Additional supply current per
input pin
2
V
CC
= 3V to 3.6V; One input at V
CC
-0.6V,
Other inputs at V
CC
or GND
0.1
0.2
mA
NOTES:
1. All typical values are at V
CC
= 3.3V and T
amb
= 25
C.
2. This is the increase in supply current for each input at the specified voltage level other than V
CC
or GND
3. Unused pins at V
CC
or GND.
4. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
5. This is the bus hold overdrive current required to force the input to the opposite logic state.
AC CHARACTERISTICS
GND = 0V; t
R
= t
F
= 2.5ns; C
L
= 50pF, R
L
= 500
; T
amb
= 40
C to +85
C.
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= 3.3V
0.3V
V
CC
= 2.7V
UNIT
MIN
TYP
1
MAX
MAX
f
MAX
Maximum clock frequency
1
150
MHz
t
PLH
t
PHL
Propagation delay
CP to Qn
1
1.7
1.9
3.5
3.5
5.5
5.5
6.3
5.9
ns
t
PHL
Propagation delay
MR to Qn
2
1.3
3.2
6.2
6.2
ns
NOTE:
1. All typical values are at V
CC
= 3.3V and T
amb
= 25
C.
PDF 
ZIP