Philips
Semiconductors
74LVT574
3.3V Octal D-type flip-flop (3-State)
Product specification
Supersedes data of 1995 Nov 14
IC23 Data Handbook
1998 Feb 19
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
74LVT574
3.3V Octal D-type flip-flop (3-State)
2
1998 Feb 19
853-1746 18988
FEATURES
Inputs and outputs on opposite side of package allow easy
interface to microprocessors
3-State outputs for bus interfacing
Common output enable
TTL input and output switching levels
Input and output interface capability to systems at 5V supply
Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
Live insertion/extraction permitted
No bus current loading when output is tied to 5V bus
Power-up 3-State
Power-up reset
Latch-up protection exceeds 500mA per JEDEC Std 17
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
DESCRIPTION
The LVT574 is a high-performance BiCMOS product designed for
V
CC
operation at 3.3V.
This device is an 8-bit, edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by the clock (CP) and Output Enable (OE) control
gates. The state of each D input (one set-up time before the
Low-to-High clock transition) is transferred to the corresponding
flip-flop's Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active-Low Output Enable (OE) controls all eight 3-State buffers
independent of the clock operation.
When OE is Low, the stored data appears at the outputs. When OE
is High, the outputs are in the High-impedance "off" state, which
means they will neither drive nor load the bus.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
T
amb
= 25
C; GND = 0V
TYPICAL
UNIT
t
PLH
t
PHL
Propagation delay
CP to Qn
C
L
= 50pF;
V
CC
= 3.3V
3.6
4.3
ns
C
IN
Input capacitance
V
I
= 0V or 3.0V
4
pF
C
OUT
Output capacitance
Outputs disabled;
V
I/O
= 0V or 3.0V
8
pF
I
CCZ
Total supply current
Outputs disabled;
V
CC
= 3.6V
0.13
mA
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
20-Pin Plastic SOL
40
C to +85
C
74LVT574 D
74LVT574 D
SOT163-1
20-Pin Plastic SSOP Type II
40
C to +85
C
74LVT574 DB
74LVT574 DB
SOT339-1
20-Pin Plastic TSSOP Type I
40
C to +85
C
74LVT574 PW
74LVT574PW DH
SOT360-1
PIN CONFIGURATION
20
19
18
17
16
15
14
13
12
10
11
9
8
7
6
5
4
3
2
1
VCC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CP
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
SV00041
LOGIC SYMBOL
2
3
4
5
6
7
8
9
11
1
CP
OE
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
19
18
17
16
15
14
13
12
SV00042
Philips Semiconductors
Product specification
74LVT574
3.3V Octal D-type flip-flop (3-State)
1998 Feb 19
3
LOGIC SYMBOL (IEEE/IEC)
EN
C1
1D
SV00033
12
13
14
15
16
17
18
19
9
8
7
6
5
4
3
2
11
1
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
1
OE
Output enable input
(active-low)
2, 3, 4, 5, 6, 7, 8, 9
D0-D7
Data inputs
19, 18, 17, 16, 15,
14, 13, 12
Q0-Q7
Data outputs
11
CP
Clock pulse input (active
rising edge)
10
GND
Ground (0V)
20
V
CC
Positive supply voltage
FUNCTION TABLE
INPUTS
INTERNAL
OUTPUTS
OPERATING
OE
CP
Dn
REGISTER
Q0 Q7
MODE
L
L
l
h
L
H
L
H
Load and read register
L
X
NC
NC
Hold
H
X
X
NC
Z
Disable outputs
H = High voltage level
h
= High voltage level one set-up time prior to the Low-to-High clock transition
L
= Low voltage level
l
= Low voltage level one set-up time prior to the Low-to-High clock transition
NC= No change
X = Don't care
Z = High impedance "off" state
= Low-to-High clock transition
= not a Low-to-High clock transition
LOGIC DIAGRAM
19
CP Q
D
2
D0
Q0
CP Q
D
3
D1
CP Q
D
4
D2
CP Q
D
5
D3
CP Q
D
6
D4
CP Q
D
7
D5
CP Q
D
8
D6
CP Q
D
9
D7
Q1
18
Q2
17
Q3
16
Q4
15
Q5
14
Q6
13
Q7
12
11
CP
1
OE
SV00043
Philips Semiconductors
Product specification
74LVT574
3.3V Octal D-type flip-flop (3-State)
1998 Feb 19
4
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
CC
DC supply voltage
0.5 to +4.6
V
I
IK
DC input diode current
V
I
< 0
50
mA
V
I
DC input voltage
3
0.5 to +7.0
V
I
OK
DC output diode current
V
O
< 0
50
mA
V
OUT
DC output voltage
3
Output in Off or High state
0.5 to +7.0
V
I
O
DC output current
Output in Low state
128
mA
I
OUT
DC output current
Output in High state
64
mA
T
stg
Storage temperature range
65 to 150
C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN
MAX
UNIT
V
CC
DC supply voltage
2.7
3.6
V
V
I
Input voltage
0
5.5
V
V
IH
High-level input voltage
2.0
V
V
IL
Input voltage
0.8
V
I
OH
High-level output current
32
mA
I
OL
Low-level output current
32
mA
I
OL
Low-level output current; current duty cycle
50%, f
1kHz
64
mA
t/
v
Input transition rise or fall rate; outputs enabled
10
ns/V
T
amb
Operating free-air temperature range
40
+85
C
Philips Semiconductors
Product specification
74LVT574
3.3V Octal D-type flip-flop (3-State)
1998 Feb 19
5
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40
C to +85
C
UNIT
MIN
TYP
1
MAX
V
IK
Input clamp voltage
V
CC
= 2.7V; I
IK
= 18mA
0.9
1.2
V
V
CC
= 2.7 to 3.6V; I
OH
= 100
A
V
CC
-0.2
V
CC
-0.1
V
OH
High-level output voltage
V
CC
= 2.7V; I
OH
= 8mA
2.4
2.5
V
V
CC
= 3.0V; I
OH
= 32mA
2.0
2.2
V
CC
= 2.7V; I
OL
= 100
A
0.1
0.2
V
CC
= 2.7V; I
OL
= 24mA
0.3
0.5
V
OL
Low-level output voltage
V
CC
= 3.0V; I
OL
= 16mA
0.25
0.4
V
V
CC
= 3.0V; I
OL
= 32mA
0.3
0.5
V
CC
= 3.0V; I
OL
= 64mA
0.4
0.55
V
RST
Power-up output low voltage
5
V
CC
= 3.6V; I
O
= 1mA; V
I
= GND or V
CC
0.13
0.55
V
V
CC
= 0 or 3.6V; V
I
= 5.5V
1
10
I
I
Input leakage current
V
CC
= 3.6V; V
I
= V
CC
or GND
Control pins
0.1
1
A
I
I
In ut leakage current
V
CC
= 3.6V; V
I
= V
CC
Data pins
4
0.1
1
A
V
CC
= 3.6V; V
I
= 0
Data ins
4
1
-5
I
OFF
Output off current
V
CC
= 0V; V
I
or V
O
= 0 to 4.5V
1
100
A
7
V
CC
= 3V; V
I
= 0.8V
75
150
I
HOLD
Bus Hold current A inputs
7
V
CC
= 3V; V
I
= 2.0V
75
150
A
V
CC
= 0V to 3.6V; V
CC
= 3.6V
500
I
EX
Current into an output in the
High state when V
O
> V
CC
V
O
= 5.5V; V
CC
= 3.0V
60
125
A
I
PU/PD
Power up/down 3-State output
current
3
V
CC
1.2V; V
O
= 0.5V to V
CC
; V
I
= GND or V
CC
;
OE/OE = Don't care
1
100
A
I
OZH
3-State output High current
V
CC
= 3.6V; V
O
= 3V; V
I
= V
IL
or V
IH
1
5
A
I
OZL
3-State output Low current
V
CC
= 3.6V; V
O
= 0.5V; V
I
= V
IL
or V
IH
1
5
A
I
CCH
V
CC
= 3.6V; Outputs High, V
I
= GND or V
CC,
I
O =
0
0.13
0.19
I
CCL
Quiescent supply current
3
V
CC
= 3.6V; Outputs Low, V
I
= GND or V
CC,
I
O =
0
3
12
mA
I
CCZ
V
CC
= 3.6V; Outputs Disabled; V
I
= GND or V
CC,
I
O =
0
5
0.13
0.19
I
CC
Additional supply current per
input pin
2
V
CC
= 3V to 3.6V; One input at V
CC
-0.6V,
Other inputs at V
CC
or GND
0.1
0.2
mA
NOTES:
1. All typical values are at V
CC
= 3.3V and T
amb
= 25
C.
2. This is the increase in supply current for each input at the specified voltage level other than V
CC
or GND
3. This parameter is valid for any V
CC
between 0V and 1.2V with a transition time of up to 10msec. From V
CC
= 1.2V to V
CC
= 3.3V
0.3V a
transition time of 100
sec is permitted. This parameter is valid for T
amb
= 25
C only.
4. Unused pins at V
CC
or GND.
5. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
6. I
CCZ
is measured with outputs pulled to V
CC
or GND.
7. This is the bus hold overdrive current required to force the input to the opposite logic state.
AC CHARACTERISTICS
GND = 0V, t
R
= t
F
= 2.5ns, C
L
= 50pF, R
L
= 500
; T
amb
= 40
C to +85
C.
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= 3.3V
0.3V
V
CC
= 2.7V
UNIT
MIN
TYP
1
MAX
MIN
MAX
f
MAX
Maximum clock frequency
NO TAG
150
150
ns
t
PLH
t
PHL
Propagation delay
CP to Qn
NO TAG
1.7
2.4
3.6
4.3
5.4
5.9
6.2
6.6
ns
t
PZH
t
PZL
Output enable time
to High and Low level
NO TAG
NO TAG
1.0
1.3
2.9
3.4
4.8
5.1
5.9
6.2
ns
t
PHZ
t
PLZ
Output disable time
from High and Low level
NO TAG
NO TAG
1.9
1.7
4.0
3.2
5.5
4.5
5.9
4.5
ns
NOTE:
1. All typical values are at V
CC
= 3.3V and T
amb
= 25
C.
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