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Электронный компонент: 80C55483C55487C554

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Philips
Semiconductors
80C554/87C554
80C51 8-bit microcontroller 6 clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I
2
C, PWM,
capture/compare, high I/O, 64L LQFP
Product data
Supersedes data of 2000 Nov 10
2003 Jan 28
INTEGRATED CIRCUITS
Philips Semiconductors
Product data
80C554/87C554
80C51 8-bit microcontroller 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I
2
C, PWM,
capture/compare, high I/O, 64L LQFP
2
2003 Jan 28
853-2408 29338
8DESCRIPTION
This data sheet describes the 6 clock version of the 8xC554. This
device is only available in 64L LQFP. The 8xC554 Single-Chip 8-Bit
Microcontroller is manufactured in an advanced CMOS process and
is a derivative of the 80C51 microcontroller family. The 87C554 has
the same instruction set as the 80C51. Three versions of the
derivative exist:
80C554--ROMless version
87C554--16 kbytes EPROM
The 87C554 contains a 16k
8 non-volatile EPROM, a 512
8
read/write data memory, five 8-bit I/O ports, one 8-bit input port, two
16-bit timer/event counters (identical to the timers of the 80C51), an
additional 16-bit timer coupled to capture and compare latches, a
15-source, four-priority-level, nested interrupt structure, an 7-input
ADC, a dual DAC pulse width modulated interface, two serial
interfaces (UART and I
2
C-bus), a "watchdog" timer and on-chip
oscillator and timing circuits. For systems that require extra
capability, the 8xC554 can be expanded using standard TTL
compatible memories and logic.
In addition, the 8xC554 has two software selectable modes of power
reduction--idle mode and power-down mode. The idle mode freezes
the CPU while allowing the RAM, timers, serial ports, and interrupt
system to continue functioning. Optionally, the ADC can be operated
in Idle mode. The power-down mode saves the RAM contents but
freezes the oscillator, causing all other chip functions to be
inoperative.
The device also functions as an arithmetic processor having
facilities for both binary and BCD arithmetic plus bit-handling
capabilities. The instruction set consists of over 100 instructions:
49 one-byte, 45 two-byte, and 17 three-byte. With an 8-MHz crystal,
58% of the instructions are executed in 0.75
s and 40% in 1.5
s.
Multiply and divide instructions require 3
s.
FEATURES
80C51 central processing unit
16k
8 EPROM expandable externally to 64 kbytes
An additional 16-bit timer/counter coupled to four capture registers
and three compare registers
Two standard 16-bit timer/counters
512
8 RAM, expandable externally to 64 kbytes
Capable of producing eight synchronized, timed outputs
A 10-bit ADC with seven multiplexed analog inputs
Fast 8-bit ADC option 9
S at 16 MHz
Two 8-bit resolution, pulse width modulation outputs
Five 8-bit I/O ports plus one 8-bit input port shared with analog
inputs
I
2
C-bus serial I/O port with byte oriented master and slave
functions
On-chip watchdog timer
Extended temperature ranges
Full static operation 0 to 16 MHz
Operating voltage range: 2.7 V to 5.5 V (0 to 8 MHz) and
4.5 V to 5.5 V (8 to 16 MHz) commercial temperature
Security bits:
ROM 2 bits
OTP/EPROM 3 bits
Four interrupt priority levels
15 interrupt sources
Full-duplex enhanced UART
Framing error detection
Automatic address recognition
Power control modes
Clock can be stopped and resumed
Idle mode
Power down mode
Second DPTR register
EMI reduction 6 clock operation and ALE inhibit
Programmable I/O pins
Wake-up from power-down by external interrupts
Software reset
Power-on detect reset
ADC charge pump disable
ONCE mode
ADC active in Idle mode
Philips Semiconductors
Product data
80C554/87C554
80C51 8-bit microcontroller 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I
2
C, PWM, capture/compare,
high I/O, 64L LQFP
2003 Jan 28
3
ORDERING INFORMATION
OTP/EPROM
ROMless
TEMPERATURE
C AND PACKAGE
FREQ.
(MHz)
DRAWING
NUMBER
P87C554SBBD
P80C554SBBD
0 to +70, Low Profile Quad Flat Package
16
SOT3142
P87C554SFBD
P80C554SFBD
40 to +85, Low Profile Quad Flat Package
16
SOT3142
PART NUMBER DERIVATION
DEVICE NUMBER
OPERATING FREQUENCY MAX
TEMPERATURE RANGE
PACKAGE
P87C554 OTP
S = 16 MHz
B= 0
_
C to 70
_
C
BD=64L LQFP
P80C554 ROMless
S = 16 MHz
F = 40
_
C to +85
_
C
BD=64L LQFP
BLOCK DIAGRAM
CPU
ADC
8-BIT INTERNAL BUS
16
P0
P1
P2
P3
TxD
RxD
P5
P4
CT0I-CT3I
T2
RT2
CMSR0-CMSR5
CMT0, CMT1
RST
EW
XTAL1
XTAL2
EA
ALE
PSEN
WR
RD
T0
T1
INT0
INT1
VDD
VSS
PWM0
PWM1
AVSS
AV
DD
AVREF
+
STADC
ADC0-7 SDA
SCL
3
3
3
3
3
3
0
2
1
1
1
4
1
1
5
0
1
2
ALTERNATE FUNCTION OF PORT 0
3
4
5
AD0-7
A8-15
3
3
16
T0, T1
TWO 16-BIT
TIMER/EVENT
COUNTERS
PROGRAM
MEMORY
16k x 8
OTP/ROM
DATA
MEMORY
512 x 8 RAM
DUAL
PWM
SERIAL
I2C PORT
80C51 CORE
EXCLUDING
ROM/RAM
PARALLEL I/O
PORTS AND
EXTERNAL BUS
SERIAL
UART
PORT
8-BIT
PORT
FOUR
16-BIT
CAPTURE
LATCHES
T2
16-BIT
TIMER/
EVENT
COUNTERS
T2
16-BIT
COMPARA-
TORS
WITH
REGISTERS
COMPARA-
TOR
OUTPUT
SELECTION
T3
WATCHDOG
TIMER
ALTERNATE FUNCTION OF PORT 1
ALTERNATE FUNCTION OF PORT 2
ALTERNATE FUNCTION OF PORT 3
ALTERNATE FUNCTION OF PORT 4
ALTERNATE FUNCTION OF PORT 5
SU00951
Philips Semiconductors
Product data
80C554/87C554
80C51 8-bit microcontroller 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I
2
C, PWM, capture/compare,
high I/O, 64L LQFP
2003 Jan 28
4
PIN CONFIGURATIONS
Plastic Quad Flat Pack pin functions
Pin
Function
1.
AV
DD
2.
P5.6/ADC6
3.
P5.5/ADC5
4.
P5.4/ADC4
5.
P5.3/ADC3
6.
P5.2/ADC2
7.
P5.1/ADC1
8.
P5.0/ADC0
9.
V
DD
10.
STADC
11.
PWM0
12.
PWM1
13.
EW
14.
P4.0/CMSR0
15.
P4.1/CMSR1
16.
P4.2/CMSR2
Pin
Function
17.
P4.3/CMSR3
18.
P4.4/CMSR4
19.
P4.5/CMSR5
20.
P4.6/CMT0
21.
P4.7/CMT1
22.
RST
23.
P1.0/CT0I
24.
P1.1/CT1I
25.
P1.2/CT2I
26.
P1.3/CT3I
27.
P1.4/T2
28.
P1.5/RT2
29.
P1.6/SCL
30.
P1.7/SDA
31.
P3.0/RxD
32.
P3.1/TxD
Pin
Function
33.
P3.2/INT0
34.
P3.3/INT1
35.
P3.4/T0
36.
P3.5/T1
37.
P3.6/WR
38.
P3.7/RD
39.
XTAL2
40.
XTAL1
41.
V
SS
42.
V
SS
43.
P2.0/A08
44.
P2.1/A09
45.
P2.2/A10
46.
P2.3/A11
47.
P2.4/A12
48.
P2.5/A13
Pin
Function
49.
P2.6/A14
50.
P2.7/A15
51.
PSEN
52.
ALE/PROG
53.
EA/V
PP
54.
P0.7/AD7
55.
P0.6/AD6
56.
P0.5/AD5
57.
P0.4/AD4
58.
P0.3/AD3
59.
P0.2/AD2
60.
P0.1/AD1
61.
P0.0/AD0
62.
AVref
63.
AVref+
64.
AV
SS
SU01444
LQFP64
48
33
49
64
32
17
1
16
LOGIC SYMBOL
POR
T
5
POR
T
4
ADC0-7
CMT0
CMT1
CMSR0-5
RST
EW
XTAL1
XTAL2
EA/V
PP
ALE/PROG
PSEN
AVref+
AVref
STADC
PWM0
PWM1
POR
T
0
LOW ORDER
ADDRESS AND
DATA BUS
POR
T
1
POR
T
2
POR
T
3
CT0I
CT1I
CT2I
CT3I
T2
RT2
SCL
SDA
RxD/DATA
TxD/CLOCK
INT0
INT1
T0
T1
WR
RD
V
SS
V
DD
AV
SS
AV
DD
HIGH ORDER
ADDRESS AND
DATA BUS
SU00210
Philips Semiconductors
Product data
80C554/87C554
80C51 8-bit microcontroller 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I
2
C, PWM, capture/compare,
high I/O, 64L LQFP
2003 Jan 28
5
PIN DESCRIPTION
PIN NO.
MNEMONIC
LQFP
TYPE
NAME AND FUNCTION
V
DD
9
I
Digital Power Supply: Positive voltage power supply pin during normal operation, idle and
power-down mode.
STADC
10
I
Start ADC Operation: Input starting analog to digital conversion (ADC operation can also be
started by software).
PWM0
11
O
Pulse Width Modulation: Output 0.
PWM1
12
O
Pulse Width Modulation: Output 1.
EW
13
I
Enable Watchdog Timer: Enable for T3 watchdog timer and disable power-down mode.
P0.0-P0.7
5461
I/O
Port 0: Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them
float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address
and data bus during accesses to external program and data memory. In this application it uses
strong internal pull-ups when emitting 1s. Port 0 is also used to input the code byte during
programming and to output the code byte during verification.
P1.0-P1.7
2330
I/O
Port 1: 8-bit I/O port. Alternate functions include:
2328
I/O
(P1.0-P1.5): Programmable I/O port pins.
2930
I/O
(P1.6, P1.7): Open drain port pins.
2326
I
CT0I-CT3I (P1.0-P1.3): Capture timer input signals for timer T2.
27
I
T2 (P1.4): T2 event input.
28
I
RT2 (P1.5): T2 timer reset signal. Rising edge triggered.
29
I/O
SCL (P1.6): Serial port clock line I
2
C-bus.
30
I/O
SDA (P1.7): Serial port data line I
2
C-bus.
Port 1 has four modes selected on a per bit basis by writing to the P1M1 and P1M2 registers as
follows:
P1M1.x
P1M2.x
Mode Description
0
0
Pseudobidirectional (standard c51 configuration; default)
0
1
Push-Pull
1
0
High impedance
1
1
Open drain
Port 1 is also used to input the lower order address byte during EPROM programming and
verification. A0 is on P1.0, etc.
P2.0-P2.7
4350
I/O
Port 2: 8-bit programmable I/O port.
Alternate function: High-order address byte for external memory (A08-A15). Port 2 is also used to
input the upper order address during EPROM programming and verification. A8 is on P2.0, A9 on
P2.1, through A13 on P2.5.
Port 2 has four output modes selected on a per bit basis by writing to the P2M1 and P2M2 registers
as follows:
P2M1.x
P2M2.x
Mode Description
0
0
Pseudobidirectional (standard c51 configuration; default)
0
1
Push-Pull
1
0
High impedance
1
1
Open drain
P3.0-P3.7
3138
I/O
Port 3: 8-bit programmable I/O port. Alternate functions include:
31
RxD(P3.0): Serial input port.
32
TxD (P3.1): Serial output port.
33
INT0 (P3.2): External interrupt.
34
INT1 (P3.3): External interrupt.
35
T0 (P3.4): Timer 0 external input.
36
T1 (P3.5): Timer 1 external input.
37
WR (P3.6): External data memory write strobe.
38
RD (P3.7): External data memory read strobe.
Port 3 has four modes selected on a per bit basis by writing to the P3M1 and P3M2 registers as
follows:
P3M1.x
P3M2.x
Mode Description
0
0
Pseudobidirectional (standard c51 configuration; default)
0
1
PushPull
1
0
High impedance
1
1
Open drain