DATA SHEET
Product specification
File under Discrete Semiconductors, SC07
1995 Apr 25
DISCRETE SEMICONDUCTORS
Philips Semiconductors
BF1100; BF1100R
Dual-gate MOS-FETs
1995 Apr 25
2
Philips Semiconductors
Product specification
Dual-gate MOS-FETs
BF1100; BF1100R
FEATURES
Specially designed for use at 9 to 12 V supply voltage
Short channel transistor with high forward transfer
admittance to input capacitance ratio
Low noise gain controlled amplifier up to 1 GHz
Superior cross-modulation performance during AGC.
APPLICATIONS
VHF and UHF applications such as television tuners and
professional communications equipment.
DESCRIPTION
Enhancement type field-effect transistor in a plastic
microminiature SOT143 or SOT143R package. The
transistor consists of an amplifier MOS-FET with source
and substrate interconnected and an internal bias circuit to
ensure good cross-modulation performance during AGC.
PINNING
CAUTION
The device is supplied in an antistatic package. The
gate-source input must be protected against static
discharge during transport or handling.
PIN
SYMBOL
DESCRIPTION
1
s, b
source
2
d
drain
3
g
2
gate 2
4
g
1
gate 1
Fig.1 Simplified outline (SOT143) and symbol.
BF1100 marking code: M56.
handbook, halfpage
4
3
2
1
Top view
MAM124
s,b
d
g
1
g
2
Fig.2 Simplified outline (SOT143R) and symbol.
BF1100R marking code: M57.
handbook, halfpage
Top view
MAM125 - 1
s,b
d
g
1
g
2
3
4
1
2
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
DS
drain-source voltage
-
-
14
V
I
D
drain current
-
-
30
mA
P
tot
total power dissipation
-
-
200
mW
T
j
operating junction temperature
-
-
150
C
y
fs
forward transfer admittance
24
28
33
mS
C
ig1-s
input capacitance at gate 1
-
2.2
2.6
pF
C
rs
reverse transfer capacitance
f = 1 MHz
-
25
35
fF
F
noise figure
f = 800 MHz
-
2
-
dB
1995 Apr 25
3
Philips Semiconductors
Product specification
Dual-gate MOS-FETs
BF1100; BF1100R
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Note
1. Device mounted on a printed-circuit board.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DS
drain-source voltage
-
14
V
I
D
drain current
-
30
mA
I
G1
gate 1 current
-
10
mA
I
G2
gate 2 current
-
10
mA
P
tot
total power dissipation
see Fig.3
BF1100
up to T
amb
= 50
C; note 1
-
200
mW
BF1100R
up to T
amb
= 40
C; note 1
-
200
mW
T
stg
storage temperature
-
65
+150
C
T
j
operating junction temperature
-
+150
C
Fig.3 Power derating curves.
handbook, halfpage
0
50
100
200
250
0
200
MLD155
150
150
100
50
Ptot
(mW)
T ( C)
amb
o
BF1100R
BF1100
Fig.4
Forward transfer admittance as a function
of junction temperature; typical values.
50
0
50
150
40
0
MLD156
100
30
20
10
Yfs
(mS)
T ( C)
j
o
1995 Apr 25
4
Philips Semiconductors
Product specification
Dual-gate MOS-FETs
BF1100; BF1100R
THERMAL CHARACTERISTICS
Notes
1. Device mounted on a printed-circuit board.
2. T
s
is the temperature at the soldering point of the source lead.
STATIC CHARACTERISTICS
T
j
= 25
C; unless otherwise specified.
Notes
1. R
G1
connects gate 1 to V
GG
= 9 V; see Fig.27.
2. R
G1
connects gate 1 to V
GG
= 12 V; see Fig.27.
SYMBOL
PARAMETER
CONDITIONS
VALUE
UNIT
R
th j-a
thermal resistance from junction to ambient
note 1
BF1100
500
K/W
BF1100R
550
K/W
R
th j-s
thermal resistance from junction to soldering point
note 2
BF1100
T
s
= 92
C
290
K/W
BF1100R
T
s
= 78
C
360
K/W
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
(BR)G1-SS
gate 1-source breakdown voltage
V
G2-S
= V
DS
= 0; I
G1-S
= 1 mA
13.2
20
V
V
(BR)G2-SS
gate 2-source breakdown voltage
V
G1-S
= V
DS
= 0; I
G2-S
= 1 mA
13.2
20
V
V
(F)S-G1
forward source-gate 1 voltage
V
G2-S
= V
DS
= 0; I
S-G1
= 10 mA
0.5
1.5
V
V
(F)S-G2
forward source-gate 2 voltage
V
G1-S
= V
DS
= 0; I
S-G2
= 10 mA
0.5
1.5
V
V
G1-S(th)
gate 1-source threshold voltage
V
G2-S
= 4 V; V
DS
= 9 V;
I
D
= 20
A
0.3
1
V
V
G2-S
= 4 V; V
DS
= 12 V;
I
D
= 20
A
0.3
1
V
V
G2-S(th)
gate 2-source threshold voltage
V
G1-S
= 4 V; V
DS
= 9 V;
I
D
= 20
A
0.3
1.2
V
V
G1-S
= 4 V; V
DS
= 12 V;
I
D
= 20
A
0.3
1.2
V
I
DSX
drain-source current
V
G2-S
= 4 V; V
DS
= 9 V;
R
G1
= 180 k
; note 1
8
13
mA
V
G2-S
= 4 V; V
DS
= 12 V;
R
G1
= 250 k
; note 2
8
13
mA
I
G1-SS
gate 1 cut-off current
V
G2-S
= V
DS
= 0; V
G1-S
= 12 V
-
50
nA
I
G2-SS
gate 2 cut-off current
V
G1-S
= V
DS
= 0; V
G2-S
= 12 V
-
50
nA
1995 Apr 25
5
Philips Semiconductors
Product specification
Dual-gate MOS-FETs
BF1100; BF1100R
DYNAMIC CHARACTERISTICS
Common source; T
amb
= 25
C; V
G2-S
= 4 V; I
D
= 10 mA; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
y
fs
forward transfer admittance
pulsed; T
j
= 25
C
V
DS
= 9 V
24
28
33
mS
V
DS
= 12 V
24
28
33
mS
C
ig1-s
input capacitance at gate 1
f = 1 MHz
V
DS
= 9 V
-
2.2
2.6
pF
V
DS
= 12 V
-
2.2
2.6
pF
C
ig2-s
input capacitance at gate 2
f = 1 MHz
V
DS
= 9 V
-
1.6
-
pF
V
DS
= 12 V
-
1.4
-
pF
C
os
drain-source capacitance
f = 1 MHz
V
DS
= 9 V
-
1.4
1.8
pF
V
DS
= 12 V
-
1.1
1.5
pF
C
rs
reverse transfer capacitance f = 1 MHz
V
DS
= 9 V
-
25
35
fF
V
DS
= 12 V
-
25
35
fF
F
noise figure
f = 800 MHz; G
S
= G
Sopt
; B
S
= B
Sopt
V
DS
= 9 V
-
2
2.8
dB
V
DS
= 12 V
-
2
2.8
dB
Fig.5
Gain reduction as a function of the AGC
voltage; typical values.
f = 50 MHz.
T
j
= 25
C.
handbook, halfpage
0
10
20
30
40
50
0
1
2
3
4
V (V)
AGC
gain
reduction
(dB)
MLD157
(1) R
G
= 250 k
to V
GG
= 12 V
(2) R
G
= 180 k
to V
GG
= 9 V
f
w
= 50 MHz; f
unw
= 60 MHz; T
amb
= 25
C.
Fig.6
Unwanted voltage for 1% cross-modulation
as a function of gain reduction; typical
values; see Fig.27.
handbook, halfpage
80
90
100
110
120
0
(1)
(2)
10
20
30
40
50
Vunw
(dB
V)
gain reduction (dB)
MLD158
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