DATA SHEET
Product specification
Supersedes data of 1997 Sep 03
File under Discrete Semiconductors, SC07
1997 Dec 08
DISCRETE SEMICONDUCTORS
BF1109; BF1109R; BF1109WR
N-channel dual-gate MOS-FETs
1997 Dec 08
2
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1109; BF1109R; BF1109WR
FEATURES
Short channel transistor with high
forward transfer admittance to input
capacitance ratio
Low noise gain controlled amplifier
up to 1 GHz
Internal self-biasing circuit to
ensure good cross-modulation
performance during AGC and good
DC stabilization.
APPLICATIONS
VHF and UHF applications with 9 V
supply voltage, such as television
tuners and professional
communications equipment.
DESCRIPTION
Enhancement type N-channel
field-effect transistor with source and
substrate interconnected. Integrated
diodes between gates and source
protect against excessive input
voltage surges. The BF1109,
BF1109R and BF1109WR are
encapsulated in the SOT143B,
SOT143R and SOT343R plastic
packages respectively.
PINNING
PIN
DESCRIPTION
1
source
2
drain
3
gate 2
4
gate 1
Fig.1
Simplified outline
(SOT143B).
BF1109 marking code: NFp.
Top view
MSB014
1
2
3
4
Fig.2
Simplified outline
(SOT143R).
BF1109R marking code: NBp.
handbook, 2 columns
Top view
MSB035
1
2
4
3
Fig.3
Simplified outline
(SOT343R).
BF1109WR marking code: NB.
fpage
Top view
MSB842
2
1
4
3
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
DS
drain-source voltage
-
-
11
V
I
D
drain current (DC)
-
-
30
mA
P
tot
total power dissipation
T
amb
80
C
-
-
200
mW
y
fs
forward transfer admittance
-
30
-
mS
C
ig1-ss
input capacitance at gate 1
-
2.2
2.7
pF
C
rss
reverse transfer capacitance
f = 1 MHz
-
25
40
fF
F
noise figure
f = 800 MHz
-
1.5
2.5
dB
X
mod
cross-modulation
input level for k = 1% at 40 dB AGC 100
-
-
dB
V
T
j
operating junction temperature
-
-
150
C
CAUTION
This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport
and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B.
1997 Dec 08
3
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1109; BF1109R; BF1109WR
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Note
1. Device mounted on a printed-circuit board.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DS
drain-source voltage
-
11
V
I
D
drain current (DC)
-
30
mA
I
G1
gate 1 current
-
10
mA
I
G2
gate 2 current
-
10
mA
P
tot
total power dissipation
T
amb
80
C; note 1
-
200
mW
T
stg
storage temperature
-
65
+150
C
T
j
operating junction temperature
-
+150
C
Fig.4 Power derating curve.
handbook, halfpage
0
40
80
160
250
0
200
MGM243
120
150
100
50
Ptot
(mW)
Tamb (
C)
1997 Dec 08
4
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1109; BF1109R; BF1109WR
THERMAL CHARACTERISTICS
Note
1. Device mounted on a printed-circuit board.
STATIC CHARACTERISTICS
T
j
= 25
C unless otherwise specified.
DYNAMIC CHARACTERISTICS
Common source; T
amb
= 25
C; V
G2-S
= 4 V; V
DS
= 9 V; self-biasing current; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
VALUE
UNIT
R
th j-a
thermal resistance from junction to ambient in free air
note 1
350
K/W
R
th j-s
thermal resistance from junction to soldering point
200
K/W
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
(BR)DSS
drain-source breakdown voltage
V
G1-S
= V
G2-S
= 0; I
D
= 10
A
11
-
V
V
(BR)G1-SS
gate 1-source breakdown voltage
V
G2-S
= 0; I
G1-S
= 10
A; I
D
= 0
11
-
V
V
(BR)G2-SS
gate 2-source breakdown voltage
V
G1-S
= V
DS
= 0; I
G2-S
= 10
A
11
-
V
V
G2-S (th)
gate 2-source threshold voltage
V
G1-S
= 9 V; V
DS
= 9 V; I
D
= 20
A
0.3
1.2
V
I
DSX
self-biasing drain current
V
G2-S
= 4 V; V
DS
= 9 V
8
16
mA
I
G1-SS
gate 1 cut-off current
V
G1-S
= 9 V; V
G2-S
= 0; I
D
= 0
-
20
nA
I
G2-SS
gate 2 cut-off current
V
G1-S
= V
DS
= 0; V
G2-S
= 9 V
-
20
nA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
y
fs
forward transfer admittance
pulsed; T
j
= 25
C
24
30
-
mS
C
ig1-ss
input capacitance at gate 1
f = 1 MHz
-
2.2
2.7
pF
C
ig2-ss
input capacitance at gate 2
f = 1 MHz
-
1.5
-
pF
C
oss
output capacitance
f = 1 MHz
-
1.3
-
pF
C
rss
reverse transfer capacitance f = 1 MHz
-
25
40
fF
F
noise figure
f = 800 MHz; Y
S
= Y
S opt
-
1.5
2.5
dB
G
p
power gain
G
S
= 2 mS; B
S
= B
S opt
; G
L
= 0.5 mS;
B
L
= B
L opt
; f = 200 MHz; see Fig.16
-
38
-
dB
G
S
= 3.3 mS; B
S
= B
S opt
; G
L
= 1 mS;
B
L
= B
L opt
; f = 800 MHz; see Fig.17
-
20
-
dB
X
mod
cross-modulation
input level for k = 1% at 0 dB AGC;
f
w
= 50 MHz; f
unw
= 60 MHz; see Fig.18
85
-
-
dB
V
input level for k = 1% at 40 dB AGC;
f
w
= 50 MHz; f
unw
= 60 MHz; see Fig.18
100
-
-
dB
V
1997 Dec 08
5
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1109; BF1109R; BF1109WR
Fig.5 Output characteristics; typical values.
V
G2-S
= 4 V.
T
j
= 25
C.
handbook, halfpage
0
10
25
0
5
10
15
20
2
4
6
8
MDA613
ID
(mA)
VDS (V)
VG1 = 1.6 V
1.3 V
1.2 V
1.1 V
1.5 V
1.4 V
1 V
Fig.6 Transfer characteristics; typical values.
V
DS
= 9 V.
T
j
= 25
C.
handbook, halfpage
0
40
20
30
10
0
0.5
2.5
MDA614
1
1.5
2
VG1 (V)
ID
(mA)
2 V
1 V
VG2-S = 4 V
3.5 V
2.5 V
1.5 V
3 V
Fig.7
Forward transfer admittance as a function
of drain current; typical values.
V
DS
= 9 V.
T
j
= 25
C.
handbook, halfpage
0
10
20
30
40
30
10
0
20
MDA615
ID (mA)
yfs
(mS)
3.5 V
3 V
2.5 V
2 V
VG2-S = 4 V
Fig.8
Drain current as a function of gate 2
voltage; typical values.
(1) V
DS
= 9 V.
(2) V
DS
= 7 V.
(3) V
DS
= 5 V.
(4) V
DS
= 3 V.
handbook, halfpage
0
16
8
12
4
0
1
5
MDA616
2
3
4
ID
(mA)
VG2-S (V)
(1)
(4)
(3)
(2)
PDF 
ZIP