Document Outline
- FEATURES
- APPLICATIONS
- DESCRIPTION
- PINNING
- QUICK REFERENCE DATA
- LIMITING VALUES
- THERMAL CHARACTERISTICS
- STATIC CHARACTERISTICS
- DYNAMIC CHARACTERISTICS
- PACKAGE OUTLINES
- DATA SHEET STATUS
- DEFINITIONS
- DISCLAIMERS
DATA SHEET
Product specification
Supersedes data of 1999 Dec 01
2000 Mar 29
DISCRETE SEMICONDUCTORS
BF1202; BF1202R; BF1202WR
N-channel dual-gate PoLo
MOS-FETs
2000 Mar 29
2
Philips Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
BF1202; BF1202R;
BF1202WR
FEATURES
Short channel transistor with high
forward transfer admittance to input
capacitance ratio
Low noise gain controlled amplifier
Partly internal self-biasing circuit to
ensure good cross-modulation
performance during AGC and good
DC stabilization.
APPLICATIONS
VHF and UHF applications with
3 to 9 V supply voltage, such as
digital and analogue television
tuners and professional
communications equipment.
DESCRIPTION
Enhancement type N-channel
field-effect transistor with source and
substrate interconnected. Integrated
diodes between gates and source
protect against excessive input
voltage surges. The BF1202,
BF1202R and BF1202WR are
encapsulated in the SOT143B,
SOT143R and SOT343R plastic
packages respectively.
PINNING
PIN
DESCRIPTION
1
source
2
drain
3
gate 2
4
gate 1
handbook, 2 columns
Top view
MSB014
1
2
3
4
Fig.1
Simplified outline
(SOT143B).
BF1202 marking code: LDp
handbook, 2 columns
Top view
MSB035
1
2
4
3
Fig.2
Simplified outline
(SOT143R).
BF1202R marking code: LEp
page
Top view
MSB842
2
1
4
3
Fig.3
Simplified outline
(SOT343R).
BF1202WR marking code: LE
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
DS
drain-source voltage
-
-
10
V
I
D
drain current
-
-
30
mA
P
tot
total power dissipation
-
-
200
mW
y
fs
forward transfer admittance
25
30
40
mS
C
ig1-ss
input capacitance at gate 1
-
1.7
2.2
pF
C
rss
reverse transfer capacitance
f = 1 MHz
-
15
30
fF
F
noise figure
f = 800 MHz
-
1.1
1.8
dB
X
mod
cross-modulation
input level for k = 1% at
40 dB AGC
100
105
-
dB
V
T
j
operating junction temperature
-
-
150
C
CAUTION
This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport
and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B.
2000 Mar 29
3
Philips Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
BF1202; BF1202R;
BF1202WR
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
Note
1. T
s
is the temperature of the soldering point of the source lead.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DS
drain-source voltage
-
10
V
I
D
drain current
-
30
mA
I
G1
gate 1 current
-
10
mA
I
G2
gate 2 current
-
10
mA
P
tot
total power dissipation
BF1202; BF1202R
T
s
113
C; note 1
-
200
mW
BF1202WR
T
s
119
C; note 1
-
200
mW
T
stg
storage temperature
-
65
+150
C
T
j
operating junction temperature
-
150
C
SYMBOL
PARAMETER
VALUE
UNIT
R
th j-s
thermal resistance from junction to soldering point
BF1202; BF1202R
185
K/W
BF1202WR
155
K/W
handbook, halfpage
0
50
(1)
(2)
Ts (
C)
Ptot
(mW)
100
200
250
0
200
150
150
100
50
MCD951
Fig.4 Power derating curve.
(1) BF1202WR.
(2) BF1202; BF1202R.
2000 Mar 29
4
Philips Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
BF1202; BF1202R;
BF1202WR
STATIC CHARACTERISTICS
T
j
= 25
C unless otherwise specified.
Note
1. R
G1
connects G
1
to V
GG
= 5 V.
DYNAMIC CHARACTERISTICS
Common source; T
amb
= 25
C; V
G2-S
= 4 V; V
DS
= 5 V; I
D
= 12 mA; unless otherwise specified.
Note
1. Measured in Fig.21 test circuit.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
(BR)DSS
drain-source breakdown voltage
V
G1-S
= V
G2-S
= 0; I
D
= 10
A
10
-
V
V
(BR)G1-SS
gate 1-source breakdown voltage
V
G2-S
= V
DS
= 0; I
G1-S
= 10 mA
6
-
V
V
(BR)G2-SS
gate 2-source breakdown voltage
V
G1-S
= V
DS
= 0; I
G2-S
= 10 mA
6
-
V
V
(F)S-G1
forward source-gate 1 voltage
V
G2-S
= V
DS
= 0; I
S-G1
= 10 mA
0.5
1.5
V
V
(F)S-G2
forward source-gate 2 voltage
V
G1-S
= V
DS
= 0; I
S-G2
= 10 mA
0.5
1.5
V
V
G1-S(th)
gate 1-source threshold voltage
V
G2-S
= 4 V; V
DS
= 5 V; I
D
= 100
A
0.3
1.0
V
V
G2-S(th)
gate 2-source threshold voltage
V
G1-S
= 5 V; V
DS
= 5 V; I
D
= 100
A
0.3
1.2
V
I
DSX
drain-source current
V
G2-S
= 4 V; V
DS
= 5 V; R
G1
= 120 k
;
note 1
8
16
mA
I
G1-SS
gate 1 cut-off current
V
G2-S
= V
DS
= 0; V
G1-S
= 5 V
-
50
nA
I
G2-SS
gate 2 cut-off current
V
G1-S
= V
DS
= 0; V
G2-S
= 4 V
-
20
nA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
y
fs
forward transfer admittance
pulsed; T
j
= 25
C
25
30
40
mS
C
ig1-ss
input capacitance at gate 1
f = 1 MHz
-
1.7
2.2
pF
C
ig2-ss
input capacitance at gate 2
f = 1 MHz
-
1
-
pF
C
oss
output capacitance
f = 1 MHz
-
0.85
-
pF
C
rss
reverse transfer capacitance f = 1 MHz
-
15
30
fF
F
noise figure
f = 10.7 MHz; G
S
= 20 mS; B
S
= 0
-
9
11
dB
f = 400 MHz; Y
S
= Y
S opt
-
0.9
1.5
dB
f = 800 MHz; Y
S
= Y
S opt
-
1.1
1.8
dB
G
tr
power gain
f = 200 MHz; G
S
= 2 mS; B
S
= B
S opt
;
G
L
= 0.5 mS; B
L
= B
L opt
-
34.5
-
dB
f = 400 MHz; G
S
= 2 mS; B
S
= B
S opt
;
G
L
= 1 mS; B
L
= B
L opt
-
30.5
-
dB
f = 800 MHz; G
S
= 3.3 mS; B
S
= B
S opt
;
G
L
= 1 mS; B
L
= B
L opt
-
26.5
-
dB
X
mod
cross-modulation
input level for k = 1%; f
w
= 50 MHz;
f
unw
= 60 MHz; note 1
at 0 dB AGC
90
-
-
dB
V
at 10 dB AGC
-
92
-
dB
V
at 40 dB AGC
100
105
-
dB
V
2000 Mar 29
5
Philips Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
BF1202; BF1202R;
BF1202WR
handbook, halfpage
0
2
20
0
4
8
12
16
0.4
0.8
1.2
1.6
VG1-S (V)
ID
(mA)
MCD952
VG2-S
=
4 V
2.5 V
3.5 V
3 V
2 V
1.5 V
1 V
Fig.5 Transfer characteristics; typical values.
V
DS
= 5 V.
T
j
= 25
C.
handbook, halfpage
0
10
24
0
8
16
2
VDS (V)
ID
(mA)
6
4
8
MCD953
VG1-S
=
1.5 V
1.4 V
1.2 V
1.3 V
1.1 V
1 V
0.9 V
Fig.6 Output characteristics; typical values.
V
G2-S
= 4 V.
T
j
= 25
C.
handbook, halfpage
0
2.5
100
0
20
40
60
80
0.5
1
1.5
2
VG1-S (V)
IG1
(
A)
MCD954
VG2-S
=
4 V
3.5 V
3 V
2.5 V
2 V
1.5 V
1 V
Fig.7
Gate 1 current as a function of gate 1
voltage; typical values.
V
DS
= 5 V.
T
j
= 25
C.
V
DS
= 5 V.
T
j
= 25
C.
handbook, halfpage
0
ID (mA)
4
20
40
30
10
0
20
8
12
16
MCD955
yfs
(mS)
3.5 V
2.5 V
3 V
2 V
VG2-S
=
4 V
Fig.8
Forward transfer admittance as a function
of drain current; typical values.
V
DS
= 5 V.
T
j
= 25
C.
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