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Philips Semiconductors

Product specification

FB2031

9-bit latched/registered/pass-thru Futurebus+ transceiver

1995 May 25

853-1714 15279

FEATURES

Latched, registered or straight through in
either A to B or B to A path

Drives heavily loaded backplanes with
equivalent load impedances down to 10

High drive 100mA BTL open collector
drivers on B-port

Allows incident wave switching in heavily
loaded backplane buses

Reduced BTL voltage swing produces less
noise and reduces power consumption

Built-in precision band-gap reference
provides accurate receiver thresholds and
improved noise immunity

Compatible with IEEE Futurebus+ or
proprietary BTL backplanes

Each BTL driver has a dedicated Bus GND
for a signal return

Controlled output ramp and multiple GND
pins minimize ground bounce

Glitch-free power up/power down operation

Low I

current

Tight output skew

Supports live insertion

QUICK REFERENCE DATA

SYMBOL

PARAMETER

TYPICAL

UNIT

PLH

PHL

Propagation delay
An to Bn

2.7

PLH

PHL

Propagation delay
Bn to An

4.4
4.2

Output capacitance (B0 Bn only)

Output current (B0 Bn only)

100

AIn to Bn
(outputs Low or High)

Supply current

Bn to AOn (outputs Low)

Bn to AOn (outputs High)

ORDERING INFORMATION

PACKAGE

COMMERCIAL RANGE

= 5V

10%; T

amb

= 0

C to +70

INDUSTRIAL RANGE

= 5V

10%; T

amb

= 40

C to +85

DRAWING

NUMBER

52-pin Plastic Quad Flat Pack (QFP)

FB2031BB

CD3206BB

SOT379-1

PIN CONFIGURATION

52 51 50 49 48 47 46

45 44 43 42 41 40

14 15

16 17 18 19

20 21

22 23 24 25 26

BUS GND

LOGIC GND

BG GND

BG V

OEA

BIAS V

9-Bit latched/registered transceiver

FB2031

52-lead PQFP

LOGIC GND

BUS GND

SEL0

OEB0

OEB1

TCK (option)

TMS (option)

BUS GND

TDO (option)

TDI (option)

SEL1

LCBA

LCAB

LOGIC GND

SG00060

Philips Semiconductors

Product specification

FB2031

9-bit latched/registered/pass-thru Futurebus+ transceiver

1995 May 25

DESCRIPTION

The FB2031 is a 9-bit latched/registered
transceiver featuring a latched, registered or
pass-thru mode in either the A-to-B or B-to-A
direction. The FB2031 is intended to provide
the electrical interface to a high performance
wired-OR bus.

The TTL-level side (A port) has a common
I/O. The common I/O, open collector B port
operates at BTL signal levels. The logic
element for data flow in each direction is
controlled by two mode select inputs (SEL0
and SEL1). A "00" configures latches in both
directions. A "10" configures thru mode in
both directions. A "01" configures register
mode in both directions. A "11" configures
register mode in the A-to-B direction and
latch mode in the B-to-A direction.

When configured in the buffer mode, the
inverse of the input data appears at the
output port. In the register mode, data is
stored on the rising edge of the appropriate
clock input (LCAB or LCBA). In the latch
mode, clock pins serve as transparent-Low
latch enables. Regardless of the mode, data
is inverted from input to output.

The 3-State A port is enabled by asserting a
High level on OEA. The B port has two output
enables, OEB0 and OEB1. Only when OEB0
is High and OEB1 is Low is the output
enabled.

When either OEB0 is Low or OEB1 is High,
the B port is inactive and is pulled to the level
of the pullup voltage. New data can be
entered in the register and latched modes or
can be retained while the associated outputs
are in 3-State (A port) or inactive (B port).

The B-port drivers are Low-capacitance open
collectors with controlled ramp and are
designed to sink 100mA. Precision band gap
references on the B-port insure very good
noise margins by limiting the switching
threshold to a narrow region centered at
1.55V.

The B-port interfaces to "Backplane
Transceiver Logic" (see the IEEE 1194.1 BTL
standard). BTL features low power
consumption by reducing voltage swing (1V
p-p, between 1V and 2V) and reduced
capacitive loading by placing an internal
series diode on the drivers. BTL also
provides incident wave switching, a necessity
for high performance backplanes.

Output clamps are provided on the BTL
outputs to further reduce switching noise.
The "V

" clamp reduces inductive ringing

effects during a Low-to-High transition. The
"V

" clamp is always active. The other

clamp, the "trapped reflection" clamp, clamps
out ringing below the BTL 0.5V V

level.

This clamp remains active for approximately
100ns after a High-to-Low transition.

To support live insertion, OEB0 is held Low
during power on/off cycles to insure glitch-
free B port drivers. Proper bias for B port
drivers during live insertion is provided by the
BIAS V pin when at a 5V level while V

Low. The BIAS V pin is a low current input
which will reverse-bias the BTL driver series
Schottky diode, and also bias the B port
output pins to a voltage between 1.62V and
2.1V. This bias function is in accordance with
IEEE BTL Standard 1194.1. If live insertion is
not a requirement, the BIAS V pin should be
tied to a V

pin.

The LOGIC GND and BUS GND pins are
isolated inside the package to minimize noise
coupling between the BTL and TTL sides.
These pins should be tied to a common
ground external to the package.

Each BTL driver has an associated BUS
GND pin that acts as a signal return path and
these BUS GND pins are internally isolated
from each other. In the event of a ground
return fault, a "hard" signal failure occurs
instead of a pattern dependent error that may
be infrequent and impossible to troubleshoot.

As with any high power device, thermal
considerations are critical. It is
recommended that airflow (300Ifpm)
and/or thermal mounting be used to
ensure proper junction temperature.

PACKAGE THERMAL CHARACTERISTICS

PARAMETER

CONDITION

52-PIN PLASTIC QFP

Still air

C/W

300 Linear feet per minute air flow

C/W

Thermally mounted on one side to heat sink

C/W

PIN DESCRIPTION

SYMBOL

PIN NUMBER

TYPE

NAME AND FUNCTION

A0 A8

50, 52, 2, 4, 6, 8, 10, 12, 14

I/O

BiCMOS data inputs/3-State outputs (TTL)

B0 B8

40, 38, 36, 34, 32,

30, 28, 26, 24

I/O

Data inputs/Open Collector outputs, High current drive (BTL)

OEB0

Input

Enables the B outputs when High

OEB1

Input

Enables the B outputs when Low

OEA

Input

Enables the A outputs when High

BUS GND

25, 27, 29, 31, 33,

35, 37, 39, 41

GND

Bus ground (0V)

LOGIC GND

51, 1, 3, 5, 7, 9, 11, 13

GND

Logic ground (0V)

23, 43, 49

Power

Positive supply voltage

BIAS V

Power

Live insertion pre-bias pin

BG V

Power

Band Gap threshold voltage reference

BG GND

GND

Band Gap threshold voltage reference ground

SEL0

Input

Mode select

SEL1

Input

Mode select

LCAB

Input

A to B clock/latch enable (transparent latch when Low)

LCBA

Input

B to A clock/latch enable (transparent latch when Low)

TMS

Input

Test Mode Select (optional, if not implemented then no connect)

TCK

Input

Test Clock (optional, if not implemented then no connect)

TDI

Input

Test Data In (optional, if not implemented then no connect)

TDO

Output

Test Data Out (optional, if not implemented then shorted to TDI)

Philips Semiconductors

Product specification

FB2031

9-bit latched/registered/pass-thru Futurebus+ transceiver

1995 May 25

FUNCTION TABLE

MODE

INPUTS

OUTPUTS

MODE

Bn*

OEB0

OEB1

OEA

LCAB

LCBA

SEL0

SEL1

An to Bn thru mode

input

H**

An to Bn thru mode

input

An to Bn transparent latch

input

H**

An to Bn transparent latch

input

An to Bn latch and read

input

H**

An to Bn latch and read

input

Bn outputs latched and read
(preconditioned latch)

latched

data

An to Bn register

input

H**

An to Bn register

input

Bn to An thru mode

Disable

input

Bn to An thru mode

Disable

input

Disable

input

Bn to An transparent latch

Disable

input

Bn to An transparent latch

Disable

input

Disable

input

Disable

input

Bn to An latch and read

Disable

input

Bn to An latch and read

Disable

input

Disable

input

An outputs latched and read

latched

data

(preconditioned latch)

latched

data

Bn to An register

Disable

input

Bn to An register

Disable

input

Disable Bn outputs

H**

Disable Bn outputs

H**

Disable An outputs

FUNCTION SELECT TABLE

MODE SELECTED

SEL0

SEL1

Thru mode

Latch mode (An to Bn)

Latch mode (Bn to An)

NOTES:
H

High voltage level

Low voltage level

Low voltage level one set-up time

prior to the Low-to-High LCXX transition
h

High voltage level one set-up time

prior to the Low-to-High LCXX transition

Don't care

High-impedance (OFF) state

Input not externally driven

Low-to-High transition

H** =

Goes to level of pull-up voltage

Bn* =

Precaution should be taken to

ensure B inputs do not float. If they do, they
are equal to Low state.
Disable = OEB0 is Low or OEB1 is High.

Philips Semiconductors

Product specification

FB2031

9-bit latched/registered/pass-thru Futurebus+ transceiver

1995 May 25

ABSOLUTE MAXIMUM RATINGS

Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.

SYMBOL

PARAMETER

RATING

UNIT

Supply voltage

-0.5 to +7.0

Input voltage

All inputs except B0 B8

-1.2 to +7.0

B0 B8

-1.2 to +3.5

Input current

-40 to +5.0

OUT

Voltage applied to output in High output state

-0.5 to +V

OUT

Current applied to output in Low output state

A0 A8

B0 B8

200

STG

Storage temperature

-65 to +150

RECOMMENDED OPERATING CONDITIONS (Industrial)

SYMBOL

PARAMETER

LIMITS

UNIT

MIN

TYP

MAX

Supply voltage

4.5

5.0

5.5

High-level input voltage

Except B0B8

2.0

B0 B8

1.62

1.55

Low-level input voltage

Except B0 B8

0.8

B0 B8

1.47

Input clamp current

Control inputs

-40

B0 B8 & A0 A8

-18

High-level output current

A0 A8

-3

Low-level output current

A0 A8

B0 B8

100

Off device input current

Except B0 B8,
V

= 0 to 5.5V, V

= 0V

100

Output capacitance of B port

amb

Operating free-air temperature range

+85

RECOMMENDED OPERATING CONDITIONS (Commercial)

SYMBOL

PARAMETER

LIMITS

UNIT

MIN

TYP

MAX

Supply voltage

4.5

5.0

5.5

High-level input voltage

Except B0B8

2.0

B0 B8

1.62

1.55

Low-level input voltage

Except B0 B8

0.8

B0 B8

1.47

Input clamp current

Control inputs

-40

B0 B8 & A0 A8

-18

High-level output current

A0 A8

-3

Low-level output current

A0 A8

B0 B8

100

Off device input current

Except B0 B8,
V

= 0 to 5.5V, V

= 0V

100

Output capacitance of B port

amb

Operating free-air temperature range

+70

Philips Semiconductors

Product specification

FB2031

9-bit latched/registered/pass-thru Futurebus+ transceiver

1995 May 25

DC ELECTRICAL CHARACTERISTICS (Industrial)

Over recommended operating free-air temperature range unless otherwise noted.

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNIT

MIN

TYP

MAX

High level output current

B0 B8

= MAX, V

= MIN, V

= 1.9V

100

OFF

Power-off output current

B0 B8

= 0.0V, V

= MAX, V

= MIN, V

= 1.9V

200

High-level output voltage

A0 A8

= MIN, V

= MAX, V

= MIN, I

= -24mA

2.0

= MIN, V

= MAX, V

= MIN, I

= -3mA

2.5

2.85

A0 A8

= MIN, V

= MAX, V

= MIN, I

= 24mA

0.5

Low-level output voltage

B0 B8

= MIN, V

= MAX, V

= MIN, I

= 80mA

.75

1.0

1.1

= MIN, V

= MAX, V

= MIN, I

= 100mA

1.15

= MIN, V

= MAX, V

= MIN, I

= 80mA

1.15

= MIN, V

= MAX, V

= MIN, I

= 4mA

0.5

Input clamp voltage

Control pins

= MIN, I

= I

-0.5

A0 A8
B0 Bn

= MIN, I

= -18mA

-1.2

Input current at maximum
input voltage

Except
B0B8

= MAX, V

= 0.5V or 5.5V

High-level input current

Except
B0B8

= MAX, V

= 2.7V

B0 B8

= MAX, V

= 1.9V

100

= MAX, V

= 3.5V

100

Low-level input current

Except
B0B8

= MAX, V

= 0.5V

-20

B0 B8

= MAX, V

= 0.75V

-100

+ I

OZH

Off-state I/O High current

A0 A8

= MAX, V

= 2.7V

+ I

OZL

Off-state I/O Low current

A0 A8

= MAX, V

= 0.5V

-50

Short-circuit output
current

A0 A8
only

= MAX, V

= 0.0V

-45

-150

An to Bn

= MAX, outputs Low or High

Bn to An

= MAX, outputs Low

Supply current (total)

Bn to An

= MAX, outputs High

CCZ

= MAX, outputs 3-State

Worst case

= MAX, all A and B outputs on

NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type.
2. All typical values are at V

= 5V, T

amb

= 25

3. Not more than one output should be shorted at a time. For testing I

, the use of high-speed test apparatus and/or sample-and-hold

techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I

tests should be performed last.

4. Due to test equipment limitations, actual test conditions are V

= 1.8V and V

= 1.3V for the B side.

5. For B port input voltage between 3 and 5 volts I

will be greater than 100

A, but the parts will continue to function normally.

6. B0 B8 clamps remain active for a minimum of 80ns following a High-to-Low transition.
7. Temperature range: 0 to +85

8. Temperature range: 40 to 0

Philips Semiconductors

Product specification

FB2031

9-bit latched/registered/pass-thru Futurebus+ transceiver

1995 May 25

DC ELECTRICAL CHARACTERISTICS (Commercial)

Over recommended operating free-air temperature range unless otherwise noted.

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNIT

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

High level output current

B0 B8

= MAX, V

= MIN, V

= 1.9V

100

OFF

Power-off output current

B0 B8

= 0.0V, V

= MAX, V

= MIN, V

= 1.9V

100

High level output voltage

= MIN, V

= MAX, V

= MIN, I

= -24mA

2.0

High-level output voltage

A0 A8

= MIN, V

= MAX, V

= MIN, I

= -3mA

2.5

2.85

A0 A8

= MIN, V

= MAX, V

= MIN, I

= 24mA

0.5

Low level output voltage

= MIN, V

= MAX, V

= MIN, I

= 80mA

.75

1.0

1.1

Low-level output voltage

B0 B8

= MIN, V

= MAX, V

= MIN, I

= 100mA

1.15

= MIN, V

= MAX, V

= MIN, I

= 4mA

0.5

Control pins

= MIN, I

= I

-0.5

Input clamp voltage

A0 A8
B0 Bn

= MIN, I

= -18mA

-1.2

Input current at maximum
input voltage

Except
B0B8

= MAX, V

= 0.0V or 5.5V

Hi h l

l i

Except
B0B8

= MAX, V

= 2.7V

High-level input current

= MAX, V

= 1.9V

100

B0 B8

= MAX, V

= 3.5V

100

Low-level input current

Except
B0B8

= MAX, V

= 0.5V

-20

B0 B8

= MAX, V

= 0.75V

-100

+ I

OZH

Off-state I/O High current

A0 A8

= MAX, V

= 2.7V

+ I

OZL

Off-state I/O Low current

A0 A8

= MAX, V

= 0.5V

-50

Short-circuit output
current

A0 A8
only

= MAX, V

= 0.0V

-45

-150

An to Bn

= MAX, outputs Low or High

Bn to An

= MAX, outputs Low

Supply current (total)

Bn to An

= MAX, outputs High

CCZ

= MAX, outputs 3-State

Worst case

= MAX, all A and B outputs on

NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type.
2. All typical values are at V

= 5V, T

amb

= 25

3. Not more than one output should be shorted at a time. For testing I

, the use of high-speed test apparatus and/or sample-and-hold

tests should be performed last.

4. Due to test equipment limitations, actual test conditions are V

= 1.8V and V

= 1.3V for the B side.

5. For B port input voltage between 3 and 5 volts I

will be greater than 100

A, but the parts will continue to function normally.

6. B0 B8 clamps remain active for a minimum of 80ns following a High-to-Low transition.

Philips Semiconductors

Product specification

FB2031

9-bit latched/registered/pass-thru Futurebus+ transceiver

1995 May 25

LIVE INSERTION SPECIFICATIONS

SYMBOL

PARAMETER

LIMITS

UNIT

SYMBOL

PARAMETER

MIN

NOM

MAX

UNIT

BIASV

Bias pin voltage

= 0 to 5.25V, Bn = 0 to 2.0V

4.5

5.5

BIASV

Bias pin DC current

= 0 to 4.75V, Bn = 0 to 2.0V,

Bias V = 4.5 to 5.5V

BIASV

Bias in DC current

= 4.5 to 5.5V, Bn = 0 to 2.0V,

Bias V = 4.5 to 5.5V

Bus voltage during prebias

B0 B8 = 0V, Bias V = 5.0V

1.62

2.1

Fall current during prebias

B0 B8 = 2V, Bias V = 4.5 to 5.5V

Rise current during prebias

B0 B8 = 1V, Bias V = 4.5 to 5.5V

-1

PEAK

Peak bus current during
insertion

= 0 to 5.25V, B0 B8 = 0 to 2.0V,

Bias V = 4.5 to 5.5V, OEB0 = 0.8V, t

= 2ns

OFF

Power up current

= 0 to 5.25V, OEB0 = 0.8V

100

OFF

Power u current

= 0 to 2.2V, OEB0 = 0 to 5V

100

Input glitch rejection

= 5.0V

1.35

1.0

AC ELECTRICAL CHARACTERISTICS (Industrial)

A PORT LIMITS

SYMBOL

PARAMETER

TEST

CONDITION

amb

= +25

C, V

= 5V,

= 50pF, R

= 500

amb

= 40 to +85

= 5V

10%,

= 50pF, R

= 500

UNIT

MIN

TYP

MAX

MIN

MAX

MAX

Maximum clock frequency

Waveform 4

120

150

100

MHz

PLH

PHL

Propagation delay (thru mode)
Bn to An

Waveform 1, 2

2.5
2.4

4.4
4.2

5.9
5.5

2.3
2.4

7.0
6.2

PLH

PHL

Propagation delay (transparent latch)
Bn to An

Waveform 1, 2

2.9
2.8

4.6
4.3

6.2
5.9

2.7
2.5

7.1
7.0

PLH

PHL

Propagation delay
LCBA to An

Waveform 1, 2

2.6
2.4

4.1
4.7

5.5
6.1

2.0
2.0

6.2
6.8

PLH

PHL

Propagation delay
SEL0 or SEL1 to An

Waveform 1, 2

1.5
1.7

3.8
3.9

5.2
6.0

1.2
1.5

6.2
6.5

PZH

PZL

Output enable time from High or Low
OEA to An

Waveform 5, 6

2.1
2.0

3.5
3.8

4.8
5.3

1.8
1.7

6.0
6.3

PHZ

PLZ

Output disable time to High or Low
OEA to An

Waveform 5, 6

1.9
1.7

3.4
3.2

4.8
4.8

1.6
1.5

5.5
5.5

TLH

THL

Output transition time, An Port
10% to 90%, 90% to 10%

Test Circuit and

Waveforms

3.0
1.7

7.5
4.0

(o)

Output to output skew for multiple
channels

Waveform 3

0.5

1.0

1.5

(p)

Pulse skew

PHL

PLH

MAX

Waveform 2

0.5

1.0

NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type.
2. All typical values are at V

= 5V, T

amb

= 25

3. Not more than one output should be shorted at a time. For testing I

, the use of high-speed test apparatus and/or sample-and-hold

tests should be performed last.

4. Due to test equipment limitations, actual test conditions are V

= 1.8V and V

= 1.3V for the B side.

5. For B port input voltage between 3 and 5 volts I

will be greater than 100

A, but the parts will continue to function normally.

6. B0 B8 clamps remain active for a minimum of 80ns following a High-to-Low transition.

Philips Semiconductors

Product specification

FB2031

9-bit latched/registered/pass-thru Futurebus+ transceiver

1995 May 25

AC ELECTRICAL CHARACTERISTICS (Industrial)

B PORT LIMITS

SYMBOL

PARAMETER

TEST

CONDITION

amb

= +25

C, V

= 5V,

= 30pF, R

= 16.5

amb

= 40 to +85

= 5V

10%,

= 30pF, R

= 16.5

UNIT

MIN

TYP

MAX

MIN

MAX

PLH

PHL

Propagation delay (thru mode)
An to Bn

Waveform 1, 2

1.0
1.0

3.0
2.7

5.0
4.0

1.5
1.5

5.7
4.5

PLH

PHL

Propagation delay (transparent latch)
An to Bn

Waveform 1, 2

1.0
1.0

3.2
3.1

5.0
4.2

1.5
1.5

5.5
5.0

PLH

PHL

Propagation delay
LCAB to Bn

Waveform 1, 2

2.0
1.5

4.0
4.0

5.5
5.5

1.5
1.5

6.5
6.0

PLH

PHL

Propagation delay
SEL0 or SEL1 to Bn

Waveform 1, 2

2.0
1.5

3.5
2.3

5.5
4.5

2.0
1.0

6.1
5.5

PZH

PZL

Enable/disable time
OEB0 or OEB1 to Bn

Waveform 1, 2

1.5
1.2

3.0
2.4

5.0
4.5

1.0
1.0

5.7
5.5

TLH

THL

Output transition time, Bn Port
(1.3V to 1.8V)

Test Circuit and

Waveforms

1.0
0.6

2.0
3.0

0.9
0.6

3.0
3.0

SK(o)

Output to output skew for multiple
channels

Waveform 3

1.0

0.4

1.6

(p)

Pulse skew

PHL

PLH

MAX

Waveform 2

0.3

1.0

1.5

NOTES:
1.

actual t

actual

for any data input to output path compared to any other data input to output path where N and M are either LH or

HL. Skew times are valid only under same test conditions (temperature, V

, loading, etc.).

2. t

(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal

duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).

Philips Semiconductors

Product specification

FB2031

9-bit latched/registered/pass-thru Futurebus+ transceiver

1995 May 25

AC ELECTRICAL CHARACTERISTICS (Commercial)

A PORT LIMITS

SYMBOL

PARAMETER

TEST

CONDITION

amb

= +25

C, V

= 5V,

= 50pF, R

= 500

amb

= 0 to +70

= 5V

10%,

= 50pF, R

= 500

UNIT

MIN

TYP

MAX

MIN

MAX

MAX

Maximum clock frequency

Waveform 4

120

150

100

MHz

PLH

PHL

Propagation delay (thru mode)
Bn to An

Waveform 1, 2

2.5
2.4

4.4
4.2

5.9
5.5

2.3
2.4

6.6
5.9

PLH

PHL

Propagation delay (transparent latch)
Bn to An

Waveform 1, 2

2.9
2.8

4.6
4.3

6.2
5.9

2.7
2.5

7.0
6.5

PLH

PHL

Propagation delay
LCBA to An

Waveform 1, 2

2.6
2.4

4.1
4.7

5.5
6.1

2.0
2.0

6.0
6.5

PLH

PHL

Propagation delay
SEL0 or SEL1 to An

Waveform 1, 2

1.5
1.7

3.8
3.9

5.2
6.0

1.2
1.5

6.0
6.5

PZH

PZL

Output enable time from High or Low
OEA to An

Waveform 5, 6

2.1
2.0

3.5
3.8

4.8
5.3

1.8
1.7

5.8
6.0

PHZ

PLZ

Output disable time to High or Low
OEA to An

Waveform 5, 6

1.9
1.7

3.4
3.2

4.8
4.8

1.6
1.5

5.4
5.4

TLH

THL

Output transition time, An Port
10% to 90%, 90% to 10%

Test Circuit and

Waveforms

2.0
1.0

7.5
3.5

(o)

Output to output skew for multiple
channels

Waveform 3

0.5

1.0

1.5

(p)

Pulse skew

PHL

PLH

MAX

Waveform 2

0.5

1.0

NOTES:
1.

actual t

actual

for any data input to output path compared to any other data input to output path where N and M are either LH or HL.

Skew times are valid only under same test conditions (temperature, V

, loading, etc.).

2. t

(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal

duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).

Philips Semiconductors

Product specification

FB2031

9-bit latched/registered/pass-thru Futurebus+ transceiver

1995 May 25

AC ELECTRICAL CHARACTERISTICS (Commercial)

B PORT LIMITS

SYMBOL

PARAMETER

TEST

CONDITION

amb

= +25

C, V

= 5V,

= 30pF, R

= 16.5

amb

= 0 to +70

= 5V

10%,

= 30pF, R

= 16.5

UNIT

MIN

TYP

MAX

MIN

MAX

PLH

PHL

Propagation delay (thru mode)
An to Bn

Waveform 1, 2

1.0
1.0

3.0
2.7

5.0
4.0

1.0
0.5

5.5
4.5

PLH

PHL

Propagation delay (transparent latch)
An to Bn

Waveform 1, 2

1.0
1.0

3.2
3.1

5.0
4.2

1.0
0.8

5.5
4.5

PLH

PHL

Propagation delay
LCAB to Bn

Waveform 1, 2

2.0
1.5

4.0
4.0

5.5
5.5

1.5
1.0

6.0
6.0

PLH

PHL

Propagation delay
SEL0 or SEL1 to Bn

Waveform 1, 2

2.0
1.5

3.5
2.3

5.5
4.5

2.0
1.0

6.0
5.0

PZH

PZL

Enable/disable time
OEB0 or OEB1 to Bn

Waveform 1, 2

1.5
1.5

3.0
2.4

5.0
4.5

1.0
0.8

5.5
5.5

TLH

THL

Output transition time, Bn Port
(1.3V to 1.8V)

Test Circuit and

Waveforms

1.0
0.6

2.0
3.0

1.0
0.6

2.3
2.3

SK(o)

Output to output skew for multiple
channels

Waveform 3

0.4

1.0

1.6

(p)

Pulse skew

PHL

PLH

MAX

Waveform 2

0.3

1.0

1.5

NOTES:
1.

actual t

actual

for any data input to output path compared to any other data input to output path where N and M are either LH or

HL. Skew times are valid only under same test conditions (temperature, V

, loading, etc.).

2. t

(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal

duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).

AC SETUP REQUIREMENTS (Industrial)

LIMITS

SYMBOL

PARAMETER

TEST

CONDITION

amb

= +25

C, V

= 5V,

amb

= 40 to +85

= 5V

10%,

UNIT

= 50pF (A side) / C

= 30pF (B side)

= 500

(A side) / R

= 16.5

(B side)

MIN

TYP

MAX

MIN

MAX

(H)

(L)

Setup time
An to LCAB

Waveform 4

1.0
1.0

1.5
1.0

(H)

(L)

Hold time
An to LCAB

Waveform 4

1.0
1.0

2.0
1.0

(H)

(L)

Setup time
Bn to LCBA

Waveform 4

2.0
2.0

3.0
3.0

(H)

(L)

Hold time
Bn to LCBA

Waveform 4

0.0
0.0

(H)

(L)

Pulse width, High or Low
LCAB or LCBA

Waveform 4

3.0
3.0

Philips Semiconductors

Product specification

FB2031

9-bit latched/registered/pass-thru Futurebus+ transceiver

1995 May 25

AC WAVEFORMS

ÍÍ

PZL

Input

Output

PLH

PHL

PLH

Output

An, Bn

tSK(o)

OEA

PLZ

VOL +0.3V

OEA

VOH -0.3V

PHZ

PZH

NOTE: VM = 1.55V for Bn, VM = 1.5V for all others.

Input

ÍÍ

ÍÍÍÍ

An, Bn

LCAB, LCBA

1/fMAX

w(L)

w(H)

The shaded areas indicate when the input is permitted to change for predictable output performance.

Waveform 1. Propagation Delay for Data

or Output Enable to Output

Waveform 2. Propagation Delay for Data

or Output Enable to Output

Waveform 3. Output to Output Skew

Waveform 4. Setup and Hold Times,

Pulse Widths and Maximum Frequency

Waveform 5. 3-State Output Enable Time to High Level

and Output Disable Time from High Level

Waveform 6. 3-State Output Enable Time to Low Level

and Output Disable Time from Low Level

(input)

(output)

SG00062

Philips Semiconductors

Product specification

FB2031

9-bit latched/registered/pass-thru Futurebus+ transceiver

1995 May 25

TEST CIRCUIT AND WAVEFORMS

2.5ns

2.0ns

500ns

INPUT PULSE REQUIREMENTS

Rep. Rate

Amplitude

TLH

THL

1MHz

3.0V

2.5ns

Input Pulse Definitions

VM = 1.55V for Bn, VM = 1.5V for all others.

VCC

Family

FB+

D.U.T.

PULSE

GENERATOR

7.0V

VIN

VOUT

Test Circuit for 3-State Outputs on A Port

TEST

SWITCH

SWITCH POSITION

PLZ,

PZL

All other

closed

open

DEFINITIONS:
R

= Load Resistor; see AC CHARACTERISTICS for value.

= Load capacitance includes jig and probe capacitance; see AC

CHARACTERISTICS for value.

= Termination resistance should be equal to Z

OUT

of pulse generators.

= Load capacitance includes jig and probe capacitance; see AC

CHARACTERISTICS for value.

= Pull up resistor; see AC CHARACTERISTICS for value.

90%

10%

90%

10%

90%

10%

90%

10%

NEGATIVE
PULSE

POSITIVE
PULSE

AMP (V)

LOW V

tTHL

)

tTLH

)

Low V

0.0V

tTLH

)

tTHL

)

AMP (V)

A Port

1MHz

2.0V

2.0ns

1.0V

B Port

D.U.T.

PULSE

GENERATOR

OUT

Test Circuit for Outputs on B Port

BIAS

2.0V (for R

= 9

)

2.1V (for R

= 16.5

)

SG00063

Philips Semiconductors

Product specification

FB2031

9-bit latched/registered/pass-thru Futurebus+ transceiver

1995 May 25

Definitions

Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381

print code

Date of release: 01-0006835

Document order number:

9397 750

Philips

Semiconductors

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

[1]

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

Data sheet status

[1]

Please consult the most recently issued datasheet before initiating or completing a design.

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