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Philips Semiconductors
Product specification
FB2033
8-bit latched/registered/pass-thru
Futurebus+ universal interface transceiver
1
1995 May 25
853-1717 15279
FEATURES
8-bit transceivers
Latched, registered or straight through in either A to B or B to A
path
Drives heavily loaded backplanes with equivalent load
impedances down to 10
.
High drive 100mA BTL Open Collector drivers on B-port
Allows incident wave switching in heavily loaded backplane buses
Reduced BTL voltage swing produces less noise and reduces
power consumption
Built-in precision band-gap reference provides accurate receiver
thresholds and improved noise immunity
Compatible with IEEE Futurebus+ or proprietary BTL backplanes
Each BTL driver has a dedicated Bus GND for a signal return
Controlled output ramp and multiple GND pins minimize ground
bounce
Glitch-free power up/power down operation
Low I
CC
current
Tight output skew
Supports live insertion
QUICK REFERENCE DATA
SYMBOL
PARAMETER
TYPICAL
UNIT
t
PLH
t
PHL
Propagation delay
AIn to Bn
3.0
3.0
ns
t
PLH
t
PHL
Propagation delay
Bn to AOn
4.3
4.1
ns
C
OB
Output capacitance (B0 Bn only)
6
pF
I
OL
Output current (B0 Bn only)
100
mA
I
CC
Supply current
AIn to Bn
(outputs Low or High)
24
mA
I
CC
Supply current
Bn to AOn (outputs Low)
45
mA
Bn to AOn (outputs High)
22
ORDERING INFORMATION
PACKAGES
COMMERCIAL RANGE
V
CC
= 5V
10%; T
amb
= 0
C to +70
C
DRAWING
NUMBER
52-pin Plastic Quad Flat Pack (QFP)
FB2033BB
SOT379-1
NOTE: Thermal mounting or forced air is recommended
PIN CONFIGURATION
OEB0
52 51 50 49 48 47 46
45 44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
28
27
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19
20
21 22 23 24 25 26
BUS GND
B1
BUS GND
B2
BUS GND
B3
BUS GND
B4
BUS GND
B5
BUS GND
B6
BUS GND
LOGIC GND
AO1
AO2
AO3
LOOPBACK
AI4
AI5
AO6
AO7
B7
AI1
AO0
OEA
LCBA
BIAS V
B0
LGOIC GND
LCAB
8-Bit Universal Transceiver
FB2033
52-lead PQFP
BG GND
OEB1
LOGIC GND
V
CC
AI2
AI3
AO4
AI6
LOGIC GND
AI7
SAB0
SAB1
V
CC
BUS GND
V
CC
AO5
AI0
SBA1
SBA0
BG V
CC
SG00068
Philips Semiconductors
Product specification
FB2033
8-bit latched/registered/pass-thru
Futurebus+ universal interface transceiver
1995 May 25
2
DESCRIPTION
The FB2033 is an 8-bit transceiver featuring a split input (AI) and
output (AO) bus on the TTL-level side.
The common I/O, open collector B port operates at BTL signal
levels. The logic element for data flow in each direction is controlled
by two pairs of mode select inputs (SBA0 and SBA1 for B-to-A,
SAB0 and SAB1 for A-to-B). It can be configured as a buffer, a
register, or a D-type latch.
When configured in the buffer mode, the inverse of the input data
appears at the output port. In the flip-flop mode, data is stored on
the rising edge of the appropriate clock input (LCAB or LCBA). In the
latch mode, clock pins serve as transparent-High latch enables.
Regardless of the mode, data is inverted from input to output.
Data flow in the B-to-A direction, regardless of the logic element
selected, is further controlled by the Loopback input. When the
Loopback input is High the output of the selected A-to-B logic
element (not inverted) becomes the B-to-A input.
The 3-State AO port is enabled by asserting a High level on OEA.
The B port has two output enables, OEB0 and OEB1. Only when
OEB0 is High and OEB1 is Low is the output enabled. When either
OEB0 is Low or OEB1 is High, the B-port is inactive and is pulled to
the level of the pull-up voltage. New data can be entered in the
flip-flop and latched modes or can be retained while the associated
outputs are in 3-State (AO port) or inactive (B port).
The B-port drivers are Low-capacitance open collectors with
controlled ramp and are designed to sink 100mA. Precision band
gap references on the B-port ensure very good noise margins by
limiting the switching threshold to a narrow region centered at 1.55V.
The B-port interfaces to "Backplane Transceiver Logic" (see the
IEEE 1194.1 BTL standard). BTL features low power consumption
by reducing voltage swing (1V p-p, between 1V and 2V) and
reduced capacitive loading by placing an internal series diode on the
drivers. BTL also provides incident wave switching, a necessity for
high performance backplanes.
Output clamps are provided on the BTL outputs to further reduce
switching noise. The "V
OH
" clamp reduces inductive ringing effects
during a Low-to-High transition. The "V
OH
" clamp is always active.
The other clamp, the "trapped reflection" clamp, clamps out ringing
below the BTL 0.5V V
OL
level. This clamp remains active for
approximately 100ns after a High-to-Low transition.
To support live insertion, OEB0 is held Low during power on/off
cycles to ensure glitch- free B port drivers. Proper bias for B port
drivers during live insertion is provided by the BIAS V pin when at a
5V level while V
CC
is Low. The BIAS V pin is a low current input
which will reverse-bias the BTL driver series Schottky diode, and
also bias the B port output pins to a voltage between 1.62V and
2.1V. This bias function is in accordance with IEEE BTL Standard
1194.1. If live insertion is not a requirement, the BIAS V pin should
be tied to a V
CC
pin.
The LOGIC GND and BUS GND pins are isolated inside the
package to minimize noise coupling between the BTL and TTL
sides. These pins should be tied to a common ground external to the
package.
Each BTL driver has an associated BUS GND pin that acts as a
signal return path and these BUS GND pins are internally isolated
from each other. In the event of a ground return fault, a "hard" signal
failure occurs instead of a pattern dependent error that may be very
infrequent and impossible to trouble- shoot.
As with any high power device thermal considerations are critical. It
is recommended that airflow (300Ifpm) and/or thermal mounting be
used to ensure proper junction temperature.
PIN DESCRIPTION
SYMBOL
PIN NUMBER
TYPE
NAME AND FUNCTION
AI0 AI7
50, 52, 3, 5, 8, 10, 12, 15
Input
Data inputs (TTL)
AO0 AO7
51, 2, 4, 6, 9, 11, 14, 16
Output
3-State outputs (TTL)
B0 B7
40, 38, 36, 34, 32, 30, 28, 26
I/O
Data inputs/Open Collector outputs, High current drive (BTL)
OEB0
23
Input
Enables the B outputs when High
OEB1
24
Input
Enables the B outputs when Low
OEA
43
Input
Enables the AO outputs when High
BUS GND
39, 37, 35, 33, 31, 29, 27, 25
GND
Bus ground (0V)
LOGIC GND
1, 13, 17, 49
GND
Logic ground (0V)
V
CC
18, 22, 48
Power
Positive supply voltage
BIAS V
41
Power
Live insertion pre-bias pin
BG V
CC
44
Power
Band Gap threshold voltage reference
BG GND
42
GND
Band Gap threshold voltage reference ground
SABn
20, 21
Input
Mode select from AI to B
SBAn
45, 46
Input
Mode select from B to AO
LCAB
47
Input
A-to-B clock/latch enable (transparent latch when High)
LCBA
19
Input
B-to-A clock/latch enable (transparent latch when High)
Loopback
7
Input
Enables loopback function when High (from AIn to AOn)
Philips Semiconductors
Product specification
FB2033
8-bit latched/registered/pass-thru
Futurebus+ universal interface transceiver
1995 May 25
3
FUNCTION TABLE
MODE
INPUTS
OUTPUTS
MODE
AIn
Bn*
OEB0
OEB1
OEA
LCAB
LCBA
SAB
1
0
SBA
1
0
AOn
Bn
AIn to Bn thru mode
L
--
H
L
L
X
X
LL
XX
Z
H**
AIn to Bn thru mode
H
--
H
L
L
X
X
LL
XX
Z
L
AIn to Bn transparent latch
L
--
H
L
L
H
X
HX
XX
Z
H**
AIn to Bn transparent latch
H
--
H
L
L
H
X
HX
XX
Z
L
AIn to Bn latch and read
l
--
H
L
L
X
HX
XX
Z
H**
AIn to Bn latch and read
h
--
H
L
L
X
HX
XX
Z
L
AIn to Bn register
L
--
H
L
L
X
LH
XX
Z
H**
AIn to Bn register
H
--
H
L
L
X
LH
XX
Z
L
Bn outputs latched and read
(preconditioned latch)
X
--
H
L
L
L
X
HX
XX
Z
latched
data
Bn to AOn thru mode
X
L
L
H
H
X
X
XX
LL
H
input
Bn to AOn thru mode
X
H
L
H
H
X
X
XX
LL
L
input
Bn to AOn transparent latch
X
L
L
H
H
X
H
XX
HX
H
input
Bn to AOn transparent latch
X
H
L
H
H
X
H
XX
HX
L
input
Bn to AOn latch and read
X
l
L
H
H
X
XX
HX
H
input
Bn to AOn latch and read
X
h
L
H
H
X
XX
HX
L
input
Bn to AOn register
X
L
L
H
H
X
XX
LH
H
input
Bn to AOn register
X
H
L
H
H
X
XX
LH
L
input
AOn outputs latched and read
(preconditioned latch)
X
X
L
H
H
X
L
XX
HX
latched
data
X
Disable Bn outputs
X
X
L
X
X
X
X
XX
XX
X
H**
Disable Bn outputs
X
X
X
H
X
X
X
XX
XX
X
H**
Disable AOn outputs
X
X
X
X
L
X
X
XX
XX
Z
X
FUNCTION SELECT TABLE
MODE SELECTED
SXX1
SXX0
Thru mode
L
L
Register mode
L
H
Latch mode
H
X
NOTES:
H
=
High voltage level
L
=
Low voltage level
h
=
High voltage level one set-up time prior to the High-to-Low LCXX transition
l
=
Low voltage level one set-up time prior to the High-to-Low LCXX transition
X
=
Don't care
Z
=
High-impedance (OFF) state
--
=
Input not externally driven
=
Low-to-High transition
=
High-to-Low transition
H** =
Goes to level of pull-up voltage
Bn* =
Precaution should be taken to ensure B inputs do not float. If they do, they are equal to Low state.
NOTE: In Loopback mode (Loopback = High), AIn inputs are routed to the AOn outputs. The Bn inputs are blocked out.
Philips Semiconductors
Product specification
FB2033
8-bit latched/registered/pass-thru
Futurebus+ universal interface transceiver
1995 May 25
4
LOGIC DIAGRAM
23
24
OEB0
OEB1
20
SAB0
21
SAB1
47
LCAB
D
En
D
Clk
50
AIn
40
Bn
1 of 8 cells
19
45
46
43
D
En
D
Clk
51
LCBA
SBA0
SBA1
OEA
AOn
1 of 8 cells
42
BGGnd
BGref
52,
2, 5,
8, 10,
12, 15
2, 4, 6, 9,
11, 14, 16
38,
36, 34,
32, 30,
28, 26
7
Loopback
SG00069
Philips Semiconductors
Product specification
FB2033
8-bit latched/registered/pass-thru
Futurebus+ universal interface transceiver
1995 May 25
5
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free-air temperature range.
SYMBOL
PARAMETER
RATING
UNIT
V
CC
Supply voltage
-0.5 to +7.0
V
V
IN
Input voltage
All inputs except B0 Bn
-1.2 to +7.0
V
V
IN
Input voltage
B0 Bn
-1.2 to +3.5
V
I
IN
Input current
-40 to +5.0
mA
V
OUT
Voltage applied to output in High output state
-0.5 to +V
CC
V
I
OUT
Current applied to output in Low output state
AO0 AOn
48
mA
I
OUT
Current applied to output in Low output state
B0 Bn
200
mA
T
STG
Storage temperature
-65 to +150
C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN
NOM
MAX
UNIT
V
CC
Supply voltage
4.5
5.0
5.5
V
V
IH
High-level input voltage
Except B0 Bn
2.0
V
V
IH
High-level input voltage
B0 Bn
1.62
1.55
V
V
IL
Low-level input voltage
Except B0 Bn
0.8
V
V
IL
Low-level input voltage
B0 Bn
1.47
V
I
IK
Input clamp current
Except B0 Bn
-40
mA
I
IK
Input clamp current
B0 Bn
-50
mA
I
OH
High-level output current
AO0 AOn
-3
mA
I
OL
Low-level output current
AO0 AOn
24
mA
I
OL
Low-level output current
B0 Bn
100
mA
I
IA
Off device input current
Except B0 Bn,
V
I
= 0 to 5.5V, V
CC
= 0V
100
A
C
OB
Output capacitance of B port
6
7
pF
T
amb
Operating free-air temperature range
0
+70
C
Philips Semiconductors
Product specification
FB2033
8-bit latched/registered/pass-thru
Futurebus+ universal interface transceiver
1995 May 25
6
DC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range unless otherwise noted.
SYMBOL
PARAMETER
TEST CONDITIONS
1
LIMITS
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
1
MIN
TYP
2
MAX
UNIT
I
OH
High level output current
B0 Bn
V
CC
= MAX, V
IL
= MAX, V
IH
= MIN, V
OH
= 1.9V
100
A
I
OFF
Power-off output current
B0 Bn
V
CC
= 0.0V, V
IL
= MAX, V
IH
= MIN, V
OH
= 1.9V
100
A
V
OH
High-level output voltage
AO0 AOn
4
V
CC
= MIN, V
IL
= MAX, V
IH
= MIN, I
OH
= -3mA
2.5
2.85
V
V
OL
Low-level output voltage
AO0 AOn
4
V
CC
= MIN, V
IL
= MAX, V
IH
= MIN, I
OL
= 24mA
0.5
V
V
OL
Low-level output voltage
B0 Bn
V
CC
= MIN, V
IL
= MAX, V
IH
= MIN, I
OL
= 100mA
.75
1.0
1.15
V
OL
B0 Bn
V
CC
= MIN, V
IL
= MAX, V
IH
= MIN, I
OL
= 4mA
0.5
V
IK
Input clamp voltage
Except
B0Bn
V
CC
= MIN, I
I
= I
IK
-0.5
V
V
IK
Input clamp voltage
B0 Bn
V
CC
= MIN, I
I
= I
IK
6
0.3
V
B0 Bn
V
CC
= MIN, I
I
= -18mA
-1.2
I
I
Input current at maximum
input voltage
Except
B0Bn
V
CC
= MAX, V
I
= 0.0V or 5.5V
50
A
I
IH
High-level input current
Except
B0Bn
V
CC
= MAX, V
I
= 2.7V, Bn = AIn = 0V
20
A
I
IH
High-level input current
B0 Bn
V
CC
= MAX, V
I
= 1.9V
100
A
B0 Bn
V
CC
= MAX, V
I
= 3.5V
5
100
mA
I
IL
Low-level input current
Except
B0Bn
V
CC
= MAX, V
I
= 0.5V
-20
A
I
IL
Low-level input current
B0 Bn
V
CC
= MAX, V
I
= 0.75V
-100
A
I
OZH
Off-state output current
AO0 AOn
V
CC
= MAX, V
O
= 2.7V
50
A
I
OZL
Off-state output current
AO0 AOn
V
CC
= MAX, V
O
= 0.5V
-50
A
I
OS
Short-circuit output
current
3
AO0 AOn
only
V
CC
= MAX, V
O
= 0.0V
-45
-150
mA
I
CC
Supply current (total)
AIn to Bn
V
CC
= MAX, outputs Low or High
24
50
mA
I
CC
Supply current (total)
Bn to AOn
V
CC
= MAX, outputs Low
45
75
mA
CC
Bn to AOn
V
CC
= MAX, outputs High
22
44
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25
C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
4. Due to test equipment limitations, actual test conditions are V
IH
= 1.8V and V
IL
= 1.3V for the B side.
5. For B port input voltage between 3 and 5 volts I
IH
will be greater than 100
A, but the parts will continue to function normally.
6. B0 B7 clamps remain active for a minimum of 80ns following a High-to-Low transition.
Philips Semiconductors
Product specification
FB2033
8-bit latched/registered/pass-thru
Futurebus+ universal interface transceiver
1995 May 25
7
LIVE INSERTION SPECIFICATIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN
NOM
MAX
UNIT
V
BIASV
Bias pin voltage
V
CC
= 0 to 5.25V, Bn = 0 to 2.0V
4.5
5.5
V
I
BIASV
Bias pin DC current
V
CC
= 0 to 4.75V, Bn = 0 to 2.0V,
Bias V = 4.5 to 5.5V
1
mA
I
BIASV
Bias pin DC current
V
CC
= 4.5 to 5.5V, Bn = 0 to 2.0V,
Bias V = 4.5 to 5.5V
10
A
V
Bn
Bus voltage during pre-bias
B0 B8 = 0V, Bias V = 5.0V
1.62
2.1
V
I
LM
Fall current during pre-bias
B0 B8 = 2V, Bias V = 4.5 to 5.5V
1
A
I
HM
Rise current during pre-bias
B0 B8 = 1V, Bias V = 4.5 to 5.5V
-1
A
I
Bn
PEAK
Peak bus current during
insertion
V
CC
= 0 to 5.25V, B0 B8 = 0 to 2.0V,
Bias V = 4.5 to 5.5V, OEB0 = 0.8V, t
r
= 2ns
10
mA
I
OL
OFF
Power up current
V
CC
= 0 to 5.25V, OEB0 = 0.8V
100
A
I
OL
OFF
Power up current
V
CC
= 0 to 2.2V, OEB0 = 0 to 5V
100
A
t
GR
Input glitch rejection
V
CC
= 5.0V
1.0
1.35
ns
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST
CONDITION
A PORT LIMITS
UNIT
SYMBOL
PARAMETER
TEST
CONDITION
T
amb
= +25
C, V
CC
= 5V,
C
L
= 50pF, R
L
= 500
T
amb
= 0 to 70
C,
V
CC
= 5V
10%,
C
L
= 50pF, R
L
= 500
UNIT
MIN
TYP
MAX
MIN
MAX
f
MAX
Maximum clock frequency
Waveform 4
100
150
100
MHz
t
PLH
t
PHL
Propagation delay (thru mode)
Bn to AOn
Waveform 1, 2
2.2
2.0
4.3
4.1
6.0
6.0
2.0
1.8
7.0
7.0
ns
t
PLH
t
PHL
Propagation delay (transparent latch)
Bn to AOn
Waveform 1, 2
1.5
2.4
4.5
4.4
6.5
6.5
1.0
2.0
7.5
7.5
ns
t
PLH
t
PHL
Propagation delay
LCBA to AOn
Waveform 1, 2
2.0
2.2
3.8
4.3
5.5
6.0
1.8
1.7
6.0
6.5
ns
t
PLH
t
PHL
Propagation delay
SBAn to AOn
Waveform 1, 2
1.4
1.4
2.9
3.1
5.0
5.5
1.0
1.0
6.0
6.5
ns
t
PLH
t
PHL
Propagation delay (Loopback mode)
AIn to AOn
Waveform 1, 2
2.0
2.0
3.8
3.9
6.0
6.0
2.8
2.3
7.0
7.0
ns
t
PLH
t
PHL
Propagation delay (Loopback mode)
Loopback to AOn
Waveform 1, 2
1.2
1.2
3.4
3.2
5.0
5.5
1.0
1.0
6.0
6.5
ns
t
PZH
t
PZL
Output enable time from High or Low
OEA to AOn
Waveform 5, 6
1.0
2.6
3.1
4.0
5.1
5.5
1.0
2.4
5.5
5.8
ns
t
PHZ
t
PLZ
Output disable time to High or Low
OEA to AOn
Waveform 5, 6
1.0
1.0
3.5
3.3
5.0
4.6
1.7
1.7
5.6
5.2
ns
t
TLH
t
THL
Output transition time, AOn Port
10% to 90%, 90% to 10%
Test Circuit and
Waveforms
2.0
2.0
5.0
5.0
ns
t
SK
(o)
Output to output skew, A port
1
Waveform 3
0.5
1.0
1.5
ns
t
SK
(p)
Pulse skew 2
t
PHL
t
PLH
MAX
Waveform 2
0.3
1.0
1.5
ns
NOTES:
1. Bn to AOn propagation delays are extended for 5 nanoseconds following B port excursions above 3.1 volts.
2.
t
PN
actual t
PM
actual
for any data input to output path compared to any other data input to output path where N and M are either LH or HL.
Skew times are valid only under same test conditions (temperature, V
CC
, loading, etc.).
3. t
SK
(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal
duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).
Philips Semiconductors
Product specification
FB2033
8-bit latched/registered/pass-thru
Futurebus+ universal interface transceiver
1995 May 25
8
AC ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL
PARAMETER
TEST
CONDITION
B PORT LIMITS
UNIT
SYMBOL
PARAMETER
TEST
CONDITION
T
amb
= +25
C, V
CC
= 5V,
C
D
= 30pF, R
U
= 9
T
amb
= 0 to 70
C,
V
CC
= 5V
10%,
C
D
= 30pF, R
U
= 9
UNIT
MIN
TYP
MAX
MIN
MAX
t
PLH
t
PHL
Propagation delay (thru mode)
AIn to Bn
Waveform 1, 2
1.2
1.0
2.9
2.9
4.3
4.4
1.0
1.0
4.8
4.6
ns
t
PLH
t
PHL
Propagation delay (transparent latch)
AIn to Bn
Waveform 1, 2
1.4
1.0
3.1
3.3
4.5
4.8
1.0
1.0
5.1
5.1
ns
t
PLH
t
PHL
Propagation delay
LCAB to Bn
Waveform 1, 2
2.7
2.2
4.4
5.1
5.7
6.6
2.4
2.0
6.4
7.1
ns
t
PLH
t
PHL
Propagation delay
SABn to Bn
Waveform 1, 2
1.8
1.0
3.6
3.3
5.0
4.9
1.4
1.0
5.7
5.2
ns
t
PZH
t
PZL
Enable/disable time
OEB0 or OEB1 to Bn
Waveform 1, 2
1.4
1.0
3.0
3.1
4.5
5.0
1.0
1.0
5.0
5.6
ns
V/
t
Output transition rate, Bn Port
20% to 80%, 80% to 20%
Test Circuit and
Waveforms
0.4
1.2
V/ns
t
SK
(o)
Output to output skew, B port
1
Waveform 3
0.8
1.5
2.0
ns
t
SK
(p)
Pulse skew 2
t
PHL
t
PLH
MAX
Waveform 2
0.3
1.5
ns
SYMBOL
PARAMETER
TEST CONDITION
R
U
= 16.5
R
U
= 16.5
UNIT
t
PLH
t
PHL
Propagation delay (thru mode)
AIn to Bn
Waveform 1, 2
1.2
1.0
3.0
3.0
4.4
4.5
1.0
1.0
4.9
4.7
ns
t
PLH
t
PHL
Propagation delay (transparent latch)
AIn to Bn
Waveform 1, 2
1.4
1.0
3.2
3.4
4.6
4.9
1.0
1.0
5.2
5.2
ns
t
PLH
t
PHL
Propagation delay
LCAB to Bn
Waveform 1, 2
2.7
2.2
4.5
5.2
5.8
6.7
2.4
2.0
6.5
7.2
ns
t
PLH
t
PHL
Propagation delay
SABn to Bn
Waveform 1, 2
1.8
1.0
3.7
3.4
5.1
5.0
1.4
1.0
5.8
5.3
ns
t
PZH
t
PZL
Enable/disable time
OEB0 or OEB1 to Bn
Waveform 1, 2
1.4
1.0
3.1
3.2
4.6
5.1
1.0
1.0
5.1
5.7
ns
V/
t
Output transition rate, Bn Port
20% to 80%, 80% to 20%
Test Circuit and
Waveforms
0.2
0.6
V/ns
t
SK
(o)
Output to output skew, B port
1
Waveform 3
0.5
1.0
1.5
ns
t
SK
(p)
Pulse skew
2
t
PHL
t
PLH
MAX
Waveform 2
0.3
1.0
1.5
ns
NOTES:
1.
t
PN
actual t
PM
actual
for any data input to output path compared to any other data input to output path where N and M are either LH or
HL. Skew times are valid only under same test conditions (temperature, V
CC
, loading, etc.).
2. t
SK
(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal
duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).
Philips Semiconductors
Product specification
FB2033
8-bit latched/registered/pass-thru
Futurebus+ universal interface transceiver
1995 May 25
9
AC SETUP REQUIREMENTS
SYMBOL
PARAMETER
TEST
CONDITION
LIMITS
UNIT
SYMBOL
PARAMETER
TEST
CONDITION
T
amb
= +25
C, V
CC
= 5V
T
amb
= 0 to 70
C,
V
CC
= 5V
10%
UNIT
SYMBOL
PARAMETER
TEST
CONDITION
C
L
= 50pF (A side) / C
D
= 30pF (B side)
R
L
= 500
(A side) / R
U
= 9
(B side)
UNIT
MIN
TYP
MAX
MIN
MAX
t
s
(H)
t
s
(L)
Setup time
AIn to LCAB or Bn to LCBA
Waveform 4
3.0
3.0
4.0
4.0
ns
t
h
(H)
t
h
(L)
Hold time
AIn to LCAB or Bn to LCBA
Waveform 4
1.0
1.0
1.3
1.3
ns
t
w
(H)
t
w
(L)
Pulse width, High or Low
LCAB or LCBA
Waveform 4
3.0
3.0
4.0
4.0
ns
SYMBOL
PARAMETER
TEST
CONDITION
C
L
= 50pF (A side) / C
D
= 30pF (B side)
R
L
= 500
(A side) / R
U
= 16.5
(B side)
UNIT
t
s
(H)
t
s
(L)
Setup time
AIn to LCAB or Bn to LCBA
Waveform 4
3.0
3.0
4.0
4.0
ns
t
h
(H)
t
h
(L)
Hold time
AIn to LCAB or Bn to LCBA
Waveform 4
1.0
1.0
1.3
1.3
ns
t
w
(H)
t
w
(L)
Pulse width, High or Low
LCAB or LCBA
Waveform 4
3.0
3.0
4.0
4.0
ns
AC WAVEFORMS
VM
t
s
t
PZL
Input
Output
VM
VM
VM
VM
t
PLH
t
PHL
VM
VM
VM
VM
t
PHL
t
PLH
Output
AIn, Bn
AOn, Bn
VM
VM
tSK(o)
AOn
OEA
VM
VM
t
PLZ
VM
VOL +0.3V
AOn
OEA
VM
VM
VM
VOH -0.3V
OV
t
PHZ
t
PZH
Input
AIn, Bn
LCAB, LCBA
VM
VM
1/fMAX
t
h
t
s
t
h
t
w(L)
t
w(H)
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
Waveform 1. Propagation Delay for Data
or Output Enable to Output
Waveform 2. Propagation Delay for Data
or Output Enable to Output
Waveform 3. Output to Output Skew
Waveform 4. Setup and Hold Times,
Pulse Widths and Maximum Frequency
Waveform 5. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
Waveform 6. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
SG00070
Philips Semiconductors
Product specification
FB2033
8-bit latched/registered/pass-thru
Futurebus+ universal interface transceiver
1995 May 25
10
TEST CIRCUIT AND WAVEFORMS
2.5ns
2.0ns
500ns
500ns
INPUT PULSE REQUIREMENTS
Rep. Rate
Amplitude
t
TLH
t
THL
1MHz
3.0V
2.5ns
Input Pulse Definitions
VM = 1.55V for Bn, VM = 1.5V for all others.
VCC
Family
FB+
D.U.T.
PULSE
GENERATOR
7.0V
RL
RL
CL
RT
VIN
VOUT
Test Circuit for 3-State Outputs on A Port
TEST
SWITCH
SWITCH POSITION
t
PLZ,
t
PZL
All other
closed
open
DEFINITIONS:
R
L
= Load Resistor; see AC CHARACTERISTICS for value.
C
L
= Load capacitance includes jig and probe capacitance; see AC
CHARACTERISTICS for value.
R
T
= Termination resistance should be equal to Z
OUT
of pulse generators.
C
D
= Load capacitance includes jig and probe capacitance; see AC
CHARACTERISTICS for value.
R
U
= Pull up resistor; see AC CHARACTERISTICS for value.
tW
90%
VM
10%
90%
VM
10%
90%
VM
10%
90%
VM
10%
NEGATIVE
PULSE
POSITIVE
PULSE
AMP (V)
LOW V
LOW V
tTHL
(t
f
)
tTLH
(t
r
)
tW
t
W
Low V
0.0V
tTLH
(t
r
)
tTHL
(t
f
)
AMP (V)
A Port
1MHz
2.0V
2.0ns
1.0V
B Port
V
CC
D.U.T.
PULSE
GENERATOR
R
U
C
D
R
T
V
IN
V
OUT
Test Circuit for Outputs on B Port
BIAS
V
2.0V (for R
U
= 9
)
2.1V (for R
U
= 16.5
)
SG00063
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