Philips
Semiconductors
FBL2031
9-bit BTL 3.3V latched/registered/pass-thru
Futurebus+ transceiver
Product specification
Supersedes data of 1998 Sep 04
2000 Apr 18
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
FBL2031
9-bit BTL 3.3V latched/registered/pass-thru
Futurebus+ transceiver
2
2000 Apr 18
853-2118 23499
FEATURES
Latched, registered or straight through in either A to B or B to A path
Drives heavily loaded backplanes with equivalent load
impedances down to 10
.
High drive 100mA BTL open collector drivers on B-port
Allows incident wave switching in heavily loaded backplane buses
Reduced BTL voltage swing produces less noise and reduces
power consumption
Built-in precision band-gap reference provides accurate receiver
thresholds and improved noise immunity
Compatible with IEEE Futurebus+ or proprietary BTL backplanes
Each BTL driver has a dedicated Bus GND for a signal return
Controlled output ramp and multiple GND pins minimize ground
bounce
Glitch-free power up/power down operation
Low I
CC
current
Tight output skew
Supports live insertion
Pins for the optional JTAG boundary scan function are provided
High density packaging in plastic Quad Flatpack
5V compatible I/O on A-port
DESCRIPTION
The FBL2031 is a 9-bit latched/registered transceiver featuring a
latched, registered or pass-thru mode in either the A-to-B or B-to-A
direction.
The FBL2031 is intended to provide the electrical interface to a high
performance wired-OR bus.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
TYPICAL
UNIT
t
PLH
t
PHL
Propagation delay
An to Bn
2.7
ns
t
PLH
t
PHL
Propagation delay
Bn to An
4.4
4.2
ns
C
O
Output capacitance (B0 Bn only)
6
pF
I
OL
Output current (B0 Bn only)
100
mA
AIn to Bn (outputs Low or High)
11
I
CC
Supply current
Bn to AOn (outputs Low)
22
mA
Bn to AOn (outputs High)
18
ORDERING INFORMATION
PACKAGE
V
CC
= 3.3V
10%; T
amb
= 40
C to +85
C
DWG No.
52-pin Plastic Quad Flat Pack (PQFP)
FBL2031BB
SOT379-1
Philips Semiconductors
Product specification
FBL2031
9-bit BTL 3.3V latched/registered/pass-thru
Futurebus+ transceiver
2000 Apr 18
3
PIN CONFIGURATION
52 51 50 49 48 47 46
45 44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
28
27
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15
16 17 18 19
20 21
22 23 24 25 26
BUS GND
B1
BUS GND
B2
BUS GND
B3
BUS GND
B4
BUS GND
B5
BUS GND
B6
BUS GND
LOGIC GND
A2
A3
A4
LOGIC GND
A5
A6
A7
LOGIC GND
BG GND
B7
BG V
CC
A1
A0
OEA
BIAS V
B0
V
CC
V
CC
9-Bit latched/registered transceiver
FBL2031
52-lead PQFP
LOGIC GND
BUS GND
SEL0
OEB0
B8
A8
OEB1
TCK (option)
TMS (option)
BUS GND
V
CC
TDO (option)
TDI (option)
SEL1
LCBA
LCAB
LOGIC GND
LOGIC GND
LOGIC GND
LOGIC GND
SG00087
PIN DESCRIPTION
SYMBOL
PIN NUMBER
TYPE
NAME AND FUNCTION
A0 A8
50, 52, 2, 4, 6, 8, 10, 12, 14
I/O
BiCMOS data inputs/3-State outputs (TTL)
B0 B8
40, 38, 36, 34, 32,
30, 28, 26, 24
I/O
Data inputs/Open Collector outputs, High current drive (BTL)
OEB0
46
Input
Enables the B outputs when High
OEB1
45
Input
Enables the B outputs when Low
OEA
47
Input
Enables the A outputs when High
BUS GND
25, 27, 29, 31, 33,
35, 37, 39, 41
GND
Bus ground (0V)
LOGIC GND
51, 1, 3, 5, 7, 9, 11, 13
GND
Logic ground (0V)
V
CC
23, 43, 49
Power
Positive supply voltage
BIAS V
48
Power
Live insertion pre-bias pin
BG V
CC
17
Power
Band Gap threshold voltage reference
BG GND
19
GND
Band Gap threshold voltage reference ground
SEL0
20
Input
Mode select
SEL1
15
Input
Mode select
LCAB
18
Input
A to B clock/latch enable (transparent latch when Low)
LCBA
16
Input
B to A clock/latch enable (transparent latch when Low)
TMS
42
Input
Test Mode Select (optional, if not implemented then no connect)
TCK
44
Input
Test Clock (optional, if not implemented then no connect)
TDI
22
Input
Test Data In (optional, if not implemented then no connect)
TDO
21
Output
Test Data Out (optional, if not implemented then shorted to TDI)
Philips Semiconductors
Product specification
FBL2031
9-bit BTL 3.3V latched/registered/pass-thru
Futurebus+ transceiver
2000 Apr 18
4
DESCRIPTION
The TTL-level side (A port) has a common I/O. The common I/O,
open collector B port operates at BTL signal levels. The logic
element for data flow in each direction is controlled by two mode
select inputs (SEL0 and SEL1). A "00" configures latches in both
directions. A "10" configures thru mode in both directions. A "01"
configures register mode in both directions. A "11" configures
register mode in the A-to-B direction and latch mode in the B-to-A
direction.
When configured in the buffer mode, the inverse of the input data
appears at the output port. In the register mode, data is stored on
the rising edge of the appropriate clock input (LCAB or LCBA). In the
latch mode, clock pins serve as transparent-Low latch enables.
Regardless of the mode, data is inverted from input to output.
The 3-State A port is enabled by asserting a High level on OEA. The
B port has two output enables, OEB0 and OEB1. Only when OEB0
is High and OEB1 is Low is the output enabled.
When either OEB0 is Low or OEB1 is High, the B port is inactive
and is pulled to the level of the pull-up voltage. New data can be
entered in the register and latched modes or can be retained while
the associated outputs are in 3-State (A port) or inactive (B port).
The B-port drivers are Low-capacitance open collectors with
controlled ramp and are designed to sink 100mA. Precision band
gap references on the B-port insure very good noise margins by
limiting the switching threshold to a narrow region centered at 1.55V.
The B-port interfaces to "Backplane Transceiver Logic" (see the
IEEE 1194.1 BTL standard). BTL features low power consumption
by reducing voltage swing (1V p-p, between 1V and 2V) and
reduced capacitive loading by placing an internal series diode on the
drivers. BTL also provides incident wave switching, a necessity for
high performance backplanes.
Output clamps are provided on the BTL outputs to further reduce
switching noise. The "V
OH
" clamp reduces inductive ringing effects
during a Low-to-High transition. The "V
OH
" clamp is always active.
The other clamp, the "trapped reflection" clamp, clamps out ringing
below the BTL 0.5V V
OL
level. This clamp remains active for
approximately 100ns after a High-to-Low transition.
To support live insertion, OEB0 is held Low during power on/off
cycles to insure glitch- free B port drivers. Proper bias for B port
drivers during live insertion is provided by the BIAS V pin when at a
3.3V level while V
CC
is Low. The BIAS V pin is a low current input
which will reverse-bias the BTL driver series Schottky diode, and
also bias the B port output pins to a voltage between 1.62V and
2.1V. This bias function is in accordance with IEEE BTL Standard
1194.1. If live insertion is not a requirement, the BIAS V pin should
be tied to a V
CC
pin.
The LOGIC GND and BUS GND pins are isolated inside the
package to minimize noise coupling between the BTL and TTL
sides. These pins should be tied to a common ground external to the
package.
Each BTL driver has an associated BUS GND pin that acts as a
signal return path and these BUS GND pins are internally isolated
from each other. In the event of a ground return fault, a "hard" signal
failure occurs instead of a pattern dependent error that may be
infrequent and impossible to troubleshoot.
As with any high power device, thermal considerations are critical. It
is recommended that airflow (300Ifpm) and/or thermal mounting be
used to ensure proper junction temperature.
PACKAGE THERMAL CHARACTERISTICS
PARAMETER
CONDITION
52-PIN PLASTIC QFP
ja
Still air
80
C/W
ja
300 Linear feet per minute air flow
58
C/W
jc
Thermally mounted on one side to heat sink
20
C/W
Philips Semiconductors
Product specification
FBL2031
9-bit BTL 3.3V latched/registered/pass-thru
Futurebus+ transceiver
2000 Apr 18
5
FUNCTION TABLE
MODE
INPUTS
OUTPUTS
MODE
An
Bn*
OEB0
OEB1
OEA
LCAB
LCBA
SEL0
SEL1
An
Bn
An to Bn thru mode
L
--
H
L
L
X
X
H
L
input
H**
An to Bn thru mode
H
--
H
L
L
X
X
H
L
input
L
An to Bn transparent latch
L
--
H
L
L
L
X
L
L
input
H**
An to Bn transparent latch
H
--
H
L
L
L
X
L
L
input
L
An to Bn latch and read
l
--
H
L
L
X
L
L
input
H**
An to Bn latch and read
h
--
H
L
L
X
L
L
input
L
Bn outputs latched and read
(preconditioned latch)
X
--
H
L
X
H
X
L
L
X
latched
data
An to Bn register
l
--
H
L
L
X
X
H
input
H**
An to Bn register
h
--
H
L
L
X
X
H
input
L
Bn to An thru mode
--
L
Disable
H
X
X
H
L
H
input
Bn to An thru mode
--
H
Disable
H
X
X
H
L
L
input
--
L
Disable
H
X
L
L
L
H
input
Bn to An transparent latch
--
H
Disable
H
X
L
L
L
L
input
Bn to An transparent latch
--
L
Disable
H
X
L
H
H
H
input
--
H
Disable
H
X
L
H
H
L
input
--
l
Disable
H
X
L
L
H
input
Bn to An latch and read
--
h
Disable
H
X
L
L
L
input
Bn to An latch and read
--
l
Disable
H
X
H
H
H
input
--
h
Disable
H
X
H
H
L
input
An outputs latched and read
--
X
X
X
H
X
H
L
L
latched
data
X
(preconditioned latch)
--
X
X
X
H
X
H
H
H
latched
data
X
Bn to An register
--
l
Disable
H
X
L
H
H
input
Bn to An register
--
h
Disable
H
X
L
H
L
input
Disable Bn outputs
X
X
L
X
X
X
X
X
X
X
H**
Disable Bn outputs
X
X
X
H
X
X
X
X
X
X
H**
Disable An outputs
X
X
X
X
L
X
X
X
X
Z
X
FUNCTION SELECT TABLE
MODE SELECTED
SEL0
SEL1
Thru mode
H
L
Register mode (An to Bn)
X
H
Latch mode (An to Bn)
L
L
Register mode (Bn to An)
L
H
Latch mode (Bn to An)
L
L
Latch mode (Bn to An)
H
H
NOTES:
H
=
High voltage level
L
=
Low voltage level
l
=
Low voltage level one set-up time prior to the Low-to-High
LCXX transition
h
=
High voltage level one set-up time prior to the Low-to-High
LCXX transition
X
=
Don't care
Z
=
High-impedance (OFF) state
--
=
Input not externally driven
=
Low-to-High transition
H** =
Goes to level of pull-up voltage
Bn* =
Precaution should be taken to ensure B inputs do not float.
If they do, they are equal to Low state.
Disable =
OEB0 is Low or OEB1 is High.
Philips Semiconductors
Product specification
FBL2031
9-bit BTL 3.3V latched/registered/pass-thru
Futurebus+ transceiver
2000 Apr 18
6
LOGIC DIAGRAM
Decode
Out
In
46
45
OEB0
OEB1
47
OEA
14
A8
D
Q
Clk
24
B8
38
18
LCAB
20
SEL0
28
30
32
34
36
BTL
TMS
TCK
TDI
TDO
42
44
22
21
(JTAG Boundary Scan pins)
LOGIC GND
=
1, 3, 5, 7, 9, 11, 13, 51
BUS GND
=
25, 27, 29, 31, 33, 35, 37, 39, 41
BIAS V
=
48
VCC
=
23, 43, 49
BG VCC
=
17
BG GND
=
19
D
Q
E
MUX
A
B
Q
D
MUX
A
B
26
B7
12
A7
MUX
A
B
52
10
8
6
4
2
TTL
A1
MUX
A
B
MUX
A
B
B1
40
50
MUX
A
B
MUX
A
B
B0
D
Q
Clk
D
Q
E
D
Q
Clk
D
Q
E
D
Q
Clk
D
Q
E
D
Q
Clk
D
Q
E
D
Q
E
D
Q
E
D
Q
Clk
D
Q
Clk
D
Q
E
15
SEL1
16
LCBA
D
Q
Clk
MUX
A
B
A0
SG00061
Philips Semiconductors
Product specification
FBL2031
9-bit BTL 3.3V latched/registered/pass-thru
Futurebus+ transceiver
2000 Apr 18
7
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free-air temperature range.
SYMBOL
PARAMETER
RATING
UNIT
V
CC
Supply voltage
0.5 to +4.6
V
V
Input voltage
AI0 AI6, OEB0, OEBn, OEAn
0.5 to +7.0
V
V
IN
Input voltage
B0 B8
0.5 to +3.5
I
IN
Input current
V
IN
t
0
50
V
OUT
Voltage applied to output in High output state
0.5 to +7.0
V
I
O
Current applied to output in
AO0 AO8
64, 64
mA
I
OUT
Low output state/High output state
B0 B8
200
T
STG
Storage temperature
65 to +150
C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
COMMERCIAL LIMITS
V
CC
= 3.3V
10%;
T
amb
= 40 to +85
C
UNIT
MIN
TYP
MAX
V
CC
Supply voltage
3.0
3.3
3.6
V
V
High level input voltage
Except B0B8
2.0
V
V
IH
High-level input voltage
B0 B8
1.62
1.55
V
Low level input voltage
Except B0B8
0.8
V
V
IL
Low-level input voltage
B0 B8
1.47
I
IK
Input clamp current
18
mA
I
OH
High-level output current
AO0 AO8
32
mA
I
O
Low level output current
AO0 AO8
+32
mA
I
OL
Low-level output current
B0 B8
100
C
OB
Output capacitance on B port
6
7
pF
T
amb
Operating free-air temperature range
0
+70
C
LIVE INSERTION SPECIFICATIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
V
BIASV
Bias pin voltage
Voltage difference between the Bias voltage
and V
CC
after the PCB is plugged in.
0.5
V
I
S
Bias pin (I
BIASV
) input
V
CC
= 0 V, Bias V = 3.6V
1.2
mA
I
BIASV
(
BIASV
)
DC current
V
CC
= 3.3V, Bias V = 3.6V
10
A
V
Bn
Bus voltage during prebias
B0 B8 = 0V, Bias V = 3.3V
1.62
2.1
V
I
LM
Fall current during prebias
B0 B8 = 2V, Bias V = 1.3 to 2.5V
1
A
I
HM
Rise current during prebias
B0 B8 = 1V, Bias V = 3 to 3.6V
1
A
I
Bn
PEAK
Peak bus current during
insertion
V
CC
= 0 to 3.3V, B0 B8 = 0 to 2.0V,
Bias V = 2.7 to 3.6V, OEB0 = 0.8V, t
r
= 2ns
10
mA
I
O
OFF
Power up current
V
CC
= 0 to 3.3V, OEB0 = 0.8V
100
A
I
OL
OFF
Power up current
V
CC
= 0 to 1.2V, OEB0 = 0 to 5V
100
A
t
GR
Input glitch rejection
V
CC
= 3.3V
1.0
1.35
ns
Philips Semiconductors
Product specification
FBL2031
9-bit BTL 3.3V latched/registered/pass-thru
Futurebus+ transceiver
2000 Apr 18
8
DC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range unless otherwise noted.
SYMBOL
PARAMETER
TEST CONDITIONS
1
LIMITS
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
1
MIN
TYP
2
MAX
UNIT
I
OH
High level output current
B0 B8
V
CC
= MAX, V
IL
= MAX, V
OH
= 1.9V
100
A
I
O
Power off output current
B0
B8
V
CC
= 0V, V
IL
= MAX, V
OH
= 1.9V
100
A
I
OFF
Power-off output current
B0 B8
V
CC
= 0V, V
IL
= MAX, V
OH
= 1.9V @ 85
C
300
A
Hi h l
l
t
t
3
V
CC
= MIN to MAX
V
CC
0.2
V
V
OH
High-level output
voltage
AO0 AO8
3
V
CC
= MIN; I
OH
= -8mA
2.4
V
voltage
V
CC
= MIN; I
OH
= -32mA
2.0
V
AO0
AO8
3
V
CC
= MIN; I
OL
= 16mA
0.4
V
V
O
Low level output voltage
AO0 AO8
3
V
CC
= MIN; I
OL
= 32mA
0.5
V
V
OL
Low-level output voltage
B0 B8
V
CC
= MIN, I
OL
= 4mA
0.5
V
V
CC
= MIN, I
OL
= 100mA
0.75
1.0
1.20
V
V
IK
Input clamp voltage
V
CC
= MIN, I
I
= I
IK
= 18mA
0.85
1.2
V
Control pins
V
CC
= 3.6V; V
I
= V
CC
or GND
1.0
I
I
Input leakage current
Control/
AI0 AI8
V
CC
= 0V or 3.6V; V
I
= 5.5V
10
A
I
g
AI0 AI8
V
CC
= 3.6V; V
I
= V
CC
1
Note 4
V
CC
= 3.6V; V
I
= 0V
5
V
CC
= MAX, V
I
= 1.9V
100
A
I
IH
High-level input current
B0 B8
V
CC
= MAX, V
I
= 3.5V, note 5
100
mA
V
CC
= MAX, V
I
= 3.75V @ 40
C
100
mA
I
IL
Low-level input current
B0 B8
V
CC
= MAX, V
I
= 0.75V
100
A
I
OZH
Off-state output current
AO0 AO8
V
CC
= MAX, V
O
=3V
5
A
I
OZL
Off-state output current
AO0 AO8
V
CC
= MAX, V
O
= 0.5V
5
A
I
CCH
B to A
V
CC
= MAX, outputs High
18
32
mA
I
CCL
B to A
V
CC
= MAX, outputs Low
22
37
mA
I
CC
Supply current (total)
I
CCH
A to B
V
CC
= MAX, outputs High
11
16
mA
I
CCL
A to B
V
CC
= MAX, outputs Low
11
16
mA
I
CCZ
V
CC
= MAX
18
32
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type.
2. All typical values are at V
CC
= 3.3V, T
A
= 25
C.
3. Due to test equipment limitations, actual test conditions are V
IH
= 1.8V and V
IL
= 1.3V for the B side.
4. Unused pins are at V
CC
or GND.
5. For B port input voltage between 3 and 5 volt; I
IH
will be greater than 100mA but the part will continue to function normally (clamping circuit
is active). This is not a tested condition.
Philips Semiconductors
Product specification
FBL2031
9-bit BTL 3.3V latched/registered/pass-thru
Futurebus+ transceiver
2000 Apr 18
9
AC ELECTRICAL CHARACTERISTICS
B TO A SPECIFICATIONS
SYMBOL
PARAMETER
TEST
CONDITION
T
amb
= +25
C,
V
CC
= 3.3V,
T
amb
= 40 to +85
C,
V
CC
= 3.3V
10%,
UNIT
MIN
TYP
MAX
MIN
MAX
f
MAX
Maximum clock frequency
Waveform 4
120
150
MHz
t
PLH
t
PHL
Propagation delay (thru mode)
Bn to An
Waveform 1, 2
2.8
3.0
4.3
4.5
5.9
6.0
2.2
2.6
6.8
7.3
ns
t
PLH
t
PHL
Propagation delay (transparent latch)
Bn to An
Waveform 1, 2
2.8
3.4
4.9
5.0
7.0
6.6
1.8
2.8
8.4
7.8
ns
t
PLH
t
PHL
Propagation delay
LCBA to An (latch)
Waveform 1, 2
7.7
7.5
10.2
10.1
13.0
12.9
6.1
6.1
15.6
15.4
ns
t
PLH
t
PHL
Propagation delay
LCBA to An (register)
Waveform 1, 2
2.7
3.0
4.2
4.5
5.7
6.1
2.1
2.4
6.7
6.9
ns
t
PLH
t
PHL
Propagation delay
SEL0 or SEL1 to An (inverting)
Waveform 1, 2
2.9
1.9
5.8
5.8
9.1
10.4
2.2
1.2
10.5
11.6
ns
t
PLH
t
PHL
Propagation delay
SEL0 or SEL1 to An (non-inverting)
Waveform 1, 2
2.0
2.8
5.9
5.6
10.3
8.8
1.4
2.2
12.3
10.0
ns
t
PZH
t
PHZ
Output enable time from High or Low
OEA to An
Waveform 5, 6
3.0
4.0
4.4
5.6
5.7
7.3
2.6
3.2
6.6
8.3
ns
t
PZL
t
PLZ
Output disable time to High or Low
OEA to An
Waveform 5, 6
2.6
1.4
4.0
2.6
5.4
3.7
2.1
1.0
6.0
4.4
ns
t
TLH
t
THL
Output transition time, An Port
10% to 90%, 90% to 10%
Test Circuit and
Waveforms
0.2
0.1
2.0
1.2
ns
t
SK
(o)
Output to output skew for multiple
channels
1
Waveform 3
0.5
1.0
1.5
ns
t
SK
(p)
Pulse skew
2
t
PHL
t
PLH
MAX
Waveform 2
0.5
1.0
1.5
ns
NOTES:
1.
t
PN
actual t
PM
actual
for any data input to output path compared to any other data input to output path where N and M are either LH or HL.
Skew times are valid only under same test conditions (temperature, V
CC
, loading, etc.). t
SK
(0) compares t
PLH
on a given path to t
PLH
on
any other path or compares t
PHL
on a given path to t
PHL
on any other path.
2. t
SK
(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal
duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).
Philips Semiconductors
Product specification
FBL2031
9-bit BTL 3.3V latched/registered/pass-thru
Futurebus+ transceiver
2000 Apr 18
10
AC ELECTRICAL CHARACTERISTICS
A TO B 9
LOAD SPECIFICATIONS
SYMBOL
PARAMETER
TEST
CONDITION
T
amb
= +25
C,
V
CC
= 3.3V,
T
amb
= 40 to +85
C,
V
CC
= 3.3V
10%,
UNIT
MIN
TYP
MAX
MIN
MAX
t
PLH
t
PHL
Propagation delay (thru latch)
An to Bn
Waveform 1, 2
1.4
1.3
2.6
2.5
3.8
3.8
1.0
1.0
4.9
4.2
ns
t
PLH
t
PHL
Propagation delay (transparent latch)
An to Bn
Waveform 1, 2
1.7
2.0
2.9
3.5
4.2
5.0
1.0
1.5
5.4
5.7
ns
t
PLH
t
PHL
Propagation delay
LCAB to Bn (latch)
Waveform 1, 2
8.8
8.4
11.6
11.0
14.5
13.7
6.7
6.7
17.9
16.6
ns
t
PLH
t
PHL
Propagation delay
LCAB to Bn (register)
Waveform 1, 2
2.3
2.5
3.6
4.0
5.0
5.4
1.4
1.9
6.2
6.4
ns
t
PLH
t
PHL
Propagation delay
SEL0 or SEL1 to Bn (inverting)
Waveform 1, 2
2.3
1.3
3.8
4.8
5.5
8.8
1.2
1.0
7.0
9.6
ns
t
PLH
t
PHL
Propagation delay
SEL0 or SEL1 to Bn (non-inverting)
Waveform 1, 2
2.0
2.6
4.4
4.3
7.2
6.1
1.1
1.7
8.5
7.6
ns
t
PLH
t
PHL
OEBn to Bn
Waveform 1, 2
1.2
1.9
2.9
3.3
4.8
4.7
1.0
1.2
5.8
6.4
ns
t
TLH
t
THL
Output transition time, Bn Port
(1.3V to 1.8V)
Test Circuit and
Waveforms
1.2
0.4
3.0
1.5
ns
t
SK
(o)
Output to output skew for multiple
channels
1
Waveform 3
0.4
1.0
2.0
ns
t
SK
(p)
Pulse skew
2
t
PHL
t
PLH
MAX
Waveform 2
0.3
1.0
1.5
ns
NOTES:
1.
t
PN
actual t
PM
actual
for any data input to output path compared to any other data input to output path where N and M are either LH or
HL. Skew times are valid only under same test conditions (temperature, V
CC
, loading, etc.). t
SK
(0) compares t
PLH
on a given path to t
PLH
on any other path or compares t
PHL
on a given path to t
PHL
on any other path.
2. t
SK
(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal
duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).
Philips Semiconductors
Product specification
FBL2031
9-bit BTL 3.3V latched/registered/pass-thru
Futurebus+ transceiver
2000 Apr 18
11
AC ELECTRICAL CHARACTERISTICS
A TO B 16.5
LOAD SPECIFICATIONS
SYMBOL
PARAMETER
TEST
CONDITION
T
amb
= +25
C,
V
CC
= 3.3V,
T
amb
= 40 to +85
C,
V
CC
= 3.3V
10%,
UNIT
MIN
TYP
MAX
MIN
MAX
t
PLH
t
PHL
Propagation delay (thru latch)
An to Bn
Waveform 1, 2
1.4
1.2
2.7
2.4
3.9
3.6
1.0
1.0
5.0
4.0
ns
t
PLH
t
PHL
Propagation delay (transparent latch)
An to Bn
Waveform 1, 2
1.8
2.0
3.0
3.2
4.2
4.7
1.0
1.4
5.6
5.5
ns
t
PLH
t
PHL
Propagation delay
LCAB to Bn (latch)
Waveform 1, 2
8.6
8.0
11.4
10.6
14.2
13.3
6.5
6.4
17.5
16.1
ns
t
PLH
t
PHL
Propagation delay
LCAB to Bn (register)
Waveform 1, 2
2.2
2.3
3.5
3.7
4.8
5.1
1.2
1.7
6.1
5.9
ns
t
PLH
t
PHL
Propagation delay
SEL0 or SEL1 to Bn (inverting)
Waveform 1, 2
2.6
1.4
4.5
4.4
6.7
7.7
1.5
1.1
8.1
8.4
ns
t
PLH
t
PHL
Propagation delay
SEL0 or SEL1 to Bn (non-inverting)
Waveform 1, 2
2.2
2.3
4.5
4.0
6.9
5.8
1.4
1.5
8.2
6.9
ns
t
PLH
t
PHL
OEB0 to Bn
Waveform 1, 2
1.8
1.7
3.1
2.9
4.4
4.2
1.0
1.0
5.8
6.0
ns
t
TLH
t
THL
Output transition time, Bn Port
(1.3V to 1.8V)
Test Circuit and
Waveforms
1.2
0.4
3.0
1.5
ns
t
SK
(o)
Output to output skew for multiple
channels
1
Waveform 3
0.5
1.0
2.0
ns
t
SK
(p)
Pulse skew
2
t
PHL
t
PLH
MAX
Waveform 2
0.5
1.0
1.5
ns
NOTES:
1.
t
PN
actual t
PM
actual
for any data input to output path compared to any other data input to output path where N and M are either LH or
HL. Skew times are valid only under same test conditions (temperature, V
CC
, loading, etc.). t
SK
(0) compares t
PLH
on a given path to t
PLH
on any other path or compares t
PHL
on a given path to t
PHL
on any other path.
2. t
SK
(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal
duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).
Philips Semiconductors
Product specification
FBL2031
9-bit BTL 3.3V latched/registered/pass-thru
Futurebus+ transceiver
2000 Apr 18
12
AC SETUP REQUIREMENTS (Commercial)
LIMITS
SYMBOL
PARAMETER
TEST
T
amb
= +25
C, V
CC
= 3.3V,
T
amb
= 40 to +85
C,
V
CC
= 3.3V
10%,
UNIT
SYMBOL
PARAMETER
CONDITION
C
L
= 50pF (A side) / C
D
= 30pF (B side)
R
L
= 500
(A side) / R
U
= 16.5
(B side)
UNIT
MIN
TYP
MIN
t
s
(H)
t
s
(L)
Setup time
An to LCAB
Waveform 4
1.3
1.3
1.5
1.5
ns
t
h
(H)
t
h
(L)
Hold time
An to LCAB
Waveform 4
1.0
1.0
1.0
1.0
ns
t
s
(H)
t
s
(L)
Setup time
Bn to LCBA
Waveform 4
5.0
4.0
6.0
4.5
ns
t
h
(H)
t
h
(L)
Hold time
Bn to LCBA
Waveform 4
0.0
0.0
0.0
0.0
ns
t
w
(H)
t
w
(L)
Pulse width, High or Low
LCAB or LCBA
Waveform 4
3.0
3.0
3.0
3.0
ns
AC WAVEFORMS
VM
t
s
t
PZL
Input
Output
VM
VM
VM
VM
t
PLH
t
PHL
VM
VM
VM
VM
t
PHL
t
PLH
Output
An, Bn
An, Bn
VM
VM
tSK(o)
An
OEA
VM
VM
t
PLZ
VM
VOL +0.3V
An
OEA
VM
VM
VM
VOH -0.3V
OV
t
PHZ
t
PZH
NOTE: VM = 1.55V for Bn, VM = 1.5V for all others.
Input
An, Bn
LCAB, LCBA
VM
VM
1/fMAX
t
h
t
s
t
h
t
w(L)
t
w(H)
The shaded areas indicate when the input is permitted to change for predictable output performance.
Waveform 1. Propagation Delay for Data
or Output Enable to Output
Waveform 2. Propagation Delay for Data
or Output Enable to Output
Waveform 3. Output to Output Skew
Waveform 4. Setup and Hold Times,
Pulse Widths and Maximum Frequency
Waveform 5. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
Waveform 6. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
t
w
(input)
t
w
(output)
SG00062
Philips Semiconductors
Product specification
FBL2031
9-bit BTL 3.3V latched/registered/pass-thru
Futurebus+ transceiver
2000 Apr 18
13
TEST CIRCUIT AND WAVEFORMS
2.5ns
2.0ns
500ns
500ns
INPUT PULSE REQUIREMENTS
Rep. Rate
Amplitude
t
TLH
t
THL
1MHz
3.0V
2.5ns
Input Pulse Definitions
VM = 1.55V for Bn, VM = 1.5V for all others.
VCC
Family
FB+
D.U.T.
PULSE
GENERATOR
7.0V
RL
RL
CL
RT
VIN
VOUT
Test Circuit for 3-State Outputs on A Port
TEST
SWITCH
SWITCH POSITION
t
PLZ,
t
PZL
All other
closed
open
DEFINITIONS:
R
L
= Load Resistor; see AC CHARACTERISTICS for value.
C
L
= Load capacitance includes jig and probe capacitance; see AC
CHARACTERISTICS for value.
R
T
= Termination resistance should be equal to Z
OUT
of pulse generators.
C
D
= Load capacitance includes jig and probe capacitance; see AC
CHARACTERISTICS for value.
R
U
= Pull up resistor; see AC CHARACTERISTICS for value.
tW
90%
VM
10%
90%
VM
10%
90%
VM
10%
90%
VM
10%
NEGATIVE
PULSE
POSITIVE
PULSE
AMP (V)
LOW V
LOW V
tTHL
(t
f
)
tTLH
(t
r
)
tW
t
W
Low V
0.0V
tTLH
(t
r
)
tTHL
(t
f
)
AMP (V)
A Port
1MHz
2.0V
2.0ns
1.0V
B Port
V
CC
D.U.T.
PULSE
GENERATOR
R
U
C
D
R
T
V
IN
V
OUT
Test Circuit for Outputs on B Port
BIAS
V
2.0V (for R
U
= 9
)
2.1V (for R
U
= 16.5
)
SG00063
Philips Semiconductors
Product specification
FBL2031
9-bit BTL 3.3V latched/registered/pass-thru
Futurebus+ transceiver
2000 Apr 18
14
QFP52:
plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm
SOT379-1
Philips Semiconductors
Product specification
FBL2031
9-bit BTL 3.3V latched/registered/pass-thru
Futurebus+ transceiver
2000 Apr 18
15
NOTES
Philips Semiconductors
Product specification
FBL2031
9-bit BTL 3.3V latched/registered/pass-thru
Futurebus+ transceiver
2000 Apr 18
16
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 2000
All rights reserved. Printed in U.S.A.
Date of release: 04-00
Document order number:
9397 750 07089
Philips
Semiconductors
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
[1]
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
Data sheet status
[1]
Please consult the most recently issued datasheet before initiating or completing a design.
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