Philips
Semiconductors
FBL2041
FBL2041I
3.3V BTL 7-bit Futurebus+ transceiver
(standard A-port)
Product specification
Supersedes data of 1998 May 11
IC23 Data Handbook
1999 Apr 27
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
FBL2041
FBL2041I
3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)
2
1999 Apr 27
853-2040 21374
FEATURES
7-bit BTL transceiver
Separate I/O on TTL A-port
Inverting
Three separate pairs of driver enables in a 1 bit, 3 bit, 3 bit
arrangement
Drives heavily loaded backplanes with equivalent load
impedances down to 10
.
High drive 100mA BTL open collector drivers on B-port
Allows incident wave switching in heavily loaded backplane buses
Reduced BTL voltage swing produces less noise and reduces
power consumption
Built-in precision band-gap reference provides accurate receiver
thresholds and improved noise immunity
Compatible with IEEE Futurebus+ or proprietary BTL backplanes
Controlled output ramp and multiple GND pins minimize ground
bounce
Each BTL driver has a dedicated Bus GND for a signal return
Glitch-free power up/power down operation
Low I
CC
current
Tight output skew
Supports live insertion
Pins for the optional JTAG boundary scan function are provided
High density packaging in plastic Quad Flatpack
5V compatible I/O on A-port
Industrial temperature range option available as FBL2041I
DESCRIPTION
The FBL2041/FBL2041I is a 7-bit bidirectional BTL transceiver and
is intended to provide the electrical interface to a high performance
wired-OR bus. The FBL2041 is an inverting transceiver.
The B-port drivers are Low-capacitance open collectors with
controlled ramp and are designed to sink 100mA. Precision band
gap references on the B-port insure very good noise margins by
limiting the switching threshold to a narrow region centered at 1.55V.
The FBL2041/FBL2041I is pin and function compatible with FB2041
but operates at a 3.3V supply voltage, greatly reducing power
consumption.
The B-port interfaces to "Backplane Transceiver Logic" (See the
IEEE 1194.1 BTL standard). BTL features low power consumption
by reducing voltage swing (1Vp-p, between 1V and 2V) and reduced
capacitive loading by placing an internal series diode on the drivers.
BTL also provides incident wave switching, a necessity for high
performance backplanes.
There are three separate pairs of driver enables in a 1 bit, 3 bit, 3 bit
arrangement. The TTL/BTL output drivers for bit 0 are enabled with
OEA1/OEB1, output drivers for bits 123 are enabled with
OEA2/OEB2 and output drivers for bits 456 are enabled with
OEA3/OEB3.
The A-port operates at TTL levels with separate I/O. The 3-state
A-port drivers are enabled when OEAn goes High after an extra 6ns
delay which is built in to provide a break-before-make function.
When OEAn goes Low, A-port drivers become High impedance
without any extra delay. During power on/off cycles, the A-port
drivers are held in a High impedance state when V
CC
is below 1.3V.
The B-port has an output enable, OEB0, which affects all seven
drivers. When OEB0 is High and OEBn is Low the output driver will
be enabled. When OEB0 is Low or if OEBn is High, the B-port
drivers will be inactive and at the level of the backplane signal.
To support live insertion, OEB0 is held Low during power on/off
cycles to insure glitch free B port drivers. Proper bias for B port
drivers during live insertion is provided by the BIAS V pin when at a
3.3V level while V
CC
is Low. If live insertion is not a requirement, the
BIAS V pin should be tied to a V
CC
pin.
The LOGIC GND and BUS GND pins are isolated in the package to
minimize noise coupling between the BTL and TTL sides. These
pins should be tied to a common ground external to the package.
Each BTL driver has an associated BUS GND pin that acts as a
signal return path and these BUS GND pins are internally isolated
from each other. In the event of a ground return fault, a "hard" signal
failure occurs instead of a pattern dependent error that may be very
infrequent and impossible to trouble-shoot.
JTAG boundary scan functionality is provided as an option with
signals TMS, TCK, TDI and TDO. When this option is not present,
TMS and TCK are no-connects (no bond wires) and TDI and TDO
are shorted together internally.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
TYPICAL
UNIT
t
PLH
Propagation delay
4.2
ns
t
PHL
AIn to Bn
3.5
ns
t
PLH
Propagation delay
4.8
ns
t
PHL
Bn to AOn
4.9
ns
C
OB
Output capacitance (B0 - B6 only)
6
pF
I
OL
Output current (B0 - B6 only)
100
mA
Standby
5.2
I
CC
Supply Current
AIn to Bn (outputs Low or High)
3.2
mA
I
CC
Su
ly Current
Bn to AOn (outputs Low)
13.5
mA
Bn to AOn (outputs High)
10.7
ORDERING INFORMATION
PACKAGE
COMMERCIAL RANGE
V
CC
= 3.3V
10%; T
amb
= 0 to +70
C
INDUSTRIAL RANGE
V
CC
= 3.3V
10%; T
amb
= 40 to +85
C
DWG
No.
52-pin Plastic Quad Flatpack
FBL2041 BB
FBL2041I BB
SOT379-1
Philips Semiconductors
Product specification
FBL2041
FBL2041I
3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)
1999 Apr 27
3
PIN CONFIGURATION
52 51 50 49 48 47 46
45 44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
28
27
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19
20
21 22 23 24 25 26
BUS GND
B1
BUS GND
B2
BUS GND
B3
BUS GND
B4
BUS GND
B5
BUS GND
B6
N/C
LOGIC GND
AI1
AI2
AO2
LOGIC GND
AO3
LOGIC GND
AI3
AI4
AO4
LOGIC GND
AO5
LOGIC GND
AI5
LOGIC GND
AO6
LOGIC GND
TDO (option)
TDI (option)
AI6
OEB3
BUS V
CC
LOGIC V
CC
AO1
AO0
OEA1
TCK (option)
TMS (option)
BUS GND
OEB1
BIAS V
B0
BUS V
CC
LOGIC V
CC
OEB0
7-Bit Transceiver
52-lead PQFP
AI0
OEB2
OEA3
OEA2
SG00115
PIN DESCRIPTION
SYMBOL
PIN NUMBER
TYPE
NAME AND FUNCTION
AI0 AI6
51, 2, 3, 8, 9, 14, 18
Input
Data inputs (TTL)
AO0 AO6
50, 52, 4, 6, 10, 12, 16
Output
3-State outputs (TTL)
B0 B6
40, 38, 36, 34, 32, 30, 28
I/O
Data inputs/Open Collector outputs, High current drive (BTL)
OEB0
46
Input
Enables the Bn outputs when High
OEB1
45
Input
Enables the B0 output when Low
OEB2
25
Input
Enables the B1 B3 outputs when Low
OEB3
26
Input
Enables the B4 B6 outputs when Low
OEA1
47
Input
Enables the A0 outputs when High
OEA2
20
Input
Enables the A1 A3 outputs when High
OEA3
24
Input
Enables the A4 A6 outputs when High
BUS GND
41, 39, 37, 35, 33, 31, 29
GND
Bus ground (0V)
LOGIC GND
1, 5, 7, 11, 13, 15, 19
GND
Logic ground (0V)
BUS V
CC
23, 43
Power
Positive supply voltage
LOGIC V
CC
17, 49
Power
Positive supply voltage BAND GAP
BIAS V
48
Power
Positive supply voltage
TMS
42
Input
Test Mode Select (no-connect)
TCK
44
Input
Test Clock (no-connect)
TDI
22
Input
Test Data In (shorted to TDO)
TDO
21
Output
Test Data Out (TDI)
N/C
27
--
Not connected
Philips Semiconductors
Product specification
FBL2041
FBL2041I
3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)
1999 Apr 27
4
FUNCTION TABLE
MODE
INPUTS
OUTPUTS
MODE
AIn
Bn*
OEB0
OEB1
OEB2
OEB3
OEA1
OEA2
OEA3
AOn
Bn*
L
--
H
L
L
L
L
L
L
Z
H**
AIn to Bn
H
--
H
L
L
L
L
L
L
Z
L
L
--
H
L
L
L
H
H
H
L
H**
H
--
H
L
L
L
H
H
H
H
L
L
--
H
L
X
X
L
L
L
Z
H**
AI0 to B0
H
--
H
L
X
X
L
L
L
Z
L
L
--
H
L
X
X
H
H
H
L
H**
H
--
H
L
X
X
H
H
H
H
L
L
--
H
X
L
X
L
L
L
Z
H**
AI1 AI3 to B1 B3
H
--
H
X
L
X
L
L
L
Z
L
L
--
H
X
L
X
H
H
H
L
H**
H
--
H
X
L
X
H
H
H
H
L
L
--
H
X
X
L
L
L
L
Z
H**
AI4 AI6 to B4 B6
H
--
H
X
X
L
L
L
L
Z
L
L
--
H
X
X
L
H
H
H
L
H**
H
--
H
X
X
L
H
H
H
H
L
Disable Bn outputs
X
X
L
X
X
X
X
X
X
X
H**
X
X
X
H
H
H
X
X
X
X
H**
Disable B0 outputs
X
X
H
H
X
X
X
X
X
X
H**
Disable B1 B3 outputs
X
X
H
X
H
X
X
X
X
X
H**
Disable B4 B6 outputs
X
X
H
X
X
H
X
X
X
X
H**
X
L
L
X
X
X
H
H
H
H
Input
Bn to AOn
X
H
L
X
X
X
H
H
H
L
Input
X
L
X
H
H
H
H
H
H
H
Input
X
H
X
H
H
H
H
H
H
L
Input
X
L
L
X
X
X
H
X
X
H
Input
B0 to AO0
X
H
L
X
X
X
H
X
X
L
Input
X
L
X
H
H
H
H
X
X
H
Input
X
H
X
H
H
H
H
X
X
L
Input
X
L
L
X
X
X
X
H
X
H
Input
B1 B3 to AO1 AO3
X
H
L
X
X
X
X
H
X
L
Input
X
L
X
H
H
H
X
H
X
H
Input
X
H
X
H
H
H
X
H
X
L
Input
X
L
L
X
X
X
X
X
H
H
Input
B4 B6 to AO4 AO6
X
H
L
X
X
X
X
X
H
L
Input
X
L
X
H
H
H
X
X
H
H
Input
X
H
X
H
H
H
X
X
H
L
Input
Disable AOn outputs
X
X
X
X
X
X
L
L
L
Z
X
Disable AO0 outputs
X
X
X
X
X
X
L
X
X
Z
X
Disable AO1 AO3 outputs
X
X
X
X
X
X
X
L
X
Z
X
Disable AO4 AO6 outputs
X
X
X
X
X
X
X
X
L
Z
X
NOTES:
H
=
High voltage level
L
=
Low voltage level
X
=
Don't care
Z
=
High-impedance (OFF) state
--
=
Input not externally driven
H** =
Goes to level of pull-up voltage
B*
=
Precaution should be taken to ensure B inputs do not float. If they do, they are equal to Low state.
Philips Semiconductors
Product specification
FBL2041
FBL2041I
3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)
1999 Apr 27
5
LOGIC DIAGRAM
SG00116
46
45
OEB0
OEB1
47
OEA1
BTL
Levels
TTL
Levels
TMS
TCK
TDI
TDO
42
44
22
21
(Future JTAG Boundary Scan option)
LOGIC V
CC
=
17, 49
LOGIC GND
=
1, 5, 7, 11, 13, 15, 19
BUS V
CC
=
23, 43
BUS GND
=
29, 31, 33, 35, 37, 39, 41
BIAS V
=
48
51
AI0
50
AO0
B0
40
25
OEB2
38
B1
20
2
52
OEA2
AI1
AO1
36
3
4
B2
AI2
AO2
34
8
6
B3
AI3
AO3
26
32
24
9
10
30
14
12
28
18
16
OEB3
B4
OEA3
AI4
AO4
B5
AI5
AO5
B6
AI6
AO6
Philips Semiconductors
Product specification
FBL2041
FBL2041I
3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)
1999 Apr 27
6
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.
SYMBOL
PARAMETER
RATING
UNIT
V
CC
Supply voltage
0.5 to +4.6
V
V
Input voltage
AI0 AI6, OEB0, OEBn, OEAn
0.5 to +7.0
V
IN
Input voltage
B0 B6
0.5 to +3.5
V
I
IN
Input current
V
IN
t
0
50
V
OUT
Voltage applied to output in High output state
0.5 to +7.0
V
I
O
Current applied to output in
AO0 AO6
64, 64
mA
I
OUT
Low output state/High output state
B0 B6
200
mA
T
STG
Storage temperature
65 to +150
C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
COMMERCIAL LIMITS
V
CC
= 3.3V
10%;
T
amb
= 0 to +70
C
INDUSTRIAL LIMITS
V
CC
= 3.3V
10%;
T
amb
= 40 to +85
C
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
V
CC
Supply voltage
3.0
3.3
3.6
3.0
3.3
3.6
V
V
High level input voltage
Except B0B6
2.0
2.0
V
V
IH
High-level input voltage
B0 B6
1.62
1.55
1.62
1.55
V
V
Low level input voltage
Except B0B6
0.8
0.8
V
V
IL
Low-level input voltage
B0 B6
1.47
1.47
V
I
IK
Input clamp current
18
18
mA
I
OH
High-level output current
AO0 AO6
32
32
mA
I
O
Low level output current
AO0 AO6
+32
+32
mA
I
OL
Low-level output current
B0 B6
100
100
mA
C
OB
Output capacitance on B port
6
7
6
7
pF
T
amb
Operating free-air temperature range
0
+70
40
+85
C
LIVE INSERTION SPECIFICATIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
V
BIASV
Bias pin voltage
Voltage difference between the Bias voltage and
V
CC
after the PCB is plugged in.
0.5
V
I
S
Bias pin (I
S
) input DC current
V
CC
= 0 V, Bias V = 3.6V
1.2
mA
I
BIASV
Bias pin (I
BIASV
) input DC current
V
CC
= 3.3V, Bias V = 3.6V
10
A
V
Bn
Bus voltage during prebias
B0 B8 = 0V, Bias V = 3.3V
1.62
2.1
V
I
LM
Fall current during prebias
B0 B8 = 2V, Bias V = 1.3 to 2.5V
1
A
I
HM
Rise current during prebias
B0 B8 = 1V, Bias V = 3 to 3.6V
1
A
I
Bn
PEAK
Peak bus current during insertion
V
CC
= 0 to 3.3V, B0 B8 = 0 to 2.0V,
Bias V = 2.7 to 3.6V, OEB0 = 0.8V, t
r
= 2ns
10
mA
I
O
OFF
Power up current
V
CC
= 0 to 3.3V, OEB0 = 0.8V
100
A
I
OL
OFF
Power up current
V
CC
= 0 to 1.2V, OEB0 = 0 to 5V
100
A
t
GR
Input glitch rejection
V
CC
= 3.3V
1.0
1.35
ns
Philips Semiconductors
Product specification
FBL2041
FBL2041I
3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)
1999 Apr 27
7
DC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range unless otherwise noted.
SYMBOL
PARAMETER
TEST CONDITIONS
1
LIMITS
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
1
MIN
TYP
2
MAX
UNIT
I
OH
High level output current
B0 B6
V
CC
= MAX, V
IL
= MAX, V
OH
= 1.9V
100
A
I
O
Power off output current
B0
B6
V
CC
= 0V, V
IL
= MAX, V
OH
= 1.9V
100
A
I
OFF
Power-off output current
B0 B6
V
CC
= 0V, V
IL
= MAX, V
OH
= 1.9V @ 85
C
300
A
Hi h l
l
t
t
3
V
CC
= MIN to MAX; I
OH
= -100
A
V
CC
0.2
V
V
OH
High-level output
voltage
AO0 AO6
3
V
CC
= MIN; I
OH
= -8mA
2.4
V
voltage
V
CC
= MIN; I
OH
= -32mA
2.0
V
AO0
AO6
3
V
CC
= MIN; I
OL
= 16mA
0.4
V
V
OL
Low-level output voltage
AO0 AO6
3
V
CC
= MIN; I
OL
= 32mA
0.5
V
B0
B6
V
CC
= MIN, I
OL
= 4mA
0.5
V
B0 B6
V
CC
= MIN, I
OL
= 100mA
0.75
1.0
1.20
V
V
IK
Input clamp voltage
V
CC
= MIN, I
I
= I
IK
= 18mA
0.85
-1.2
V
Control pins
V
CC
= 3.6V; V
I
= V
CC
or GND
1.0
I
Input leakage current
Control/ AI0 AI6
V
CC
= 0V or 3.6V; V
I
= 5.5V
10
A
I
I
Input leakage current
AI0 AI6
V
CC
= 3.6V; V
I
= V
CC
1
A
Note 4
V
CC
= 3.6V; V
I
= 0V
5
V
CC
= MAX, V
I
= 1.9V
100
A
I
IH
High-level input current
B0 B6
V
CC
= MAX, V
I
= 3.5V, note 5
100
mA
V
CC
= MAX; V
I
= 3.75V @ 40
C
100
mA
I
IL
Low-level input current
B0 B6
V
CC
= MAX, V
I
= 0.75V
-100
A
I
OZH
Off-state output current
AO0 AO6
V
CC
= MAX, V
O
=3V
5
A
I
OZL
Off-state output current
AO0 AO6
V
CC
= MAX, V
O
= 0.5V
-5
A
I
CCZ
V
CC
= MAX
5.2
13.5
I
CC
Supply current (total)
I
CCB
V
CC
= MAX, outputs Low or High
3.2
9.0
mA
I
CC
Supply current (total)
I
CCL
V
CC
= MAX, outputs Low
13.5
19.5
mA
I
CCH
V
CC
= MAX, outputs High
10.7
16.0
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type.
2. All typical values are at V
CC
= 3.3V, T
A
= 25
C.
3. Due to test equipment limitations, actual test conditions are V
IH
= 1.8V and V
IL
= 1.3V for the B side.
4. Unused pins are at V
CC
or GND.
5. For B port input voltage between 3 and 5 volt; I
IH
will be greater than 100mA but the part will continue to function normally (clamping circuit
is active).
Philips Semiconductors
Product specification
FBL2041
FBL2041I
3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)
1999 Apr 27
8
AC ELECTRICAL CHARACTERISTICS
A PORT LIMITS
TEST
T
amb
= +25
C,
FBL2041
COMMERCIAL
FBL2041I
INDUSTRIAL
SYMBOL
PARAMETER
TEST
CONDITION
amb
,
V
cc
= 3.3V,
C
L
= 50pf, R
L
= 500
T
amb
= 0 to +70
C,
V
CC
= 3.3V
10%,
C
L
= 50pF, R
L
= 500
T
amb
= 40 to +85
C,
V
CC
= 3.3V
10%,
C
L
= 50pF, R
L
= 500
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
MAX
t
PLH
t
PHL
Propagation delay,
Bn to AOn
Waveform 1, 2
3.9
4.0
4.8
4.9
5.8
6.0
3.7
3.8
6.4
6.7
2.8
2.7
6.9
7.0
ns
t
PZH
t
PZL
Output enable time,
OEA to AOn
Waveform 4, 5
5.3
2.4
6.6
4.4
8.0
8.0
5.0
2.1
8.6
8.5
4.5
1.1
9.0
9.0
ns
t
PHZ
t
PLZ
Output disable time,
OEA to AOn
Waveform 4, 5
3.5
2.3
4.8
3.1
6.0
3.9
3.4
2.2
6.5
4.3
2.7
1.4
7.0
4.7
ns
t
TLH
t
THL
Transition time, AOn Port
(10% to 90%
or 90% to 10%)
Test Circuit
and Waveforms
0.7
0.5
1.8
1.6
3.0
2.0
0.7
0.5
3.0
2.0
0.7
0.5
3.0
2.0
ns
t
SK
(o)
Output skew between
receivers in same
package
1
Waveform 3
0.7
1.5
1.5
1.5
ns
B PORT LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
T
amb
= +25
C,
V
CC
= 3.3V,
C
D
= 30pF, R
U
= 9
T
amb
= 0 to +70
C,
V
CC
= 3.3V
10%,
C
D
= 30pF, R
U
= 9
T
amb
= 40 to +85
C,
V
CC
= 3.3V
10%,
C
D
= 30pF, R
U
= 9
UNIT
t
PLH
t
PHL
Propagation delay,
AIn to Bn
Waveform 1, 2
3.3
2.7
4.2
3.5
5.2
4.5
2.9
2.5
6.0
5.0
1.8
1.7
6.7
5.6
ns
t
PLH
t
PHL
Enable/disable time,
OEB0 to Bn
Waveform 2
4.0
3.4
4.9
4.3
5.8
5.3
3.6
3.1
6.6
6.0
2.8
2.5
7.1
6.4
ns
t
PLH
t
PHL
Enable/disable time,
OEB1 to Bn
Waveform 1
4.2
2.9
5.1
3.8
6.1
4.7
3.9
2.6
6.9
5.5
2.9
1.9
7.3
6.0
ns
t
TLH
t
THL
Transition time, Bn Port
(1.3V to 1.8V)
Test Circuit
and Waveforms
1.2
0.4
2.4
0.9
3.0
1.5
1.2
0.4
3.0
1.5
1.2
0.4
3.0
1.5
ns
t
SK
(o)
Output skew between
drivers in same package
1
Waveform 3
1.5
1.5
1.5
ns
SYMBOL
PARAMETER
TEST
CONDITION
R
U
= 16.5
R
U
= 16.5
R
U
= 16.5
UNIT
t
PLH
t
PHL
Propagation delay,
AIn to Bn
Waveform 1, 2
3.3
2.7
4.2
3.6
5.1
4.5
3.0
2.5
6.0
5.0
1.8
1.7
6.7
5.6
ns
t
PLH
t
PHL
Enable/disable time,
OEB0 to Bn
Waveform 2
4.0
3.4
4.9
4.3
5.8
5.3
3.6
3.1
6.6
6.0
2.7
2.5
7.1
6.4
ns
t
PLH
t
PHL
Enable/disable time,
OEB1 to Bn
Waveform 1
4.2
2.9
5.1
3.8
6.1
4.7
3.9
2.6
6.8
5.5
3.0
1.9
7.3
6.0
ns
t
TLH
t
THL
Transition time, Bn Port
(1.3V to 1.8V)
Test Circuit
and Waveforms
1.2
0.4
2.4
0.9
3.0
1.5
1.2
0.4
3.0
1.5
1.2
0.4
3.0
1.5
ns
t
SK
(o)
Output skew between
drivers in same package
1
Waveform 3
1.5
1.5
1.5
ns
NOTES:
1.
t
PN
actual t
PM
actual
for any data input to output path compared to any other data input to output path where N and M are either LH or
HL. Skew times are valid only under same test conditions (temperature, V
CC
, loading, etc.).
Philips Semiconductors
Product specification
FBL2041
FBL2041I
3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)
1999 Apr 27
9
AC WAVEFORMS
V
M
= 1.55V for Bn, V
M
= 1.5V for all others.
AIn, Bn or Bn
OEBn
AOn or Bn
V
M
V
M
V
M
V
M
t
PLH
t
PHL
SG00101
Waveform 1.
Propagation Delay for Data or
Output Enable to Output
V
M
V
M
V
M
V
M
t
PHL
t
PLH
AOn, Bn
AIn, Bn
OEB0
SG00102
Waveform 2.
Propagation Delay for Data or
Output Enable to Output
AIn, Bn
AOn, Bn
V
M
V
M
t
SK
(o)
SG00103
Waveform 3.
Output Skews
AOn
OEA
V
M
V
M
V
M
V
OH
-0.3V
OV
t
PHZ
t
PZH
SG00104
Waveform 4.
3-State Output Enable Time to High Level and
Output Disable Time from High Level
t
PZL
AOn
OEA
V
M
V
M
t
PLZ
V
M
V
OL
+0.3V
SG00105
Waveform 5.
3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
Philips Semiconductors
Product specification
FBL2041
FBL2041I
3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)
1999 Apr 27
10
TEST CIRCUIT AND WAVEFORMS
2.5ns
2.5ns
500ns
500ns
INPUT PULSE REQUIREMENTS
Rep. Rate
Amplitude
t
TLH
t
THL
1MHz
3.0V
2.5ns
Input Pulse Definitions
VM = 1.55V for Bn, VM = 1.5V for all others.
V
CC
Family
FB+
D.U.T.
PULSE
GENERATOR
6.0V
RL
RL
CL
RT
VIN
VOUT
Test Circuit for 3-State Outputs on A Port
TEST
SWITCH
SWITCH POSITION FOR ALL A-PORTS
t
PLH,
t
PHL
OPEN
DEFINITIONS:
R
L
= Load Resistor; see AC CHARACTERISTICS for value.
C
L
= Load capacitance includes jig and probe capacitance; see AC
CHARACTERISTICS for value.
R
T
= Termination resistance should be equal to Z
OUT
of pulse generators.
C
D
= Load capacitance includes jig and probe capacitance; see AC
CHARACTERISTICS for value.
R
U
= Pull up resistor; see AC CHARACTERISTICS for value.
tW
90%
VM
10%
90%
VM
10%
90%
VM
10%
90%
VM
10%
NEGATIVE
PULSE
POSITIVE
PULSE
LOW V
LOW V
tTHL
(t
f
)
tTLH
(t
r
)
tW
BIAS
V
t
W
Low V
0.0V
tTLH
(t
r
)
tTHL
(t
f
)
A Port
1MHz
2.0V
2.5ns
1.0V
B Port
V
CC
D.U.T.
PULSE
GENERATOR
RU
CD
RT
VIN
VOUT
Test Circuit for Outputs on B Port
BIAS
V
2.0V (for RU = 9
)
2.1V (for RU = 16.5
)
VIN
VIN
SG00090
t
PLZ,
t
PZL
CLOSED
t
PHZ,
t
PZH
GND
Philips Semiconductors
Product specification
FBL2041
FBL2041I
3.3V BTL 7-bit Futurebus+ transceiver (standard A port)
1999 Apr 27
11
QFP52:
plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm
SOT379-1
Philips Semiconductors
Product specification
FBL2041
FBL2041I
3.3V BTL 7-bit Futurebus+ transceiver (standard A port)
1999 Apr 27
12
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1999
All rights reserved. Printed in U.S.A.
Date of release: 11-99
Document order number:
9397 750 06597
Philips
Semiconductors
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
[1]
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
Data sheet status
[1]
Please consult the most recently issued datasheet before initiating or completing a design.
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