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Электронный компонент: GTL2008PW

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1.
General description
The GTL2008/GTL2107 is a customized translator between dual Xeon processors,
Platform Health Management, South Bridge and Power Supply LVTTL and GTL signals.
Functionally and footprint identical to the GTL2007, the GTL2008/GTL2107 LVTTL and
GTL outputs were changed to put them into a high-impedance state when EN1 and EN2
are LOW, with the exception of 11BO because its normal state is LOW, so it is forced
LOW. EN1 and EN2 will remain LOW until V
CC
is at normal voltage, the other inputs are in
valid states and VREF is at its proper voltage to assure that the outputs will remain
high-impedance through power-up.
Both the GTL2008/GTL2107 and the GTL2007 are derived from the GTL2006. They add
an enable function that disables the error output to the monitoring agent for platforms that
monitor the individual error conditions from each processor. This enable function can be
used so that false error conditions are not passed to the monitoring agent when the
system is unexpectedly powered down. This unexpected power-down could be from a
power supply overload, a CPU thermal trip, or some other event of which the monitoring
agent is unaware.
A typical implementation would be to connect each enable line to the system power good
signal or the individual enables to the VRD power good for each processor.
Typically Xeon processors specify a V
TT
of 1.1 V to 1.2 V, as well as a nominal V
ref
of
0.73 V to 0.76 V. To allow for future voltage level changes that may extend V
ref
to 0.63 of
V
TT
(minimum of 0.693 V with V
TT
of 1.1 V) the GTL2008/GTL2107 allows a minimum V
ref
of 0.66 V. Characterization results show that there is little DC or AC performance variation
between these levels.
The GTL2008 is the companion chip to the GTL2009 3-bit GTL Front-Side Bus frequency
comparator that is used in dual-processor Xeon applications.
The GTL2107 is the Intel designation for the GTL2008.
2.
Features
I
Operates as a GTL to LVTTL sampling receiver or LVTTL to GTL driver
I
EN1 and EN2 disable error output
I
All LVTTL and GTL outputs are put in a high-impedance state when EN1 and EN2 are
LOW
I
3.0 V to 3.6 V operation
I
LVTTL I/O not 5 V tolerant
GTL2008; GTL2107
12-bit GTL to LVTTL translator with power good control and
high-impedance LVTTL and GTL outputs
Rev. 02 -- 26 September 2006
Product data sheet
GTL2008_GTL2107_2
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 -- 26 September 2006
2 of 20
Philips Semiconductors
GTL2008; GTL2107
GTL translator with power good control and high-impedance outputs
I
Series termination on the LVTTL outputs of 30
I
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
I
Latch-up testing is done to JEDEC Standard JESD78 Class II, Level A which exceeds
500 mA
I
Package offered: TSSOP28
3.
Quick reference data
4.
Ordering information
The GTL2107 is the Intel designation for the GTL2008 and is identical to the GTL2008
except for the type number and the topside markings.
Table 1.
Quick reference data
T
amb
= 25
C
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
C
io
input/output capacitance
A port; V
O
= 3.0 V or 0 V
-
2.5
3.5
pF
B port; V
O
= V
TT
or 0 V
-
1.5
2.5
pF
V
ref
= 0.73 V; V
TT
= 1.1 V
t
PLH
LOW-to-HIGH
propagation delay
nA to nBI; see
Figure 4
1
4
8
ns
nBI to nA or nAO (open-drain outputs);
see
Figure 14
2
13
18
ns
t
PHL
HIGH-to-LOW
propagation delay
nA to nBI; see
Figure 4
2
5.5
10
ns
nBI to nA or nAO (open-drain outputs);
see
Figure 14
2
4
10
ns
V
ref
= 0.76 V; V
TT
= 1.2 V
t
PLH
LOW-to-HIGH
propagation delay
nA to nBI; see
Figure 4
1
4
8
ns
nBI to nA or nAO (open-drain outputs);
see
Figure 14
2
13
18
ns
t
PHL
HIGH-to-LOW
propagation delay
nA to nBI; see
Figure 4
2
5.5
10
ns
nBI to nA or nAO (open-drain outputs);
see
Figure 14
2
4
10
ns
Table 2.
Ordering information
T
amb
=
-
40
C to +85
C
Type
number
Topside
mark
Package
Name
Description
Version
GTL2008PW GTL2008
TSSOP28
plastic thin shrink small outline package; 28 leads; body width 4.4 mm
SOT361-1
GTL2107PW GTL2107
TSSOP28
plastic thin shrink small outline package; 28 leads; body width 4.4 mm
SOT361-1
GTL2008_GTL2107_2
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 -- 26 September 2006
3 of 20
Philips Semiconductors
GTL2008; GTL2107
GTL translator with power good control and high-impedance outputs
5.
Functional diagram
(1) The enable on 7BO1/7BO2 include a delay that prevents the transient condition where 5BI/6BI go from LOW to HIGH, and
the LOW to HIGH on 5A/6A lags up to 100 ns from causing a LOW glitch on the 7BO1/7BO2 outputs.
(2) The 11BO output is driven LOW after V
CC
is powered up with EN2 LOW to prevent reporting of a fault condition before EN2
goes HIGH.
Fig 1.
Logic diagram of GTL2008/GTL2107
002aab968
GTL2008/GTL2107
1BI
2BI
27
26
GTL inputs
7BO1
25
7BO2
24
GTL outputs
EN2
23
LVTTL input
11BO
22
GTL output
DELAY
(1)
5BI
6BI
21
20
3BI
19
4BI
18
DELAY
(1)
GTL inputs
7
11BI
8
11A
9
9BI
LVTTL input/output
(open-drain)
GTL input
GTL input
1
VREF
2
1AO
3
2AO
4
5A
5
6A
6
EN1
LVTTL input
GTL
LVTTL inputs/outputs
(open-drain)
LVTTL outputs
(open-drain)
10
3AO
11
4AO
LVTTL outputs
(open-drain)
10BO1
17
10BO2
16
GTL outputs
12
10AI1
13
10AI2
LVTTL inputs
9AO
15
LVTTL output
(2)
1
1
&
&
1
GTL2008_GTL2107_2
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 -- 26 September 2006
4 of 20
Philips Semiconductors
GTL2008; GTL2107
GTL translator with power good control and high-impedance outputs
6.
Pinning information
6.1 Pinning
6.2 Pin description
Fig 2.
Pin configuration for TSSOP28
GTL2008PW
GTL2107PW
VREF
V
CC
1AO
1BI
2AO
2BI
5A
7BO1
6A
7BO2
EN1
EN2
11BI
11BO
11A
5BI
9BI
6BI
3AO
3BI
4AO
4BI
10AI1
10BO1
10AI2
10BO2
GND
9AO
002aab969
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
18
17
20
19
22
21
24
23
26
25
28
27
Table 3.
Pin description
Symbol
Pin
Description
VREF
1
GTL reference voltage
1AO
2
data output (LVTTL), open-drain
2AO
3
data output (LVTTL), open-drain
5A
4
data input/output (LVTTL), open-drain
6A
5
data input/output (LVTTL), open-drain
EN1
6
enable input (LVTTL)
11BI
7
data input (GTL)
11A
8
data input/output (LVTTL), open-drain
9BI
9
data input (GTL)
3AO
10
data output (LVTTL), open-drain
4AO
11
data output (LVTTL), open-drain
10AI1
12
data input (LVTTL)
10AI2
13
data input (LVTTL)
GND
14
ground (0 V)
9AO
15
data output (LVTTL), 3-state
10BO2
16
data output (GTL)
10BO1
17
data output (GTL)
4BI
18
data input (GTL)
3BI
19
data input (GTL)
GTL2008_GTL2107_2
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 -- 26 September 2006
5 of 20
Philips Semiconductors
GTL2008; GTL2107
GTL translator with power good control and high-impedance outputs
7.
Functional description
Refer to
Figure 1 "Logic diagram of GTL2008/GTL2107"
.
7.1 Function tables
[1]
1AO, 2AO, 3AO, 4AO and 5A/6A condition changed by ENn power good signal as described in
Table 5
and
Table 6
.
6BI
20
data input (GTL)
5BI
21
data input (GTL)
11BO
22
data output (GTL)
EN2
23
enable input (LVTTL)
7BO2
24
data output (GTL)
7BO1
25
data output (GTL)
2BI
26
data input (GTL)
1BI
27
data input (GTL)
V
CC
28
positive supply voltage
Table 3.
Pin description
...continued
Symbol
Pin
Description
Table 4.
GTL input signals
H = HIGH voltage level; L = LOW voltage level.
Input
Output
[1]
1BI/2BI/3BI/4BI/9BI
1AO/2AO/3AO/4AO/9AO
L
L
H
H
Table 5.
EN1 power good signal
H = HIGH voltage level; L = LOW voltage level.
EN1
1AO and 2AO
5A
L
1BI and 2BI disconnected (high-Z)
5BI disconnected
H
follows BI
5BI connected
Table 6.
EN2 power good signal
H = HIGH voltage level; L = LOW voltage level.
EN2
3AO and 4AO
6A
L
3BI and 4BI disconnected (high-Z)
6BI disconnected
H
follows BI
6BI connected
GTL2008_GTL2107_2
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 -- 26 September 2006
6 of 20
Philips Semiconductors
GTL2008; GTL2107
GTL translator with power good control and high-impedance outputs
[1]
The enable on 7BO1/7BO2 includes a delay that prevents the transient condition where 5BI/6BI go from
LOW to HIGH, and the LOW to HIGH on 5A/6A lags up to 100 ns from causing a low glitch on the
7BO1/7BO2 outputs.
[2]
Open-drain input/output terminal is driven to logic LOW state by other driver.
[1]
Open-drain input/output terminal is driven to logic LOW state by other driver.
Table 7.
SMI signals
H = HIGH voltage level; L = LOW voltage level; X = Don't care.
Inputs
Output
10AI1/10AI2
EN2
9BI
10BO1/10BO2
L
H
L
L
L
H
H
L
H
H
L
L
H
H
H
H
L
L
X
L
H
L
X
H
Table 8.
PROCHOT signals
H = HIGH voltage level; L = LOW voltage level.
Input
Input/output
Output
5BI/6BI
5A/6A (open-drain)
7BO1/7BO2
L
L
H
[1]
H
L
[2]
L
H
H
H
Table 9.
NMI signals
H = HIGH voltage level; L = LOW voltage level; X = Don't care.
Inputs
Input/output
Output
11BI
EN2
11A (open-drain)
11BO
L
H
H
L
L
H
L
[1]
H
H
H
L
H
X
L
H
L
X
L
L
[1]
H
GTL2008_GTL2107_2
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 -- 26 September 2006
7 of 20
Philips Semiconductors
GTL2008; GTL2107
GTL translator with power good control and high-impedance outputs
8.
Application design-in information
(1) If 9AO needs to be HIGH before EN2 goes HIGH, a pull-up resistor is required because it is high-impedance until EN2 goes
HIGH. All other outputs, both GTL and LVTTL, require pull-up resistors because they are open-drain.
Fig 3.
Typical application
THRMTRIP L
CPU1
IERR_L
FORCEPR_L
CPU2 DISABLE_L
GTL2008
GTL2107
PROCHOT L
FORCEPR_L
PROCHOT L
THRMTRIP L
IERR_L
CPU1 DISABLE_L
CPU2
NMI
NMI
10BO2
10BO1
4BI
3BI
6BI
5BI
EN2
7BO2
7BO1
2BI
1BI
1AO
2AO
5A
6A
11A
3AO
4AO
10AI1
10AI2
EN1
GND
9BI
9AO
PLATFORM
HEALTH
MANAGEMENT
CPU1 1ERR_L
CPU1 THRMTRIP L
CPU1 PROCHOT L
CPU2 PROCHOT L
NMI_L
CPU2 IERR_L
CPU2 THRMTRIP L
CPU1 SMI L
CPU2 SMI L
SMI_BUFF_L
SOUTHBRIDGE NMI
SOUTHBRIDGE SMI_L
power supply
POWER GOOD
1.5 k
to 1.2 k
V
CC
V
TT
56
1.5 k
R
2R
VREF
11B1
V
CC
V
CC
11B0
002aab970
56
V
TT
(1)
GTL2008_GTL2107_2
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 -- 26 September 2006
8 of 20
Philips Semiconductors
GTL2008; GTL2107
GTL translator with power good control and high-impedance outputs
9.
Limiting values
[1]
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
[2]
Current into any output in the LOW state.
[3]
Current into any output in the HIGH state.
[4]
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
C.
10. Recommended operating conditions
Table 10.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Max
Unit
V
CC
supply voltage
-
0.5
+4.6
V
I
IK
input clamping current
V
I
< 0 V
-
-
50
mA
V
I
input voltage
A port (LVTTL)
-
0.5
[1]
+4.6
V
B port (GTL)
-
0.5
[1]
+4.6
V
I
OK
output clamping current
V
O
< 0 V
-
-
50
mA
V
O
output voltage
output in OFF or HIGH state; A port
-
0.5
[1]
+4.6
V
output in OFF or HIGH state; B port
-
0.5
[1]
+4.6
V
I
OL
LOW-level output current
[2]
A port
-
32
mA
B port
-
30
mA
I
OH
HIGH-level output current
[3]
A port
-
-
32
mA
T
stg
storage temperature
-
60
+150
C
T
j(max)
maximum junction temperature
[4]
-
+125
C
Table 11.
Operating conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
CC
supply voltage
3.0
3.3
3.6
V
V
TT
termination voltage
GTL
-
1.2
-
V
V
ref
reference voltage
GTL
0.64
0.8
1.1
V
V
I
input voltage
A port
0
3.3
3.6
V
B port
0
V
TT
3.6
V
V
IH
HIGH-level input voltage
A port and ENn
2
-
-
V
B port
V
ref
+ 0.050
-
-
V
V
IL
LOW-level input voltage
A port and ENn
-
-
0.8
V
B port
-
-
V
ref
-
0.050
V
I
OH
HIGH-level output current
A port
-
-
-
16
mA
I
OL
LOW-level output current
A port
-
-
16
mA
B port
-
-
15
mA
T
amb
ambient temperature
operating in free-air
-
40
-
+85
C
GTL2008_GTL2107_2
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 -- 26 September 2006
9 of 20
Philips Semiconductors
GTL2008; GTL2107
GTL translator with power good control and high-impedance outputs
11. Static characteristics
[1]
All typical values are measured at V
CC
= 3.3 V and T
amb
= 25
C.
[2]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[3]
This is the increase in supply current for each input that is at the specified LVTTL voltage level rather than V
CC
or GND.
Table 12.
Static characteristics
Recommended operating conditions; voltages are referenced to GND (ground = 0 V). T
amb
=
-
40
C to +85
C
Symbol
Parameter
Conditions
Min
Typ
[1]
Max
Unit
V
OH
HIGH-level output
voltage
9AO; V
CC
= 3.0 V to 3.6 V; I
OH
=
-
100
A
[2]
V
CC
-
0.2
3.0
-
V
9AO; V
CC
= 3.0 V; I
OH
=
-
16 mA
[2]
2.1
2.3
-
V
V
OL
LOW-level output
voltage
A port; V
CC
= 3.0 V; I
OL
= 4 mA
[2]
-
0.15
0.4
V
A port; V
CC
= 3.0 V; I
OL
= 8 mA
[2]
-
0.3
0.55
V
A port; V
CC
= 3.0 V; I
OL
= 16 mA
[2]
-
0.6
0.8
V
B port; V
CC
= 3.0 V; I
OL
= 15 mA
[2]
-
0.13
0.4
V
I
OH
HIGH-level output
current
open-drain outputs; A port other than 9AO;
V
O
= V
CC
; V
CC
= 3.6 V
-
-
1
A
I
I
input current
A port; V
CC
= 3.6 V; V
I
= V
CC
-
-
1
A
A port; V
CC
= 3.6 V; V
I
= 0 V
-
-
1
A
B port; V
CC
= 3.6 V; V
I
= V
TT
or GND
-
-
1
A
I
CC
supply current
A or B port; V
CC
= 3.6 V; V
I
= V
CC
or GND;
I
O
= 0 mA
-
8
12
mA
I
CC
[3]
additional supply
current
per input; A port or control inputs;
V
CC
= 3.6 V; V
I
= V
CC
-
0.6 V
-
-
500
A
C
io
input/output
capacitance
A port; V
O
= 3.0 V or 0 V
-
2.5
3.5
pF
B port; V
O
= V
TT
or 0 V
-
1.5
2.5
pF
GTL2008_GTL2107_2
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 -- 26 September 2006
10 of 20
Philips Semiconductors
GTL2008; GTL2107
GTL translator with power good control and high-impedance outputs
12. Dynamic characteristics
Table 13.
Dynamic characteristics
V
CC
= 3.3 V
0.3 V
Symbol Parameter
Conditions
Min
Typ
[1]
Max
Unit
V
ref
= 0.73 V; V
TT
= 1.1 V
t
PLH
LOW-to-HIGH propagation delay
nA to nBI; see
Figure 4
1
4
8
ns
9BI to 9AO; see
Figure 5
2
5.5
10
ns
nBI to nA or nAO (open-drain outputs);
see
Figure 14
2
13
18
ns
9BI to 10BOn
2
6
11
ns
11A to 11BO; see
Figure 10
1
4
8
ns
11BI to 11A; see
Figure 9
2
7.5
11
ns
11BI to 11BO
2
8
13
ns
5BI to 7BO1 or 6BI to 7BO2;
see
Figure 7
4
7
12
ns
t
PHL
HIGH-to-LOW propagation delay
nA to nBI; see
Figure 4
2
5.5
10
ns
9BI to 9AO; see
Figure 5
2
5.5
10
ns
nBI to nA or nAO (open-drain outputs);
see
Figure 14
2
4
10
ns
9BI to 10BOn
2
6
11
ns
11A to 11BO; see
Figure 10
1
5.5
10
ns
11BI to 11A; see
Figure 9
2
8.5
13
ns
11BI to 11BO
[2]
2
14
21
ns
5BI to 7BO1 or 6BI to 7BO2;
see
Figure 7
100
205
350
ns
t
PLZ
LOW to OFF-state
propagation delay
EN1 to nAO or EN2 to nAO;
see
Figure 8
1
3
10
ns
EN1 to 5A (I/O) or EN2 to 6A (I/O);
see
Figure 8
1
3
7
ns
t
PZL
OFF-state to LOW
propagation delay
EN1 to nAO or EN2 to nAO;
see
Figure 8
2
7
10
ns
EN1 to 5A (I/O) or EN2 to 6A (I/O);
see
Figure 8
2
7
10
ns
t
PHZ
HIGH to OFF-state
propagation delay
EN2 to 9AO; see
Figure 11
2
5
10
ns
t
PZH
OFF-state to HIGH
propagation delay
EN2 to 9AO; see
Figure 11
1
4
10
ns
GTL2008_GTL2107_2
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 -- 26 September 2006
11 of 20
Philips Semiconductors
GTL2008; GTL2107
GTL translator with power good control and high-impedance outputs
[1]
All typical values are at V
CC
= 3.3 V and T
amb
= 25
C.
[2]
Includes ~7.6 ns RC rise time of test load pull-up on 11A, 1.5 k
pull-up and 21 pF load on 11A has about 23 ns RC rise time.
V
ref
= 0.76 V; V
TT
= 1.2 V
t
PLH
LOW-to-HIGH propagation delay
nA to nBI; see
Figure 4
1
4
8
ns
9BI to 9AO; see
Figure 5
2
5.5
10
ns
nBI to nA or nAO (open-drain outputs);
see
Figure 14
2
13
18
ns
9BI to 10BOn
2
6
11
ns
11A to 11BO; see
Figure 10
1
4
8
ns
11BI to 11A; see
Figure 9
2
7.5
11
ns
11BI to 11BO
2
8
13
ns
5BI to 7BO1 or 6BI to 7BO2;
see
Figure 7
4
7
12
ns
t
PHL
HIGH-to-LOW propagation delay
nA to nBI; see
Figure 4
2
5.5
10
ns
9BI to 9AO; see
Figure 5
2
5.5
10
ns
nBI to nA or nAO (open-drain outputs);
see
Figure 14
2
4
10
ns
9BI to 10BOn
2
6
11
ns
11A to 11BO; see
Figure 10
1
5.5
10
ns
11BI to 11A; see
Figure 9
2
8.5
13
ns
11BI to 11BO
[2]
2
14
21
ns
5BI to 7BO1 or 6BI to 7BO2;
see
Figure 7
100
205
350
ns
t
PLZ
LOW to OFF-state propagation
delay
EN1 to nAO or EN2 to nAO;
see
Figure 8
1
3
10
ns
EN1 to 5A (I/O) or EN2 to 6A (I/O);
see
Figure 8
1
3
7
ns
t
PZL
OFF-state to LOW
propagation delay
EN1 to nAO or EN2 to nAO;
see
Figure 8
2
7
10
ns
EN1 to 5A (I/O) or EN2 to 6A (I/O);
see
Figure 8
2
7
10
ns
t
PHZ
HIGH to OFF-state
propagation delay
EN2 to 9AO; see
Figure 11
2
5
10
ns
t
PZH
OFF-state to HIGH
propagation delay
EN2 to 9AO; see
Figure 11
2
4
10
ns
Table 13.
Dynamic characteristics
...continued
V
CC
= 3.3 V
0.3 V
Symbol Parameter
Conditions
Min
Typ
[1]
Max
Unit
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Product data sheet
Rev. 02 -- 26 September 2006
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Philips Semiconductors
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GTL translator with power good control and high-impedance outputs
12.1 Waveforms
V
M
= 1.5 V at V
CC
3.0 V for A ports; V
M
= V
ref
for B ports.
V
M
= 1.5 V for A port and V
ref
for B port
A port to B port
a. Pulse duration
b. Propagation delay times
Fig 4.
Voltage waveforms
002aaa999
V
OH
0 V
t
p
V
M
V
M
002aab000
3.0 V
0 V
V
TT
V
OL
t
PLH
t
PHL
V
ref
V
ref
1.5 V
1.5 V
input
output
PRR
10 MHz; Z
o
= 50
; t
r
2.5 ns; t
f
2.5 ns
Fig 5.
Propagation delay, 9BI to 9AO
Fig 6.
nBI to nA (I/O) or nBI to nAO open-drain outputs
Fig 7.
5BI to 7BO1 or 6BI to 7BO2
Fig 8.
EN1 to 5A (I/O) or EN2 to 6A (I/O) or EN1 to nAO
or EN2 to nAO
002aab001
V
TT
1
/
3
V
TT
V
OH
V
OL
t
PLH
t
PHL
1.5 V
1.5 V
V
ref
V
ref
input
output
002aab002
V
TT
1
/
3
V
TT
V
CC
t
PLZ
t
PZL
V
ref
V
ref
input
output
V
OL
+ 0.3 V
1.5 V
002aac195
V
TT
1
/
3
V
TT
V
TT
V
OL
t
PLH
t
PHL
V
ref
V
ref
input
output
V
ref
V
ref
002aab005
3.0 V
0 V
V
OH
V
OL
t
PLZ
t
PZL
1.5 V
1.5 V
input
output
1.5 V
V
OL
+ 0.3 V
GTL2008_GTL2107_2
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Product data sheet
Rev. 02 -- 26 September 2006
13 of 20
Philips Semiconductors
GTL2008; GTL2107
GTL translator with power good control and high-impedance outputs
Fig 9.
11BI to 11A
Fig 10. 11A to 11BO
Fig 11. EN2 to 9AO
002aac196
V
TT
0 V
V
OH
V
OL
t
PLZ
t
PZL
V
ref
V
ref
input
output
1.5 V
V
OL
+ 0.3 V
002aac197
3.0 V
0 V
V
TT
V
OL
t
PLH
t
PHL
V
ref
V
ref
1.5 V
1.5 V
input
output
002aab980
3.0 V
0 V
V
OH
V
OL
t
PHZ
t
PZH
1.5 V
1.5 V
input
output
1.5 V
V
OL
+ 0.3 V
GTL2008_GTL2107_2
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Product data sheet
Rev. 02 -- 26 September 2006
14 of 20
Philips Semiconductors
GTL2008; GTL2107
GTL translator with power good control and high-impedance outputs
13. Test information
R
L
-- Load resistor
C
L
-- Load capacitance; includes jig and probe capacitance
R
T
-- Termination resistance; should be equal to Z
o
of pulse generators.
Fig 12. Load circuit for A outputs (9AO)
Fig 13. Load circuit for B outputs
Fig 14. Load circuit for open-drain LVTTL I/O and open-drain outputs
Fig 15. Load circuit for 9AO OFF-state to LOW and LOW to OFF-state
PULSE
GENERATOR
V
O
CL
50 pF
002aab981
RL
500
RT
V
I
V
CC
DUT
PULSE
GENERATOR
DUT
V
O
CL
30 pF
50
002aab264
RT
V
I
V
CC
V
TT
PULSE
GENERATOR
DUT
V
O
C
L
21 pF
R
L
1.5 k
002aab265
R
T
V
I
V
CC
V
CC
PULSE
GENERATOR
DUT
V
O
CL
50 pF
RL
500
002aab982
RT
V
I
V
CC
6 V
RL
500
GTL2008_GTL2107_2
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Product data sheet
Rev. 02 -- 26 September 2006
15 of 20
Philips Semiconductors
GTL2008; GTL2107
GTL translator with power good control and high-impedance outputs
14. Package outline
Fig 16. Package outline SOT361-1 (TSSOP28)
UNIT
A
1
A
2
A
3
b
p
c
D
(1)
E
(2)
(1)
e
H
E
L
L
p
Q
Z
y
w
v
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
mm
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
9.8
9.6
4.5
4.3
0.65
6.6
6.2
0.4
0.3
0.8
0.5
8
0
o
o
0.13
0.1
0.2
1
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT361-1
MO-153
99-12-27
03-02-19
0.25
w
M
b
p
Z
e
1
14
28
15
pin 1 index
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
H
E
E
c
v
M
A
X
A
D
y
0
2.5
5 mm
scale
TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm
SOT361-1
A
max.
1.1
GTL2008_GTL2107_2
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Product data sheet
Rev. 02 -- 26 September 2006
16 of 20
Philips Semiconductors
GTL2008; GTL2107
GTL translator with power good control and high-impedance outputs
15. Soldering
15.1 Introduction to soldering surface mount packages
There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is recommended.
15.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement. Driven by legislation and
environmental forces the worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and cooling)
vary between 100 seconds and 200 seconds depending on heating method.
Typical reflow temperatures range from 215
C to 260
C depending on solder paste
material. The peak top-surface temperature of the packages should be kept below:
Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
15.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal results:
Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
For packages with leads on two sides and a pitch (e):
Table 14.
SnPb eutectic process - package peak reflow temperatures (from
J-STD-020C
July 2004)
Package thickness
Volume mm
3
< 350
Volume mm
3
350
< 2.5 mm
240
C + 0/
-
5
C
225
C + 0/
-
5
C
2.5 mm
225
C + 0/
-
5
C
225
C + 0/
-
5
C
Table 15.
Pb-free process - package peak reflow temperatures (from
J-STD-020C July
2004)
Package thickness
Volume mm
3
< 350
Volume mm
3
350 to
2000
Volume mm
3
> 2000
< 1.6 mm
260
C + 0
C
260
C + 0
C
260
C + 0
C
1.6 mm to 2.5 mm
260
C + 0
C
250
C + 0
C
245
C + 0
C
2.5 mm
250
C + 0
C
245
C + 0
C
245
C + 0
C
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Product data sheet
Rev. 02 -- 26 September 2006
17 of 20
Philips Semiconductors
GTL2008; GTL2107
GTL translator with power good control and high-impedance outputs
larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
For packages with leads on four sides, the footprint must be placed at a 45
angle to
the transport direction of the printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250
C
or 265
C, depending on solder material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal of corrosive residues in most
applications.
15.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage
(24 V or less) soldering iron applied to the flat part of the lead. Contact time must be
limited to 10 seconds at up to 300
C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 seconds to 5 seconds between 270
C and 320
C.
15.5 Package related soldering information
[1]
For more detailed information on the BGA packages refer to the
(LF)BGA Application Note (AN01026);
order a copy from your Philips Semiconductors sales office.
[2]
All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal or
external package cracks may occur due to vaporization of the moisture in them (the so called popcorn
effect). For details, refer to the Drypack information in the
Data Handbook IC26; Integrated Circuit
Packages; Section: Packing Methods.
Table 16.
Suitability of surface mount IC packages for wave and reflow soldering methods
Package
[1]
Soldering method
Wave
Reflow
[2]
BGA, HTSSON..T
[3]
, LBGA, LFBGA, SQFP,
SSOP..T
[3]
, TFBGA, VFBGA, XSON
not suitable
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP,
HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,
HVSON, SMS
not suitable
[4]
suitable
PLCC
[5]
, SO, SOJ
suitable
suitable
LQFP, QFP, TQFP
not recommended
[5][6]
suitable
SSOP, TSSOP, VSO, VSSOP
not recommended
[7]
suitable
CWQCCN..L
[8]
, PMFP
[9]
, WQCCN..L
[8]
not suitable
not suitable
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Product data sheet
Rev. 02 -- 26 September 2006
18 of 20
Philips Semiconductors
GTL2008; GTL2107
GTL translator with power good control and high-impedance outputs
[3]
These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no
account be processed through more than one soldering cycle or subjected to infrared reflow soldering with
peak temperature exceeding 217
C
10
C measured in the atmosphere of the reflow oven. The package
body peak temperature must be kept as low as possible.
[4]
These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the
solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink
on the top side, the solder might be deposited on the heatsink surface.
[5]
If wave soldering is considered, then the package must be placed at a 45
angle to the solder wave
direction. The package footprint must incorporate solder thieves downstream and at the side corners.
[6]
Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
[7]
Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger
than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
[8]
Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered
pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by
using a hot bar soldering process. The appropriate soldering profile can be provided on request.
[9]
Hot bar soldering or manual soldering is suitable for PMFP packages.
16. Abbreviations
17. Revision history
Table 17.
Abbreviations
Acronym
Description
CDM
Charged Device Model
CMOS
Complementary Metal Oxide Semiconductor
CPU
Central Processing Unit
DUT
Device Under Test
ESD
ElectroStatic Discharge
GTL
Gunning Transceiver Logic
HBM
Human Body Model
LVTTL
Low Voltage Transistor-Transistor Logic
MM
Machine Model
PRR
Pulse Rate Repetition
TTL
Transistor-Transistor Logic
VRD
Voltage Regulator Down
Table 18.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
GTL2008_GTL2107_2
20060926
Product data sheet
-
GTL2008_1
Modifications:
Added type number GTL2017
Section 1 "General description"
: added new 7th paragraph
Section 4 "Ordering information"
: added type number GTL2107PW to
Table 2 "Ordering
information"
and following paragraph
Table 10 "Limiting values"
: removed (old) Table note 1 (information is now in
Section 18
"Legal information"
)
added "DUT" to
Table 17 "Abbreviations"
GTL2008_1
20060502
Product data sheet
-
-
GTL2008_GTL2107_2
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Product data sheet
Rev. 02 -- 26 September 2006
19 of 20
Philips Semiconductors
GTL2008; GTL2107
GTL translator with power good control and high-impedance outputs
18. Legal information
18.1
Data sheet status
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term `short data sheet' is explained in section "Definitions".
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL
http://www.semiconductors.philips.com.
18.2
Definitions
Draft -- The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Philips Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet -- A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local Philips Semiconductors
sales office. In case of any inconsistency or conflict with the short data sheet,
the full data sheet shall prevail.
18.3
Disclaimers
General -- Information in this document is believed to be accurate and
reliable. However, Philips Semiconductors does not give any representations
or warranties, expressed or implied, as to the accuracy or completeness of
such information and shall have no liability for the consequences of use of
such information.
Right to make changes -- Philips Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use -- Philips Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a Philips Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. Philips Semiconductors accepts no liability for inclusion and/or use
of Philips Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is for the customer's own risk.
Applications -- Applications that are described herein for any of these
products are for illustrative purposes only. Philips Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values -- Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale -- Philips Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at
http://www.semiconductors.philips.com/profile/terms
, including those
pertaining to warranty, intellectual property rights infringement and limitation
of liability, unless explicitly otherwise agreed to in writing by Philips
Semiconductors. In case of any inconsistency or conflict between information
in this document and such terms and conditions, the latter will prevail.
No offer to sell or license -- Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
18.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
19. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
Document status
[1][2]
Product status
[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
Philips Semiconductors
GTL2008; GTL2107
GTL translator with power good control and high-impedance outputs
Koninklijke Philips Electronics N.V. 2006.
All rights reserved.
For more information, please visit: http://www.semiconductors.philips.com.
For sales office addresses, email to: sales.addresses@www.semiconductors.philips.com.
Date of release: 26 September 2006
Document identifier: GTL2008_GTL2107_2
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section `Legal information'.
20. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
4
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
5
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
6
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
6.1
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
Functional description . . . . . . . . . . . . . . . . . . . 5
7.1
Function tables . . . . . . . . . . . . . . . . . . . . . . . . . 5
8
Application design-in information . . . . . . . . . . 7
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8
10
Recommended operating conditions. . . . . . . . 8
11
Static characteristics. . . . . . . . . . . . . . . . . . . . . 9
12
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
12.1
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
13
Test information . . . . . . . . . . . . . . . . . . . . . . . . 14
14
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15
15
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
15.1
Introduction to soldering surface mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
15.2
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 16
15.3
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 16
15.4
Manual soldering . . . . . . . . . . . . . . . . . . . . . . 17
15.5
Package related soldering information . . . . . . 17
16
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18
17
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18
18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 19
18.1
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19
18.2
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
18.3
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
18.4
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
19
Contact information. . . . . . . . . . . . . . . . . . . . . 19
20
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20