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Электронный компонент: HEF4013BPB

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DATA SHEET
Product specification
File under Integrated Circuits, IC04
January 1995
INTEGRATED CIRCUITS
HEF4013B
flip-flops
Dual D-type flip-flop
For a complete data sheet, please also download:
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
January 1995
2
Philips Semiconductors
Product specification
Dual D-type flip-flop
HEF4013B
flip-flops
DESCRIPTION
The HEF4013B is a dual D-type flip-flop which features
independent set direct (S
D
), clear direct (C
D
), clock inputs
(CP) and outputs (O, O). Data is accepted when CP is
LOW and transferred to the output on the positive-going
edge of the clock. The active HIGH asynchronous
clear-direct (C
D
) and set-direct (S
D
) are independent and
override the D or CP inputs. The outputs are buffered for
best system performance. Schmitt-trigger action in the
clock input makes the circuit highly tolerant to slower clock
rise and fall times.
Fig.1 Functional diagram.
Fig.2 Pinning diagram.
FUNCTION TABLES
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
= positive-going transition
O
n
+
1 = state after clock positive transition
PINNING
FAMILY DATA, I
DD
LIMITS category FLIP-FLOPS
See Family Specifications
INPUTS
OUTPUTS
S
D
C
D
CP
D
O
O
H
L
X
X
H
L
L
H
X
X
L
H
H
H
X
X
H
H
INPUTS
OUTPUTS
S
D
C
D
CP
D
O
n
+
1
O
n
+
1
L
L
L
L
H
L
L
H
H
L
D
data inputs
CP
clock input (L to H edge-triggered)
S
D
asynchronous set-direct input (active HIGH)
C
D
asynchronous clear-direct input (active HIGH)
O
true output
O
complement output
HEF4013BP(N):
14-lead DIL; plastic
(SOT27-1)
HEF4013BD(F):
14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4013BT(D):
14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
January 1995
3
Philips Semiconductors
Product specification
Dual D-type flip-flop
HEF4013B
flip-flops
Fig.3 Logic diagram (one flip-flop).
January 1995
4
Philips Semiconductors
Product specification
Dual D-type flip-flop
HEF4013B
flip-flops
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
C; C
L
= 50 pF; input transition times
20 ns
V
DD
V
SYMBOL
MIN.
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
CP
O, O
5
110
220
ns
83 ns
+
(0,55 ns/pF) C
L
HIGH to LOW
10
t
PHL
45
90
ns
34 ns
+
(0,23 ns/pF) C
L
15
30
60
ns
22 ns
+
(0,16 ns/pF) C
L
5
95
190
ns
68 ns
+
(0,55 ns/pF) C
L
LOW to HIGH
10
t
PLH
40
80
ns
29 ns
+
(0,23 ns/pF) C
L
15
30
60
ns
22 ns
+
(0,16 ns/pF) C
L
S
D
O
5
100
200
ns
73 ns
+
(0,55 ns/pF) C
L
HIGH to LOW
10
t
PHL
40
80
ns
29 ns
+
(0,23 ns/pF) C
L
15
30
60
ns
22 ns
+
(0,16 ns/pF) C
L
S
D
O
5
75
150
ns
48 ns
+
(0,55 ns/pF) C
L
LOW to HIGH
10
t
PLH
35
70
ns
24 ns
+
(0,23 ns/pF) C
L
15
25
50
ns
17 ns
+
(0,16 ns/pF) C
L
C
D
O
5
100
200
ns
73 ns
+
(0,55 ns/pF) C
L
HIGH to LOW
10
t
PHL
40
80
ns
29 ns
+
(0,23 ns/pF) C
L
15
30
60
ns
22 ns
+
(0,16 ns/pF) C
L
C
D
O
5
60
120
ns
33 ns
+
(0,55 ns/pF) C
L
LOW to HIGH
10
t
PLH
30
60
ns
19 ns
+
(0,23 ns/pF) C
L
15
20
40
ns
12 ns
+
(0,16 ns/pF) C
L
Output transition times
5
60
120
ns
10 ns
+
(1,0 ns/pF) C
L
HIGH to LOW
10
t
THL
30
60
ns
9 ns
+
(0,42 ns/pF) C
L
15
20
40
ns
6 ns
+
(0,28 ns/pF) C
L
5
60
120
ns
10 ns
+
(1,0 ns/pF) C
L
LOW to HIGH
10
t
TLH
30
60
ns
9 ns
+
(0,42 ns/pF) C
L
15
20
40
ns
6 ns
+
(0,28 ns/pF) C
L
January 1995
5
Philips Semiconductors
Product specification
Dual D-type flip-flop
HEF4013B
flip-flops
AC CHARACTERISTI CS
V
SS
= 0 V; T
amb
= 25
C; C
L
= 50 pF; input transition times
20 ns
V
DD
V
SYMBOL
MIN.
TYP.
MAX.
Set-up time
5
40
20
ns
see also waveforms
Figs 4 and 5
D
CP
10
t
su
25
10
ns
15
15
5
ns
Hold time
5
20
0
ns
D
CP
10
t
hold
20
0
ns
15
15
0
ns
Minimum clock
5
60
30
ns
pulse width; LOW
10
t
WCPL
30
15
ns
15
20
10
ns
Minimum S
D
pulse
5
50
25
ns
width; HIGH
10
t
WSDH
24
12
ns
15
20
10
ns
Minimum C
D
pulse
5
50
25
ns
width; HIGH
10
t
WCDH
24
12
ns
15
20
10
ns
Recovery time
5
15
-
5
ns
for S
D
10
t
RSD
15
0
ns
15
15
0
ns
Recovery time
5
40
25
ns
for C
D
10
t
RCD
25
10
ns
15
25
10
ns
Maximum clock
5
7
14
MHz
pulse frequency
10
f
max
14
28
MHz
15
20
40
MHz
V
DD
V
TYPICAL FORMULA FOR P (
W)
Dynamic power
5
850 f
i
+
(f
o
C
L
)
V
DD
2
where
dissipation per
10
3 600 f
i
+
(f
o
C
L
)
V
DD
2
f
i
= input freq. (MHz)
package (P)
15
9 000 f
i
+
(f
o
C
L
)
V
DD
2
f
o
= output freq. (MHz)
C
L
= total load cap. (pF)
(f
o
C
L
) = sum of outputs
V
DD
= supply voltage (V)
January 1995
6
Philips Semiconductors
Product specification
Dual D-type flip-flop
HEF4013B
flip-flops
Fig.4
Waveforms showing set-up times, hold times and minimum clock pulse width. Set-up and hold times are
shown as positive values but may be specified as negative values.
Fig.5 Waveforms showing recovery times for S
D
and C
D
; minimum S
D
and C
D
pulse widths.
January 1995
7
Philips Semiconductors
Product specification
Dual D-type flip-flop
HEF4013B
flip-flops
APPLICATION INFORMATION
Some examples of applications for the HEF4013B are:
Counters/dividers
Registers
Toggle flip-flops
Fig.6 Typical application of the HEF4013B in an n-stage shift register.
Fig.7 Typical application of the HEF4013B in a binary ripple up-counter; divide-by-2
n
.
Fig.8 Typical application of the HEF4013B in a modified ring counter; divide-by-(n + 1).