DATA SHEET
Product specification
File under Integrated Circuits, IC04
January 1995
INTEGRATED CIRCUITS
HEF40174B
MSI
Hex D-type flip-flop
For a complete data sheet, please also download:
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
January 1995
2
Philips Semiconductors
Product specification
Hex D-type flip-flop
HEF40174B
MSI
DESCRIPTION
The HEF40174B is a hex edge-triggered D-type flip-flop
with six data inputs (D
0
to D
5
), a clock input (CP), an
overriding asynchronous master reset input (MR), and six
buffered outputs (O
0
to O
5
). Information on D
0
to D
5
is
transferred to O
0
to O
5
on the LOW to HIGH transition of
CP if MR is HIGH. When LOW, MR resets all flip-flops
(O
0
to O
5
= LOW) independent of CP and D
0
to D
5
.
Fig.1 Functional diagram.
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
HEF40174BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF40174BD(F):
16-lead DIL; ceramic (cerdip)
(SOT74)
HEF40174BT(D):
16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
PINNING
FUNCTION TABLE
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
= positive-going transition
= negative-going transition
D
0
to D
5
data inputs
CP
clock input (LOW to HIGH; edge-triggered)
MR
master reset input (active LOW)
O
0
to O
5
buffered outputs
INPUTS
OUTPUT
CP
D
MR
O
H
H
H
L
H
L
X
H
no change
X
X
L
L
January 1995
3
Philips Semiconductors
Product specification
Hex D-type flip-flop
HEF40174B
MSI
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Fig.3 Logic diagram.
January 1995
5
Philips Semiconductors
Product specification
Hex D-type flip-flop
HEF40174B
MSI
APPLICATION INFORMATION
Some examples of applications for the HEF40174B are:
Shift registers
Buffer/storage register
Pattern generator
V
DD
V
TYPICAL FORMULA FOR P(
W)
Dynamic power
5
3500 f
i
+
(f
o
C
L
)
V
DD
2
where
dissipation per
10
16 000 f
i
+
(f
o
C
L
)
V
DD
2
f
i
= input freq. (MHz)
package (P)
15
42 000 f
i
+
(f
o
C
L
)
V
DD
2
f
o
= output freq. (MHz)
C
L
= load capacitance (pF)
(f
o
C
L
) = sum of outputs
V
DD
= supply voltage (V)
Fig.4
Waveforms showing minimum pulse widths for CP and MR, MR to CP recovery time, and set-up time and
hold time for D
n
to CP. Set-up and hold times are shown as positive values but may be specified as
negative values.