Document Outline
- DESCRIPTION
- PINNING
- FAMILY DATA, IDD LIMITS category MSI
- FUNCTION TABLE
- AC CHARACTERISTICS
- APPLICATION INFORMATION
DATA SHEET
Product specification
File under Integrated Circuits, IC04
January 1995
INTEGRATED CIRCUITS
HEF40194B
MSI
4-bit bidirectional universal shift
register
For a complete data sheet, please also download:
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
January 1995
2
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register
HEF40194B
MSI
DESCRIPTION
The HEF40194B is a 4-bit bidirectional shift register with
two mode control inputs (S
0
and S
1
), a clock input (CP), a
serial data shift left input (D
SL
), a serial data shift right input
(D
SR
), four parallel data inputs (P
0
to P
3
), an overriding
asynchronous master reset input (MR), and four buffered
parallel outputs (O
0
to O
3
). When LOW, MR resets all
stages and forces O
0
to O
3
LOW, overriding all other input
conditions. When MR is HIGH, the operation mode is
controlled by S
0
and S
1
as shown in the function table.
Serial and parallel operation are edge-triggered on the
LOW to HIGH transition of CP. The inputs at which the
data are to be entered and S
0
, S
1
must be stable for a
set-up time before the LOW to HIGH transition of CP.
Fig.1 Functional diagram.
HEF40194BP(N):
16-lead DIL; plastic
(SOT38-1)
HEF40194BD(F):
16-lead DIL; ceramic (cerdip)
(SOT74)
HEF40194BT(D):
16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
PINNING
S
0
, S
1
mode control inputs
P
0
to P
3
parallel data inputs
D
SR
serial data shift right input
D
SL
serial data shift left input
CP
clock input (LOW to HIGH edge-triggered)
MR
master reset input (active LOW)
O
0
to O
3
buffered parallel outputs
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
January 1995
3
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register
HEF40194B
MSI
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Fig.3 Logic diagram.
January 1995
4
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register
HEF40194B
MSI
FUNCTION TABLE
Notes
1. H = HIGH state (the more positive voltage)
2. L = LOW state (the less positive voltage)
3. X = state is immaterial
4. t
n
+
1
= state after next LOW to HIGH transition of CP
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
C; input transition times
20 ns
INPUTS (MR = HIGH)
OUTPUTS AT T
n
+
1
OPERATING MODE
S
1
S
0
D
SR
D
SL
P
0
TO P
3
O
0
O
1
O
2
O
3
hold
L
L
X
X
X
O
0
O
1
O
2
O
3
shift left
H
L
X
L
X
O
1
O
2
O
3
L
H
L
X
H
X
O
1
O
2
O
3
H
shift right
L
H
L
X
X
L
O
0
O
1
O
2
L
H
H
X
X
H
O
0
O
1
O
2
parallel load
H
H
X
X
L
L
L
L
L
H
H
X
X
H
H
H
H
H
V
DD
V
TYPICAL FORMULA FOR P (
W)
Dynamic power
5
1 500 f
i
+
(f
o
C
L
)
V
DD
2
where
dissipation per
10
6 900 f
i
+
(f
o
C
L
)
V
DD
2
f
i
= input freq. (MHz)
package (P)
15
18 900 f
i
+
(f
o
C
L
)
V
DD
2
f
o
= output freq. (MHz)
C
L
= load cap. (pF)
(f
o
C
L
) = sum of outputs
V
DD
= supply voltage (V)
January 1995
5
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register
HEF40194B
MSI
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
C; C
L
= 50 pF; input transition times
20 ns
V
DD
V
SYMBOL
MIN.
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
CP
O
n
5
100
205
ns
73 ns
+
(0,55 ns/pF) C
L
HIGH to LOW
10
t
PHL
40
85
ns
29 ns
+
(0,23 ns/pF) C
L
15
30
60
ns
22 ns
+
(0,16 ns/pF) C
L
5
80
165
ns
53 ns
+
(0,55 ns/pF) C
L
LOW to HIGH
10
t
PLH
35
70
ns
24 ns
+
(0,23 ns/pF) C
L
15
25
55
ns
17 ns
+
(0,16 ns/pF) C
L
MR
O
n
5
85
175
ns
58 ns
+
(0,55 ns/pF) C
L
HIGH to LOW
10
t
PHL
40
80
ns
29 ns
+
(0,23 ns/pF) C
L
15
30
60
ns
22 ns
+
(0,16 ns/pF) C
L
Output transition times
5
60
120
ns
10 ns
+
(1,0 ns/pF) C
L
HIGH to LOW
10
t
THL
30
60
ns
9 ns
+
(0,42 ns/pF) C
L
15
20
40
ns
6 ns
+
(0,28 ns/pF) C
L
5
60
120
ns
10 ns
+
(1,0 ns/pF) C
L
LOW to HIGH
10
t
TLH
30
60
ns
9 ns
+
(0,42 ns/pF) C
L
15
20
40
ns
6 ns
+
(0,28 ns/pF) C
L
January 1995
6
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register
HEF40194B
MSI
Set-up times
5
80
40
ns
see also waveforms
Figs 4 and 5
P
n
, D
SR
, D
SL
CP
10
t
su
30
15
ns
15
20
10
ns
5
140
70
ns
S
n
CP
10
t
su
60
30
ns
15
40
20
ns
Hold times
5
10
-
30
ns
P
n
, D
SR
, D
SL
CP
10
t
hold
5
-
10
ns
15
5
-
5
ns
5
25
-
45
ns
S
n
CP
10
t
hold
15
-
15
ns
15
10
-
10
ns
Minimum clock
5
50
25
ns
pulse width; LOW
10
t
WCPL
20
10
ns
15
20
10
ns
Minimum MR
5
80
40
ns
pulse width; LOW
10
t
WMRL
40
20
ns
15
30
15
ns
Recovery time
5
30
10
ns
for MR
10
t
RMR
15
5
ns
15
15
5
ns
Maximum clock
5
6
12
MHz
pulse frequency
10
f
max
15
30
MHz
15
20
40
MHz
V
DD
V
SYMBOL
MIN.
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA
January 1995
7
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register
HEF40194B
MSI
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Fig.4
Waveforms showing set-up times, hold times for D
SR
, D
SL
and P
n
inputs; minimum MR pulse width, MR to output delays and MR to CP
recovery time; minimum CP pulse width and CP to output delays. Set-up and hold times are shown as positive values but may be
specified as negative values.
January 1995
8
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register
HEF40194B
MSI
APPLICATION INFORMATION
Some examples of applications for the HEF40194B are:
Arithmetic unit register
Serial/parallel converter.
Fig.5
Waveforms showing set-up times and hold times for S
0
and S
1
inputs. Set-up and hold times are shown
as positive values but may be specified as negative values.
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