DATA SHEET
Product specification
File under Integrated Circuits, IC04
January 1995
INTEGRATED CIRCUITS
HEF4066B
gates
Quadruple bilateral switches
For a complete data sheet, please also download:
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
January 1995
2
Philips Semiconductors
Product specification
Quadruple bilateral switches
HEF4066B
gates
DESCRIPTION
The HEF4066B has four independent bilateral analogue
switches (transmission gates). Each switch has two
input/output terminals (Y/Z) and an active HIGH enable
input (E). When E is connected to V
DD
a low impedance
bidirectional path between Y and Z is established (ON
condition). When E is connected to V
SS
the switch is
disabled and a high impedance between Y and Z is
established (OFF condition).
The HEF4066B is pin compatible with the HEF4016B but
exhibits a much lower ON resistance. In addition the ON
resistance is relatively constant over the full input signal
range.
Fig.1 Functional diagram.
Fig.2 Pinning diagram.
HEF4066BP(N):
14-lead DIL; plastic (SOT27-1)
HEF4066BD(F):
14-lead DIL; ceramic (cerdip)
(SOT73))
HEF4066BT(D):
14-lead SO; plastic (SOT108-1)
( ): Package Designator North America
PINNING
APPLICATION INFORMATION
An example of application for the HEF4066B is:
Analogue and digital switching
E
0
to E
3
enable inputs
Y
0
to Y
3
input/output terminals
Z
0
to Z
3
input/output terminals
Fig.3 Schematic diagram (one switch).
January 1995
3
Philips Semiconductors
Product specification
Quadruple bilateral switches
HEF4066B
gates
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
DC CHARACTERISTICS
T
amb
= 25
C
Power dissipation per switch
P
max.
100
mW
For other RATINGS see Family Specifications
V
DD
V
SYMBOL
MIN.
TYP.
MAX.
CONDITIONS
ON resistance
5
R
ON
-
350
2500
E
n
at V
DD
10
-
80
245
V
is
= V
SS
to V
DD
15
-
60
175
see Fig.4
ON resistance
5
R
ON
-
115
340
E
n
at V
DD
10
-
50
160
V
is
= V
SS
15
-
40
115
see Fig.4
ON resistance
5
R
ON
-
120
365
E
n
at V
DD
10
-
65
200
V
is
= V
DD
15
-
50
155
see Fig.4
`
' ON resistance
5
R
ON
-
25
-
E
n
at V
DD
between any two
10
-
10
-
V
is
= V
SS
to V
DD
channels
15
-
5
-
see Fig.4
OFF state leakage
5
I
OZ
-
-
-
nA
E
n
at V
SS
current, any
10
-
-
-
nA
channel OFF
15
-
-
200 nA
E
n
input voltage
5
V
IL
-
2,25
1 V
I
is
= 10
A
see Fig.9
LOW
10
-
4,50
2 V
15
-
6,75
2 V
V
DD
V
SYMBOL
T
amb
(
c)
CONDITIONS
-
40
+
25
+
85
MAX.
MAX.
MAX.
Quiescent device
5
I
DD
1,0
1,0
7,5
A
V
SS
= 0; all valid
current
10
2,0
2,0
15,0
A
input combinations;
15
4,0
4,0
30,0
A
V
I
= V
SS
or V
DD
Input leakage current at E
n
15
I
IN
-
300
1000 nA
E
n
at V
SS
or V
DD
January 1995
4
Philips Semiconductors
Product specification
Quadruple bilateral switches
HEF4066B
gates
NOTE
To avoid drawing V
DD
current out of terminal Z, when switch current flows into terminals Y, the voltage drop across the
bidirectional switch must not exceed 0,4 V. If the switch current flows into terminal Z, no V
DD
current will flow out of
terminals Y, in this case there is no limit for the voltage drop across the switch, but the voltages at Y and Z may not
exceed V
DD
or V
SS
.
Fig.4 Test set-up for measuring R
ON
.
Fig.5 Typical R
ON
as a function of input voltage.
E
n
at V
DD
I
is
= 200
A
V
SS
= 0 V
January 1995
5
Philips Semiconductors
Product specification
Quadruple bilateral switches
HEF4066B
gates
AC CHARACTERISTICS
(1)
,
(2)
V
SS
= 0 V; T
amb
= 25
C; input transition times
20 ns
V
DD
V
SYMBOL
TYP.
MAX.
Propagation delays
V
is
V
os
5
10
20
ns
note 3
HIGH to LOW
10
t
PHL
5
10
ns
15
5
10
ns
5
10
20
ns
note 3
LOW to HIGH
10
t
PLH
5
10
ns
15
5
10
ns
Output disable times
E
n
V
os
5
80
160
ns
note 4
HIGH
10
t
PHZ
65
130
ns
15
60
120
ns
5
80
160
ns
note 4
LOW
10
t
PLZ
70
140
ns
15
70
140
ns
Output enable times
E
n
V
os
5
40
80
ns
note 4
HIGH
10
t
PZH
20
40
ns
15
15
30
ns
5
45
90
ns
note 4
LOW
10
t
PZL
20
40
ns
15
15
30
ns
Distortion, sine-wave
5
0,25
%
note 5
response
10
0,04
%
15
0,04
%
Crosstalk between
5
-
MHz
note 6
any two channels
10
1
MHz
15
-
MHz
Crosstalk; enable
5
-
mV
note 7
input to output
10
50
mV
15
-
mV
OFF-state
5
-
MHz
note 8
feed-through
10
1
MHz
15
-
MHz
ON-state frequency
5
-
MHz
note 9
response
10
90
MHz
15
-
MHz
January 1995
6
Philips Semiconductors
Product specification
Quadruple bilateral switches
HEF4066B
gates
Notes
1. V
is
is the input voltage at a Y or Z terminal, whichever is assigned as input.
2. V
os
is the output voltage at a Y or Z terminal, whichever is assigned as output.
3. R
L
= 10 k
to V
SS
; C
L
= 50 pF to V
SS
; E
n
= V
DD
; V
is
= V
DD
(square-wave); see Figs 6 and 10.
4. R
L
= 10 k
; C
L
= 50 pF to V
SS
; E
n
= V
DD
(square-wave);
V
is
= V
DD
and R
L
to V
SS
for t
PHZ
and t
PZH
;
V
is
= V
SS
and R
L
to V
DD
for t
PLZ
and t
PZL
; see Figs 6 and 11.
5. R
L
= 10 k
; C
L
= 15 pF; E
n
= V
DD
; V
is
=
1
/
2
V
DD(p-p)
(sine-wave, symmetrical about
1
/
2
V
DD
); f
is
= 1 kHz; see Fig.7.
6. R
L
= 1 k
; V
is
=
1
/
2
V
DD(p-p)
(sine-wave, symmetrical about
1
/
2
V
DD
);
7. R
L
= 10 k
to V
SS
; C
L
= 15 pF to V
SS
; E
n
= V
DD
(square-wave); crosstalk is
V
os
(peak value); see Fig.6.
8. R
L
= 1 k
; C
L
= 5 pF; E
n
= V
SS
; V
is
=
1
/
2
V
DD(p-p)
(sine-wave, symmetrical about
1
/
2
V
DD
);
9. R
L
= 1 k
; C
L
= 5 pF; E
n
= V
DD
; V
is
=
1
/
2
V
DD(p-p)
(sine-wave, symmetrical about
1
/
2
V
DD
);
V
DD
V
TYPICAL FORMULA FOR P (
W)
Dynamic power
5
800 f
i
+
(f
o
C
L
)
V
DD
2
where
dissipation per
10
3 500 f
i
+
(f
o
C
L
)
V
DD
2
f
i
= input freq. (MHz)
package (P)
15
10 100 f
i
+
(f
o
C
L
)
V
DD
2
f
o
= output freq. (MHz)
C
L
= load capacitance (pF)
(f
o
C
L
) = sum of outputs
V
DD
= supply voltage (V)
20 log
V
os
(B)
V
is
A
( )
-------------------
-50 dB; E
n
(A)
V
SS
E
;
n
B
( )
V
DD
; see Fig. 8.
=
=
=
20 log
V
os
V
is
---------
-50 dB; see Fig. 7.
=
20 log
V
os
V
is
---------
-3 dB; see Fig. 7.
=
Fig.6
Fig.7
January 1995
7
Philips Semiconductors
Product specification
Quadruple bilateral switches
HEF4066B
gates
Fig.8
Fig.9
January 1995
8
Philips Semiconductors
Product specification
Quadruple bilateral switches
HEF4066B
gates
Fig.10 Waveforms showing propagation delays from V
is
to V
os
.
Fig.11 Waveforms showing output disable and enable times.
(1) V
is
at V
DD
(2) V
is
at V
SS
.
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