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Электронный компонент: HEF4085BD

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DATA SHEET
Product specification
File under Integrated Circuits, IC04
January 1995
INTEGRATED CIRCUITS
HEF4085B
gates
Dual 2-wide 2-input AND-OR-invert
gate
For a complete data sheet, please also download:
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
January 1995
2
Philips Semiconductors
Product specification
Dual 2-wide 2-input AND-OR-invert gate
HEF4085B
gates
DESCRIPTION
The HEF4085B is a dual 2-wide 2-input AND-OR-invert
gate, each with an additional input (A
4
or B
4
) which can be
used as either an expander input or an inhibit input. A
HIGH on A
4
or B
4
forces the output (O
A
or O
B
) LOW
independent of the other inputs (A
0
to A
3
or B
0
to B
3
). The
outputs O
A
and O
B
are fully buffered for highest noise
immunity and pattern insensitivity of output impedance.
Fig.1 Functional diagram.
HEF4085BP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4085BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4085BT(D): 14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
Fig.3 Logic diagram (one gate).
LOGIC FUNCTION
FAMILY DATA,
I
DD
LIMITS category GATES
See Family Specifications
O
A
A
0
A
1
A
2
A
3
A
4
+
+
=
O
B
B
0
B
1
B
2
B
3
B
4
+
+
=
January 1995
3
Philips Semiconductors
Product specification
Dual 2-wide 2-input AND-OR-invert gate
HEF4085B
gates
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
C; C
L
= 50 pF; input transition times
20 ns
V
DD
V
SYMBOL
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
A
n
, B
n
O
n
5
75
155 ns
48 ns
+
(0,55 ns/pF) C
L
HIGH to LOW
10
t
PHL
30
60 ns
19 ns
+
(0,23 ns/pF) C
L
15
20
40 ns
12 ns
+
(0,16 ns/pF) C
L
5
65
135 ns
38 ns
+
(0,55 ns/pF) C
L
LOW to HIGH
10
t
PLH
30
55 ns
19 ns
+
(0,23 ns/pF) C
L
15
20
40 ns
12 ns
+
(0,16 ns/pF) C
L
Output transition times
5
60
120 ns
10 ns
+
(1,0
ns/pF) C
L
HIGH to LOW
10
t
THL
30
60 ns
9 ns
+
(0,42 ns/pF) C
L
15
20
40 ns
6 ns
+
(0,28 ns/pF) C
L
5
60
120 ns
10 ns
+
(1,0
ns/pF) C
L
LOW to HIGH
10
t
TLH
30
60 ns
9 ns
+
(0,42 ns/pF) C
L
15
20
40 ns
6 ns
+
(0,28 ns/pF) C
L
V
DD
V
TYPICAL FORMULA FOR P (
W)
Dynamic power
5
750 f
i
+
(f
o
C
L
)
V
DD
2
where
dissipation per
10
3200 f
i
+
(f
o
C
L
)
V
DD
2
f
i
= input freq. (MHz)
package (P)
15
9200 f
i
+
(f
o
C
L
)
V
DD
2
f
o
= output freq. (MHz)
C
L
= load capacitance (pF)
(f
o
C
L
) = sum of outputs
V
DD
= supply voltage (V)