DATA SHEET
Product specification
File under Integrated Circuits, IC04
January 1995
INTEGRATED CIRCUITS
HEF4751V
LSI
Universal divider
For a complete data sheet, please also download:
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
January 1995
2
Philips Semiconductors
Product specification
Universal divider
HEF4751V
LSI
DESCRIPTION
The HEF4751V is a universal divider (U.D.) intended for
use in high performance phase lock loop frequency
synthesizer systems. It consists of a chain of counters
operating in a programmable feedback mode.
Programmable feedback signals are generated for up to
three external (fast)
10/11 prescaler.
The system comprising one HEF4751V U.D. together with
prescalers is a fully programmable divider with a maximum
configuration of: 5 decimal stages, a programmable mode
M stage (1
M
16, non-decimal fraction channel
selection), and a mode H stage (H = 1 or 2, stage for half
channel offset).
Programming is performed in BCD code in a bit-parallel,
digit-serial format.
To accommodate fixed or variable frequency offset, two
numbers are applied in parallel, one being subtracted from
the other to produce the internal programme.
The decade selection address is generated by an internal
programme counter which may run continuously or on
demand. Two or more universal dividers can be cascaded,
each extra U.D. (in slave mode) adds two decades to the
system. The combination retains the full programmability
and features of a single U.D. The U.D. provides a fast
output signal FF at output OFF, which can have a phase
jitter of
1 system input period, to allow fast frequency
locking. The slow output signal FS at output OFS, which is
jitter-free, is used for fine phase control at a lower speed.
Fig.1 Pinning diagram.
SUPPLY VOLTAGE
FAMILY DATA, I
DD
LIMITS category LSI
See Family Specifications
HEF4751VP(N):
28-lead DIL; plastic (SOT117)
HEF4751VD(F):
28-lead DIL; ceramic (cerdip) (SOT135V)
HEF4751VT(D):
28-lead SO; plastic (SOT136A)
( ): Package Designator North America
RATING
RECOMMENDED OPERATING
-
0,5 to
+
18
4,5 to 12,5 V
January 1995
3
Philips Semiconductors
Product specification
Universal divider
HEF4751V
LSI
Fig.2 Block diagram.
January 1995
4
Philips Semiconductors
Product specification
Universal divider
HEF4751V
LSI
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Fig.3 The HEF4751V U.D. used in a system with 3 (fast) prescalers.
1
M
16; 1
H
2; n
5
>
0; f
i
/f
OFS
= {(n
5
10
4
+
n
4
10
3
+
n
3
10
2
+
n
2
10
+
n
1
) M
+
n
0
} H
+
n
h
.
January 1995
5
Philips Semiconductors
Product specification
Universal divider
HEF4751V
LSI
Fig.4 Timing diagram showing programme data inputs.
Allocation of data input
FETCH
PERIOD
INPUTS
A
3
A
2
A
1
A
0
B
3
B
2
B
1
B
0
SI
0
n
0A
n
0B
b
in
1
n
1A
n
1B
X
2
n
2A
n
2B
X
3
n
3A
n
3B
X
4
n
4A
n
4B
X
5
n
5A
n
5B
X
6
M
C0
b
control
1
/
2
channel
control
X
Allocation of data input B3 to B0 during fetch period 6
Notes
1. H = HIGH state (the more positive voltage)
2. L = LOW state (the less positive voltage)
3. X = state is immaterial
B
3
B
2
C0
b
DIVISION RATIO
L
L
1
L
H
2
H
L
5
H
H
10/11
B
1
B
0
1
/
2
CHANNEL CONFIGURATION
L
L
H = 1
L
H
H = 2; n
h
= 0
H
H
H = 2; n
h
= 1
H
L
test state
January 1995
6
Philips Semiconductors
Product specification
Universal divider
HEF4751V
LSI
PROGRAMME DATA INPUT (see also Figs 3 and 4)
The programming process is timed and controlled by input
PC and PE. When the programme enable (PE) input is
HIGH; the positive edges of the programme clock (PC)
signal step through the internal programme counter in a
sequence of 8 states. Seven states define fetch periods,
each indicated by a LOW signal at one of the
corresponding data address outputs (OD
0
to OD
6
). These
data address signals may be used to address the external
programme source. The data fetched from the programme
source is applied to inputs A
0
to A
3
and B
0
to B
3
. When PC
is LOW in a fetch period an internal load pulse is
generated, the data is valid during this time and has to be
stable. When PE is LOW, the programming cyclus is
interrupted on the first positive edge of PC. On the next
negative edge at input PC fetch period 6 is entered. Data
may enter asynchronously in fetch period 6.
Ten blocks in the U.D. need programme input signals (see
Fig.2). Four of these (C0
b
, C3, C4 and RSH) are
concerned with the configuration of the U.D. and are
programmed in fetch period 6. The remaining blocks (RS0
to RS4 and C1) are programmed with number P,
consisting of six internal digits n
0
to n
5
.
P = (n
5
10
4
+
n
4
10
3
+
n
3
10
2
+
n
2
10
+
n
1
)
M
+
n
0
These digits are formed by a substractor from two external
numbers A and B and a borrow-in (b
in
).
P = A
-
B
-
b
in
or if this result is negative;
P = A
-
B
-
b
in
+
M
10
5
.
The numbers A and B, each consisting of six four bit digits
n
0A
to n
5A
and n
0B
to n
5B
, are applied in fetch period 0 to 5
to the inputs A
0
to A
3
(data A) and B
0
to B
3
(data B) in
binary coded negative logic.
A = (n
5A
10
4
+
n
4A
10
3
+
n
3A
10
2
+
n
2A
10
+
n
1A
)
M
+
n
0A
.
B = (n
5B
10
4
+
n
4B
10
3
+
n
3B
10
2
+
n
2B
10
+
n
1B
)
M
+
n
0B
.
Borrow-in (b
in
) is applied via input SI in fetch period 0
(SI = HIGH: borrow, SI = LOW: no borrow).
Counter C1 is automatically programmed with the most
significant non-zero digit (n
ms
) from the internal digits n
5
to
n
2
of number P. The counter chain C
-
2 to C1 (see Fig.3)
is fully programmable by the use of pulse rate feedback.
Rate feedback is generated by the rate selectors RS4 to
RS0 and RSH, which are programmed with digits n
4
to
n
0
and n
h
respectively. In fetch period 6 the fractional
counter C3, half channel counter C4 and C0
b
are
programmed and configured via data B inputs. Counter C3
is programmed in fetch period 6 via data A inputs in
negative logic (except all HIGH is understood as: M = 16).
The counter C0 is a side steppable 10/11 counter
composed of an internal part C0
b
and an external part C0
a
.
C0
b
is configured via B
3
and B
2
to a division ratio of 1 or 2
or 5 or 10/11; C0
a
must have the complementary ratio
10/11 or 5/6 or 2/3 or 1 respectively. In the latter case
C0
b
comprises the whole C0 counter with internal
feedback, C0
a
is then not required.
The half channel counter C4 is enabled with B
0
= HIGH
and disabled with B
0
= LOW. With C4 enabled, a half
channel offset can be programmed with input B
1
= HIGH,
and no offset with B
1
= LOW.
FEEDBACK TO PRESCALERS (see also Figs 5 and 6)
The counters C1, C0, C
-
1 and C
-
2 are side-steppable
counters, i.e. its division ratio may be increased by one, by
applying a pulse to a control terminal for the duration of
one division cycle. Counter C2 has 10 states, which are
accessible as timing signals for the rate selectors RS1 to
RS4. A rate selector, programmed with n (n
1
to n
4
in the
U.D.) generates n of 10 basic timing periods an active
signal. Since n
9, 1 of 10 periods is always non-active. In
this period RS1 transfers the output of rate selector RS0,
which is timed by counter C3 and programmed with n
0
.
Similarly, RS0 transfers RSH output during one period of
C3. Rate selector RSH is timed by C4 and programmed
with n
h
. In one of the two states of C4, if enabled, or
always, if C4 is disabled, RSH transfers the LOW active
signal at input RI to RS0. If RI is not used it must be
connected to HIGH. The feedback output signals of RS1,
RS2 and RS3 are externally available as active LOW
signals at outputs OFB
1
, OFB
2
and OFB
3
.
Output OFB
1
is intended for the prescaler at the highest
frequency (if present), OFB
2
for the next (if present) and
OFB
3
for the lowest frequency prescaler (if present). A
prescaler needs a feedback signal, which is timed on one
of its own division cycles in a basic timing period. The
timing signal at OSY is LOW during the last U.D. input
period of a basic timing period and is suitable for timing of
the feedback for the last external prescaler. The
synchronization signal for a preceding prescaler is the
OR-function of the sync. input and sync. output of the
following prescaler (all sync. signals active LOW).
January 1995
7
Philips Semiconductors
Product specification
Universal divider
HEF4751V
LSI
Fig.5 Block diagram showing feedback to prescalers.
Fig.6 Timing diagram showing signals occurring in Fig.5.
January 1995
8
Philips Semiconductors
Product specification
Universal divider
HEF4751V
LSI
CASCADING OF U.D.s (see also Fig. 8)
A U.D. is programmed into the `slave' mode by the
programme input data: n
2A
= 11, n
2B
= 10,
n
3A
= n
4A
= n
3B
= n
4B
= n
5B
= 0. A U.D. operating in the
slave mode performs the function of two extra
programmable stages C2' and C3' to a `master' (not slave)
mode operating U.D. More slave U.D.s may be used,
every slave adding two lower significant digits to the
system.
Output OFB
3
is converted to the borrow output of the
programme data subtractor, which is valid after fetch
period 5. Input SI is the borrow input (both in master and in
slave mode), which has to be valid in fetch period 0. Input
SI has to be connected to output OFB
3
of a following slave,
if not present, to LOW. For proper transfer of the borrow
from a lower to a higher significant U.D. subtractor, the
U.D.s have to be programmed sequentially in order of
significance or synchronously if the programme is
repeated at least the number of U.D.s in the system.
Rate input RI and output OFS must be connected to rate
output OFB
1
and the input IN of the next slave U.D. The
combination thus formed retains the full programmability
and features of one U.D.
OUTPUT (see also Fig.7)
The normal output of the U.D. is the slow output OFS,
which consists of evenly spaced LOW pulses. This output
is intended for accurate phase comparison. If a better
frequency acquisition time is required, the fast output OFF
can be used. The output frequency on OFF is a factor
M
H higher than the frequency on OFS. However, phase
jitter of maximum
1 system input period occurs at OFF,
since the division ratio of the counters preceding OFF are
varied by slow feedback pulse trains from rate selectors
following OFF.
Fig.7 Timing diagram showing output pulses.
January 1995
9
Philips Semiconductors
Product specification
Universal divider
HEF4751V
LSI
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Fig.8 Block diagram showing cascading of U.Ds.
January 1995
10
Philips Semiconductors
Product specification
Universal divider
HEF4751V
LSI
DC CHARACTERISTICS
V
SS
= 0 V
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
C; input transition times
20 ns
V
DD
V
V
OH
V
V
OL
V
SYMBOL
T
amb
(
C)
-
40
+
25
+
85
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Output (sink)
4,75
0,4
1,6
1,4
1,1
mA
current LOW
5
0,4
I
OL
1,7
1,5
1,2
mA
10
0,5
2,9
2,7
2,2
mA
Output (source)
5
4,6
1,0
0,85
0,55
mA
current HIGH
5
2,5
-
I
OH
3,0
2,5
1,7
mA
10
9,5
3,0
2,5
1,7
mA
PARAMETER
V
DD
V
SYMBOL
MIN.
TYP.
MAX.
UNIT
Propagation delay
5
t
PHL
135
270 ns
C
L
= 10 pF
IN
OSY
10
45
90 ns
HIGH to LOW
Output transition
times
HIGH to LOW
5
t
THL
30
60 ns
C
L
= 50 pF
10
12
25 ns
LOW to HIGH
5
t
TLH
45
90 ns
C
L
= 50 pF
10
20
40 ns
Maximum input
5
f
max
4
8
MHz
= 50%
frequency; IN
10
12
24
MHz
C0
b
ratio
>
1
Maximum input
5
f
max
2
4
MHz
= 50%
frequency; IN
10
6
12
MHz
C0
b
ratio = 1
Maximum input
5
f
max
0,15
0,3
MHz
frequency; PC
10
0,5
1,0
MHz
V
DD
V
TYPICAL FORMULA FOR P (
W)
Dynamic power
where
dissipation per
5
1 200 f
i
+
(f
o
C
L
)
V
DD
2
f
i
= input freq. (MHz)
package (P)
10
5 400 f
i
+
(f
o
C
L
)
V
DD
2
f
o
= output freq. (MHz)
C
L
= load capacitance (pF)
(f
o
C
L
) = sum of outputs
V
DD
= supply voltage (V)
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