Document Outline
- FEATURES
- DESCRIPTION
- PIN CONFIGURATION
- ORDERING INFORMATION
- INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
- LOGIC SYMBOL
- IEC/IEEE SYMBOL
- LOGIC DIAGRAM
- MODE-SELECT FUNCTION TABLE
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS
- DC ELECTRICAL CHARACTERISTICS
- AC ELECTRICAL CHARACTERISTICS
- AC WAVEFORMS
- TEST CIRCUIT AND WAVEFORMS
Philips Semiconductors FAST Products
Product specification
74F181
Arithmetic logic unit
1
March 3, 1989
8530351 95947
FEATURES
Provides 16 arithmetic operation: add, subtract, compare, and
double; plus 12 other arithmetic operations
Provides all 16 logic operations of two variables: Exclusive-OR,
Compare, AND, NAND, NOR, OR, plus 10 other logic operations
Full look-ahead carry for high speed arithmetic operation on long
words
40% faster than 'S181 with only 30% 'S181 power consumption
Available in 300mil-wide Slim 24-pin Dual In-Line package
DESCRIPTION
The 74F181 is a 4-bit high-speed parallel Arithmetic Logic Unit
(ALU). Controlled by the four Function Select inputs (S0S3) and
the Mode Control input (M), it can perform all the 16 possible logic
operations or 16 different arithmetic operations on active-High or
active-Low operands. The Function Table lists these operations.
PIN CONFIGURATION
SF00193
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
B0
A0
S3
S2
S1
S0
Cn
M
F0
F1
F2
VCC
A1
B1
A2
B2
A3
B3
C
n+4
G
P
A=B
F3
GND
TYPE
TYPICAL PROPAGATION DELAY
TYPICAL
SUPPLY CURRENT
(TOTAL)
74F181
7.0ns
43mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
10%, T
amb
= 0
C to +70
C
24-Pin Plastic Slim DIP (300 mil)
N74F181N
24-Pin Plastic SOL
N74F181D
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
LOAD VALUE HIGH/LOW
A0A3
A operand inputs
1.0/3.0
20
A/1.8mA
B0B3
B operand inputs
1.0/3.0
20
A/1.8mA
M
Mode control input
1.0/1.0
20
A/0.6mA
S0S3
Function select input
1.0/4.0
20
A/2.4mA
Cn
Carry input
1.0/5.0
20
A/3.0mA
C
n+4
Carry output
50/33
1.0mA/20mA
P
Carry Propagate output
50/33
1.0mA/20mA
G
Carry Generate output
50/33
1.0mA/20mA
A=B
Compare output
OC/33
OC/20mA
F0F3
Outputs
50/33
1.0mA/20mA
NOTE:
One (1.0) FAST unit load is defined as: 20
A in the High state and 0.6mA in the Low state.
OC = Open Collector
Philips Semiconductors FAST Products
Product specification
74F181
Arithmetic logic unit
March 3, 1989
2
LOGIC SYMBOL
7
8
6
5
4
3
Cn
M
S0
S1
S2
S3
A0 B0 A1 B1 A2 B2 A3 B3
2
1
23 22
21 20
19 18
9
10
11
13
F0 F1 F2 F3
16
14
17
15
A=B
G
P
C
n+4
Active-High Operands
7
8
6
5
4
3
Cn
M
S0
S1
S2
S3
A0 B0 A1 B1 A2 B2 A3 B3
2
1
23 22
21 20
19 18
9
10
11
13
F0 F1 F2 F3
16
14
17
15
A=B
G
P
C
n+4
Active-Low Operands
V
CC
= Pin 24
GND = Pin 12
SF00196
IEC/IEEE SYMBOL
SF00197
0
1
2
3
5
6
ALU
[T]
P0
Q0
9
4
M
0
21
8
7
CI
4
17
15
16
14
CP
CG
CO
P=G
22
23
P1
Q1
10
20
21
P2
Q2
11
18
19
P3
Q3
13
Philips Semiconductors FAST Products
Product specification
74F181
Arithmetic logic unit
March 3, 1989
3
LOGIC DIAGRAM
S0
6
S1
5
S2
4
S3
B3
3
18
A3
19
B2
20
A2
21
A1
23
A0
2
M
8
7
B1
22
B0
1
Cn
V
CC
= Pin 24
GND = Pin 12
17
G
16
C
n+4
15
P
13
F3
11
F2
14
A=B
10
F1
9
F0
SF00194
Philips Semiconductors FAST Products
Product specification
74F181
Arithmetic logic unit
March 3, 1989
4
When the Mode Control input (M) is High, all internal carries are
inhibited and the device performs logic operations on the individual
bits as listed. When the Mode control input is Low, the carries are
enabled and the device performs arithmetic operations on the two
4-bit words. The device incorporates full internal carry look-ahead
and provides for either ripple carry between device using the C
n+4
output, or for carry look-ahead between packages using the signals
P (Carry Propagate) and G (Carry Generate). P and G are not
affected by carry in. When speed requirements are not stringent, it
can be used in a simple ripple carry mode by connecting the Carry
output (C
n+4
) signal to the Carry input (Cn) of the next unit. For
high-speed operation, the device is used in conjunction with the
74F182 carry look-ahead circuit. One carry look-ahead package is
required for each group of four 74F181 devices. Carry look-ahead
can be provided at various levels and offers high speed capability
over extremely long word lengths.
The A=B output from the device goes High when all four F outputs
are High and can be used to indicate logic equivalence over 4-bits
when the unit is in the subtract mode. The A=B output is
open-collector and can be wired-AND with other A=B outputs to give
a comparison for more than 4 bits. The A=B signal can also be used
with the C
n+4
signal to indicate A>B and A<B. The Function Table
lists the arithmetic operations that are performed without a carry in.
An incoming carry adds a one to each operation. Thus select code
LHHL generates A minus B minus 1 (two's complement notation)
without a carry in and generates A minus B when a carry is applied.
Because subtraction is actually performed by complementary
addition (one's complement), a carry out means borrow; thus, a
carry is generated when there is no underflow and no carry is
generated when there is underflow. As indicated, this device can be
used with either active-Low inputs producing active-Low outputs or
with active-High inputs producing active-High outputs. For either
case, the table lists the operations that are performed to the
operands labeled inside the logic symbol.
MODE-SELECT FUNCTION TABLE
MODE SELECT INPUTS
ACTIVE HIGH INPUTS & OUTPUTS
ACTIVE LOW INPUTS & OUTPUTS
S3
S2
S1
S0
Logic (M=H)
Arithmetic** (M=L) (Cn=H)
Logic (M=H)
Arithmetic** (M=L) (Cn=L)
L
L
L
L
A
A
A
A minus 1
L
L
L
H
A+B
A+B
AB
AB minus 1
L
L
H
L
AB
A+B
A+B
AB minus 1
L
L
H
H
Logical 0
minus 1
Logical 1
minus 1
L
H
L
L
AB
A plus AB
A+B
A plus (A+B)
L
H
L
H
B
(A+B) plus AB
B
AB plus (A+B)
L
H
H
L
A
B
A minus B minus 1
A
B
A minus B minus 1
L
H
H
H
AB
AB minus 1
A+B
A+B
H
L
L
L
A+B
A plus AB
AB
A plus (A+B)
H
L
L
H
A
B
A plus B
A
B
A plus B
H
L
H
L
B
(A+B) plus AB
B
AB plus (A+B)
H
L
H
H
AB
AB minus 1
A+B
A+B
H
H
L
L
Logical 1
A plus A*
Logical 0
A plus A*
H
H
L
H
A+B
(A+B) plus A
AB
AB plus A
H
H
H
L
A+B
(A+B) plus A
AB
AB plus A
H
H
H
H
A
A minus 1
A
A
H = High voltage level
L
= Low voltage level
*
= Each bit is shifted to the next more significant position.
** = Arithmetic operations expressed in two's complement notation.
Philips Semiconductors FAST Products
Product specification
74F181
Arithmetic logic unit
March 3, 1989
5
Table 1. Sum Mode Test
Function Inputs: S0 = S3 = 4.5V,
S1 = S2 = M = 0V
PARAMETER
INPUT
UNDER TEST
OTHER INPUT, SAME BIT
OTHER DATA INPUTS
OUTPUT
UNDER TEST
PARAMETER
INPUT
UNDER TEST
Apply 4.5V
Apply GND
Apply 4.5V
Apply GND
OUTPUT
UNDER TEST
t
PLH
, t
PHL
A
i
B
i
None
Remaining A and B
Cn
F
i
t
PLH
, t
PHL
B
i
A
i
None
Remaining A and B
Cn
F
i
t
PLH
, t
PHL
A
i
B
i
None
None
Remaining A, B, Cn
P
t
PLH
, t
PHL
B
i
A
i
None
None
Remaining A, B, Cn
P
t
PLH
, t
PHL
A
i
None
B
i
Remaining B
Remaining A, Cn
G
t
PLH
, t
PHL
B
i
None
A
i
Remaining B
Remaining A, Cn
G
t
PLH
, t
PHL
A
i
None
B
i
Remaining B
Remaining A, Cn
C
n+4
t
PLH
, t
PHL
B
i
None
A
i
Remaining B
Remaining A, Cn
C
n+4
t
PLH
, t
PHL
Cn
None
None
All A
All B
Any F or C
n+4
Table 2. Diff Mode Test
Function Inputs: S1 = S2 = 4.5V,
S0 = S3 = M = 0V
PARAMETER
INPUT
UNDER TEST
OTHER INPUT, SAME BIT
OTHER DATA INPUTS
OUTPUT
UNDER TEST
PARAMETER
INPUT
UNDER TEST
Apply 4.5V
Apply GND
Apply 4.5V
Apply GND
OUTPUT
UNDER TEST
t
PLH
, t
PHL
A
i
None
B
i
Remaining A
Remaining B, Cn
F
i
t
PLH
, t
PHL
B
i
A
i
None
Remaining A
Remaining B, Cn
F
i
t
PLH
, t
PHL
A
i
None
B
i
None
Remaining A, B, Cn
P
t
PLH
, t
PHL
B
i
A
i
None
None
Remaining A, B, Cn
P
t
PLH
, t
PHL
A
i
B
i
None
None
Remaining A, B, Cn
G
t
PLH
, t
PHL
B
i
None
A
i
None
Remaining A, B, Cn
G
t
PLH
, t
PHL
A
i
None
B
i
Remaining A
Remaining B, Cn
A=B
t
PLH
, t
PHL
B
i
A
i
None
Remaining A
Remaining B, Cn
A=B
t
PLH
, t
PHL
A
i
B
i
None
None
Remaining A, B, Cn
C
n+4
t
PLH
, t
PHL
B
i
None
A
i
None
Remaining A, B, Cn
C
n+4
t
PLH
, t
PHL
Cn
None
None
All A and B
None
Any F or C
n+4
Table 3. Logic Mode Test
Function Inputs: S1 = S2 = 4.5V,
S0 = S3 = 0V
PARAMETER
INPUT
UNDER TEST
OTHER INPUT, SAME BIT
OTHER DATA INPUTS
OUTPUT
UNDER TEST
PARAMETER
INPUT
UNDER TEST
Apply 4.5V
Apply GND
Apply 4.5V
Apply GND
OUTPUT
UNDER TEST
t
PLH
, t
PHL
A
i
B
i
None
None
Remaining A, B, Cn
F
i
t
PLH
, t
PHL
B
i
A
i
None
None
Remaining A, B, Cn
F
i
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
V
CC
Supply voltage
0.5 to +7.0
V
V
IN
Input voltage
0.5 to +7.0
V
I
IN
Input current
30 to +5
mA
V
OUT
Voltage applied to output in High output state
0.5 to V
CC
V
I
OUT
Current applied to output in Low output state
40
mA
T
amb
Operating free-air temperature range
0 to +70
C
T
stg
Storage temperature range
65 to +150
C
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