Philips Semiconductors

Product specification

74F194

4-bit bidirectional universal shift register

April 4, 1989

8530354 96224

FEATURES

Shift right and shift left capability

Synchronous parallel and serial data transfer

Easily expanded for both serial and parallel operation

Asynchronous Master Reset

Hold (do nothing) mode

DESCRIPTION

The functional characteristics of the 74F194 4-Bit Bidirectional Shift
Register are indicated in the Logic Diagram and Function Table. The
register is fully synchronous, with all operations taking place in less
than 9ns (typical) for 74F, making the device especially useful for
implementing very high speed CPUs, or for memory buffer registers.

The 74F194 design has special logic features which increase the
range of application. The synchronous operation of the device is
determined by two Mode Select inputs, S0 and S1. As shown in the
Mode Select-Function Table, data can be entered and shifted from
left to right (shift right, Q0

Q1, etc.), or right to left (shift left,

Q2, etc.), or parallel data can be entered, loading all 4 bits of

the register simultaneously. When both S0 and S1 are Low, existing
data is retained in a hold (do nothing) mode. The first and last
stages provide D-type Serial Data inputs (D

, D

) to allow

multistage shift right or shift left data transfers without interfering
with parallel load operation. Mode Select and data inputs on the
74F194 are edge-triggered, responding only to the Low-to-High
transition of the Clock (CP). Therefore, the only timing restriction is
that the Mode Select and selected data inputs must be stable one
setup time prior to the Low-to-High transition of the clock pulse.
Signals on the Mode Select, Parallel Data (D0D3) and Serial Data
(D

, D

) can change when the clock is in either state, provided

only the recommended setup and hold times, with respect to the
clock rising edge, are observed. The four Parallel Data inputs
(D0D3) are D-type inputs. Data appearing on (D0D3) inputs when
S0 and S1 are High is transferred to the Q0Q3 outputs
respectively, following the next Low-to-High transition of the clock.
When Low, the asynchronous Master Reset (MR) overrides all other
input conditions and forces the Q outputs Low.

PIN CONFIGURATION

GND

SF00167

TYPE

TYPICAL f

MAX

TYPICAL

SUPPLY CURRENT

(TOTAL)

74F194

150MHz

33mA

ORDERING INFORMATION

DESCRIPTION

COMMERCIAL RANGE

= 5V

10%,

amb

= 0

C to +70

PKG DWG #

16-pin plastic DIP

N74F194N

SOT38-4

16-pin plastic SO

N74F194D

SOT109-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74F (U.L.) HIGH/LOW

LOAD VALUE HIGH/LOW

D0D3

Parallel data inputs

1.0/1.0

A/0.6mA

Serial data input (Shift Right)

1.0/1.0

A/0.6mA

Serial data input (Shift Left)

1.0/1.0

A/0.6mA

S0, S1

Mode Select inputs

1.0/1.0

A/0.6mA

Clock Pulse input (active rising edge)

1.0/1.0

A/0.6mA

Asynchronous master Reset input (Active Low)

1.0/1.0

A/0.6mA

Q0Q3

Data outputs

50/33

1.0mA/20mA

NOTE: One (1.0) FAST unit load is defined as: 20

A in the High state and 0.6mA in the Low state.

Philips Semiconductors

Product specification

74F194

4-bit bidirectional universal shift register

April 4, 1989

FUNCTION TABLE

INPUTS

OUTPUTS

OPERATING MODES

Reset (clear)

Hold (do nothing)

Shift left

Shift right

Parallel load

H = High voltage level
h = High voltage level one setup time prior to Low-to-High clock transition
L = Low voltage level
l = Low voltage level one setup time prior to Low-to-High clock transition
X = Don't care

= Low-to-High clock transition

dn(qn) = Lower case letters indicate the state of the referenced input (or output) one setup time prior to the Low-to-High clock transition.

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)

SYMBOL

PARAMETER

RATING

UNIT

Supply voltage

0.5 to +7.0

Input voltage

0.5 to +7.0

Input current

30 to +5

OUT

Voltage applied to output in High output state

0.5 to V

OUT

Current applied to output in Low output state

amb

Operating free-air temperature range

0 to +70

stg

Storage temperature range

65 to +150

RECOMMENDED OPERATING CONDITIONS

SYMBOL

PARAMETER

LIMITS

UNIT

SYMBOL

PARAMETER

MIN

NOM

MAX

UNIT

Supply voltage

4.5

5.0

5.5

High-level input voltage

2.0

Low-level input voltage

0.8

Input clamp current

High-level output current

Low-level output current

amb

Operating free-air temperature range

+70

Philips Semiconductors

Product specification

74F194

4-bit bidirectional universal shift register

April 4, 1989

DC ELECTRICAL CHARACTERISTICS

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNIT

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

High level output voltage

= MIN, V

= MAX

10%V

2.5

High-level output voltage

= MIN, I

= MAX

5%V

2.7

3.4

Low level output voltage

= MIN, V

= MAX

10%V

0.30

0.50

Low-level output voltage

= MIN, I

= MAX

5%V

0.30

0.50

Input clamp voltage

= MIN, I

= I

0.73

1.2

Input current at maximum input voltage

= MAX, V

= 7.0V

100

High-level input current

= MAX, V

= 2.7V

Low-level input current

= MAX, V

= 0.5V

0.6

Short-circuit output current

= MAX

150

Supply current (total)

= MAX

NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V

= 5V, T

amb

= 25

3. Output High state will change to Low stat if an external voltage of less than 0.0V is applied.
4. Not more than one output should be shorted at a time. For testing I

, the use of high-speed test apparatus and/or sample-and-hold

techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I

tests should be performed last.

5. With all outputs open, D

inputs grounded and a 4.5V applied to S0, S1, MR and the serial inputs, I

is tested with a momentary ground,

then 4.5V applied to CP.

AC ELECTRICAL CHARACTERISTICS

LIMITS

SYMBOL

PARAMETER

TEST

CONDITION

= +5.0V

amb

= +25

= 50pF, R

= 500

= +5.0V

10%

amb

= 0

C to +70

= 50pF, R

= 500

UNIT

MIN

TYP

MAX

MIN

MAX

MAX

Maximum clock frequency

Waveform 1

105

150

MHz

PLH

PHL

Propagation delay
CP to Qn

Waveform 1

3.5
3.5

5.2
5.5

7.0
7.0

3.5
3.5

8.0
8.0

PHL

Propagation delay
MR to Qn

Waveform 2

4.5

8.6

12.0

4.5

14.0

AC SETUP REQUIREMENTS

LIMITS

SYMBOL

PARAMETER

TEST

CONDITION

= +5.0V

amb

= +25

= 50pF, R

= 500

= +5.0V

10%

amb

= 0

C to +70

= 50pF, R

= 500

UNIT

MIN

TYP

MAX

MIN

MAX

(H)

(L)

Setup time, High or Low
Dn, D

, D

to CP

Waveform 3

4.0
4.0

(H)

(L)

Hold time, High or Low
Dn, D

, D

to CP

Waveform 3

0
0

1.0
1.0

(H)

(L)

Setup time, High or Low
Sn to CP

Waveform 3

8.0
8.0

9.0
8.0

(H)

(L)

Hold time, High or Low
Sn to CP

Waveform 3

0
0

(H)

CP Pulse width, High

Waveform 1

5.0

5.5

(L)

MR Pulse width, Low

Waveform 2

5.0

REC

Recovery time, MR to CP

Waveform 2

7.0

8.0

Philips Semiconductors

Product specification

74F194

4-bit bidirectional universal shift register

April 4, 1989

AC WAVEFORMS

For all waveforms, V

= 1.5V.

The shaded areas indicate when the input is permitted to change for predictable output performance.

SF00171

tw(H)

tPHL

tPLH

1/fMAX

Waveform 1.

Propagation Delay, Clock Input to Output,

Clock Pulse Width, and Maximum Clock Frequency

SF00158

(L)

PHL

REC

Waveform 2.

Master Reset Pulse Width, Master Reset to

Output Delay, and Master Reset to Clock Recovery Time

th(H)

ts(H)

SF00172

th(L)

ts(L)

Dn, D

S0, S1

Waveform 3.

Setup and Hold Times

TIMING DIAGRAM

Typical Clear, Load, Shift-Right, Shift-Left and Inhibit Sequence

SERIAL

DATA

INPUTS

PARALLEL

DATA

INPUTS

OUTPUTS

INHIBIT

CLEAR

SF00173

SHIFT LEFT

CLEAR

LOAD

SHIFT RIGHT

Philips Semiconductors

Product specification

74F194

4-bit bidirectional universal shift register

April 4, 1989

TEST CIRCUIT AND WAVEFORMS

90%

10%

90%

10%

90%

10%

90%

10%

NEGATIVE
PULSE

POSITIVE
PULSE

AMP (V)

tTHL (tf

)

INPUT PULSE REQUIREMENTS

rep. rate

TLH

THL

1MHz

500ns

2.5ns

Input Pulse Definition

VCC

family

74F

D.U.T.

PULSE

GENERATOR

VIN

VOUT

Test Circuit for Totem-Pole Outputs

DEFINITIONS:
R

= Load resistor;

see AC ELECTRICAL CHARACTERISTICS for value.

= Load capacitance includes jig and probe capacitance;

see AC ELECTRICAL CHARACTERISTICS for value.

= Termination resistance should be equal to Z

OUT

pulse generators.

tTHL (tf

)

tTLH (tr

)

tTLH (tr

)

AMP (V)

amplitude

3.0V

1.5V

SF00006

Philips Semiconductors

Product specification

74F194

4-bit bidirectional universal shift register

yyyy mmm dd

Definitions

Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381

print code

Date of release: 10-98

Document order number:

9397-750-05095

Philips

Semiconductors

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

[1]

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

Data sheet status

[1]

Please consult the most recently issued datasheet before initiating or completing a design.

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