Philips
Semiconductors
74F219A
64-bit TTL bipolar RAM, non-inverting
(3-State)
Product specification
1996 Jan 05
INTEGRATED CIRCUITS
IC15 Data Handbook
Philips Semiconductors
Product specification
74F219A
64-bit TTL bipolar RAM, non-inverting (3-State)
2
1996 Jan 05
853-1308 16196
FEATURES
High speed performance
Replaces 74F219
Address access time: 8ns max vs 28ns for 74F219
Power dissipation: 4.3mW/bit typ
Schottky clamp TTL
One chip enable
NonInverting outputs (for inverting outputs see 74F189A)
3state outputs
74F219A in 150 mil wide SO is preferred options for new designs
C3F219A in 300 mil wide SOL replaces 74F219 in existing
designs
DESCRIPTION
The 74F219A is a high speed, 64bit RAM organized as a 16word
by 4bit array. Address inputs are buffered to minimize loading and
are fully decoded on chip. The outputs are in high impedance state
whenever the chip enable (CE) is high. The outputs are active only
in the READ mode (WE = high) and the output data is the
complement of the stored data.
APPLICATIONS
Scratch pad memory
Buffer memory
Push down stacks
Control store
PIN CONFIGURATION
16
15
14
13
12
11
10
7
6
5
4
3
2
1
D0
D3
D2
Q2
Q3
A1
A2
A0
CE
Q1
WE
D1
GND
9
8
Q0
V
CC
A3
SF00307
TYPE
TYPICAL ACCESS TIME
TYPICAL SUPPLY CURRENT(TOTAL)
74F219A
5.0ns
55mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
10%, T
amb
= 0
C to +70
C
DRAWING NUMBER
16-pin plastic Dual In-line Package
N74F219AN
SOT38-4
16-pin plastic Small Outline (150mil)
N74F219AD
SOT109-1
16-pin plastic Small Outline Large (300mil)
C3F219AD
SOT1621
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
D0 D3
Data inputs
1.0/1.0
20
A
/
0.6mA
A0 A3
Address inputs
1.0/1.0
20
A
/
0.6mA
CE
Chip enable input (active low)
1.0/2.0
20
A/1.2mA
WE
Write enable input (active low)
1.0/2.0
20
A/1.2mA
Q0 Q3
Data outputs
150/40
3mA/24mA
NOTE: One (1.0) FAST unit load is defined as: 20
A in the high state and 0.6mA in the low state.
Philips Semiconductors
Product specification
74F219A
64-bit TTL bipolar RAM, non-inverting (3-State)
1996 Jan 05
3
LOGIC SYMBOL
D0
D2 D3
D1
Q0 Q1 Q2 Q3
5
7
9
11
6
10 12
V
CC
= pin 16
GND = pin 8
4
A0
A1
A2
A3
CE
WE
1
15
14
13
2
3
SF00308
IEC/IEEE SYMBOL
1
15
14
13
12
11
RAM 16X4
10
9
6
7
4
5
2
3
A,2D
A
G1
1 EN [READ]
1 C2 [WRITE]
0
1
A
0
15
SF00301
LOGIC DIAGRAM
V
CC
= Pin 16
GND = Pin 8
Decoder
Drivers
A0
A1
A2
A3
Address
Decoder
16word x 4bit
memory cell
array
Data buffers
Output buffers
Q0 Q1 Q2 Q3
D0 D1 D2 D3
WE
CE
1
15
14
13
3
2
5
7
9
11
4
6
10 12
SF00309
FUNCTION TABLE
INPUTS
OUTPUT
OPERATING
CE
WE
Dn
Q
n
MODE
L
H
X
Stored data
Read
L
L
L
High impedance
Write "0"
L
L
H
High impedance
Write "1"
H
X
X
High impedance
Disable input
NOTES:
H = High voltage level
L = Low voltage level
X = Don't care
Philips Semiconductors
Product specification
74F219A
64-bit TTL bipolar RAM, non-inverting (3-State)
1996 Jan 05
4
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
V
CC
Supply voltage
0.5 to +7.0
V
V
IN
Input voltage
0.5 to +7.0
V
I
IN
Input current
30 to +5
mA
V
OUT
Voltage applied to output in high output state
0.5 to V
CC
V
I
OUT
Current applied to output in low output state
48
mA
T
amb
Operating free-air temperature range
0 to +70
C
T
stg
Storage temperature range
65 to +150
C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN
NOM
MAX
UNIT
V
CC
Supply voltage
4.5
5.0
5.5
V
V
IH
Highlevel input voltage
2.0
V
V
IL
Lowlevel input voltage
0.8
V
I
Ik
Input clamp current
18
mA
I
OH
Highlevel output current
3
mA
I
OL
Lowlevel output current
24
mA
T
amb
Operating free-air temperature range
0
+70
C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS
1
LIMITS
UNIT
MIN
TYP
2
MAX
V
OH
High-level output voltage
V
CC
= MIN, V
IL
= MAX
10%V
CC
2.4
V
V
IH
= MIN, I
OH
= MAX
5%V
CC
2.7
3.4
V
V
OL
Low-level output voltage
V
CC
= MIN, V
IL
= MAX
10%V
CC
0.35
0.50
V
V
IH
= MIN, I
OL
= MAX
5%V
CC
0.35
0.50
V
V
IK
Input clamp voltage
V
CC
= MIN, I
I
= I
IK
-0.73
-1.2
V
I
I
Input current at maximum input voltage
V
CC
= MAX, V
I
= 7.0V
100
A
I
IH
Highlevel input current
V
CC
= MAX, V
I
= 2.7V
20
A
I
IL
Lowlevel input current
others
V
CC
= MAX, V
I
= 0.5V
-0.6
mA
CE, WE
-1.2
mA
I
OZH
Offset output current,
highlevel voltage applied
V
CC
= MAX, V
I
= 2.7V
50
A
I
OZL
Offset output current,
lowlevel voltage applied
V
CC
= MAX, V
I
= 0.5V
50
A
I
OS
Short-circuit output current
3
V
CC
= MAX
-60
-150
mA
I
CC
Supply current (total)
V
CC
= MAX, CE = WE = GND
55
80
mA
C
IN
Input capacitance
V
CC
= 5V, V
IN
= 2.0V
4
pF
C
OUT
Output capacitance
V
CC
= 5V, V
OUT
= 2.0V
7
pF
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25
C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
Philips Semiconductors
Product specification
74F219A
64-bit TTL bipolar RAM, non-inverting (3-State)
1996 Jan 05
5
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
T
amb
= +25
C
V
CC
= +5.0V
C
L
= 50pF, R
L
= 500
T
amb
= 0
C to +70
C
V
CC
= +5.0V
10%
C
L
= 50pF, R
L
= 500
UNIT
MIN
TYP
MAX
MIN
MAX
t
PLH
t
PHL
Access time
Propagation delay
An to Qn
Waveform 1
2.5
2.0
5.0
4.5
8.0
8.0
2.5
2.0
8.0
8.0
ns
t
PZH
t
PZL
Enable time
CE to Qn
Waveform 2
1.5
2.5
3.0
4.0
6.0
7.0
1.5
2.0
7.0
7.5
ns
t
PHZ
t
PLZ
Disable time
CE to Qn
Waveform 3
2.5
1.5
4.5
3.0
7.0
5.5
2.0
1.0
8.0
6.0
ns
t
PZH
t
PZL
Write recovery time
Enable time
WE to Qn
Waveform 4
2.0
3.0
3.5
4.5
6.5
7.5
1.5
2.5
7.0
8.0
ns
t
PHZ
t
PLZ
Disable time
WE to Qn
Waveform 4
3.0
1.5
5.0
3.5
8.0
6.0
2.5
1.5
9.0
7.0
ns
AC SETUP REQUIREMENT
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
T
amb
= +25
C
V
CC
= +5.0V
C
L
= 50pF, R
L
= 500
T
amb
= 0
C to +70
C
V
CC
= +5.0V
10%
C
L
= 50pF, R
L
= 500
UNIT
MIN
TYP
MAX
MIN
MAX
t
su
(H)
t
su
(L)
Setup time, high or low
An to WE
Waveform 4
4.5
4.5
5.0
5.0
ns
t
h
(H)
t
h
(L)
Hold time, high or low
An to WE
Waveform 4
0
0
0
0
ns
t
su
(H)
t
su
(L)
Setup time, high or low
Dn to WE
Waveform 4
8.0
7.5
9.0
8.5
ns
t
h
(H)
t
h
(L)
Hold time, high or low
Dn to WE
Waveform 4
0
0
0
0
ns
t
su
(L)
Setup time, low
CE (falling edge) to WE (falling edge)
Waveform 4
0
0
ns
t
h
(L)
Hold time, low
WE (falling edge) to WE (rising edge)
Waveform 4
6.5
7.5
ns
t
w
(L)
Pulse width, low
WE
Waveform 4
7.0
8.0
ns
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