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Электронный компонент: N74F2373N

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Philips
Semiconductors
74F2373
Octal transparent latch with 30
equivalent output termination (3-State)
Product specification
Supersedes data of 1995 Jun 20
IC15 Data Handbook
1999 Feb 01
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
74F2373
Octal transparent latch with 30
equivalent output
termination (3-State)
2
1999 Feb 01
853-2140 20747
FEATURES
8-bit transparent latch
30 Ohm output termination for driving DRAM
3-State outputs glitch free during power-up and power-down
Common 3-State output register
Independent register and 3-State buffer operation
DESCRIPTION
The 74F2373 is an octal transparent latch coupled to eight 3-State
output devices. The two sections of the device are controlled
independently by enable (E) and output enable (OE) control gates.
The 30 Ohm series termination on the outputs reduces
over/undershoot, making them ideal for driving DRAM
The data on the D inputs is transferred to the latch outputs when the
enable (E) input is high. The latch remains transparent to the data
input while E is high, and stores the data that is present one setup
time before the high-to-low enable transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active low output enable (OE) controls all eight 3-State buffers
independent of the latch operation. When OE is low, latched or
transparent data appears at the output.
When OE is high, the outputs are in high impedance "off " state,
which means they will neither drive nor load the bus.
TYPE
TYPICAL
PROPAGATION
DELAY
TYPICAL SUPPLY
CURRENT
(TOTAL)
74F2373
4.5ns
35mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
DRAWING NUMBER
V
CC
= 5V
10%, T
amb
= 0
C to +70
C
20-pin plastic DIP
N74F2373N
SOT146-1
20-pin plastic SOL
N74F2373D
SOT163-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
D0 - D7
Data inputs
1.0/1.0
20
A
/
0.6mA
E
Enable input (active high)
1.0/1.0
20
A/0.6mA
OE
Output enable inputs (active low)
1.0/1.0
20
A/0.6mA
Q0 - Q7
3-State outputs
150/40
3.0mA/3.0mA
NOTE: One (1.0) FAST unit load is defined as: 20
A in the high state and 0.6mA in the low state.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
V
CC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
E
SF00250
LOGIC SYMBOL
E
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
D0 D1 D2 D3 D4 D5 D6 D7
3
4
7
8
13
14
17
18
2
5
6
9
12
15
16
19
V
CC
= Pin 20
GND = Pin 10
11
1
OE
SF00251
Philips Semiconductors
Product specification
74F2373
Octal transparent latch with 30
equivalent output
termination (3-State)
1999 Feb 01
3
IEC/IEEE SYMBOL
1
EN2
2D
EN1
1
11
3
4
7
8
13
14
17
18
2
5
6
12
9
15
16
19
SF00252
LOGIC DIAGRAM
VCC
= Pin 20
D0
D
E
Q
Q0
3
2
D1
D
E
Q
Q1
4
5
D2
D
E
Q
Q2
7
6
D3
D
E
Q
Q3
8
9
D4
D
E
Q
Q4
13
12
D5
D
E
Q
Q5
14
15
D6
D
E
Q
Q6
17
16
D7
D
E
Q
Q7
18
19
11
1
OE
E
GND = Pin 10
SF00256
FUNCTION TABLE
INPUTS
INTERNAL
OUTPUTS
OPERATING MODE
OE
E
Dn
REGISTER
Q0 - Q7
OPERATING MODE
L
H
L
L
L
Enable and read register
L
H
H
H
H
Enable and read register
L
l
L
L
Latch and read register
L
h
H
H
Latch and read register
L
L
X
NC
NC
Hold
H
L
X
NC
Z
Disable outputs
H
H
Dn
Dn
Z
Disable outputs
NOTES:
H =
High-voltage level
h
=
High state must be present one setup time before the high-to-low enable transition
L
=
Low-voltage level
l
=
Low state must be present one setup time before the high-to-low enable transition
NC=
No change
X =
Don't care
Z =
High impedance "off " state
=
High-to-low enable transition
Philips Semiconductors
Product specification
74F2373
Octal transparent latch with 30
equivalent output
termination (3-State)
1999 Feb 01
4
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
V
CC
Supply voltage
0.5 to +7.0
V
V
IN
Input voltage
0.5 to +7.0
V
I
IN
Input current
30 to +5
mA
V
OUT
Voltage applied to output in high output state
-0.5 to V
CC
V
I
OUT
Current applied to output in low output state
24
mA
T
amb
Operating free air temperature range
0 to +70
C
T
stg
Storage temperature range
65 to +150
C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN
NOM
MAX
UNIT
V
CC
Supply voltage
4.5
5.0
5.5
V
V
IH
High-level input voltage
2.0
V
V
IL
Low-level input voltage
0.8
V
I
Ik
Input clamp current
18
mA
I
OH
High-level output current
3*
mA
I
OL
Low-level output current
5*
mA
T
amb
Operating free air temperature range
0
+70
C
*
12mA with reduced noise margin
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST
LIMITS
UNIT
SYMBOL
PARAMETER
CONDITIONS
1
MIN
TYP
2
MAX
UNIT
V
CC
= MIN, V
IL
= MAX,
10%V
CC
2.4
V
V
O
High level output voltage
V
IH
= MIN, I
OH
= 3mA
5%V
CC
2.7
3.4
V
V
OH
High-level output voltage
V
CC
= MIN, V
IL
= MAX,
10%V
CC
2.0
V
V
IH
= MIN, I
OH
= 12mA
5%V
CC
2.0
V
V
CC
= MIN, V
IL
= MAX,
10%V
CC
0.42
0.50
V
V
OL
Low-level output voltage
V
IH
= MIN, I
OL
= 5mA
5%V
CC
0.42
0.50
V
V
OL
Low-level out ut voltage
V
CC
= MIN, V
IL
= MAX,
10%V
CC
0.67
V
V
IH
= MIN, I
OL
= 12mA
5%V
CC
0.67
V
V
IK
Input clamp voltage
V
CC
= MIN, I
I
= I
IK
-0.73
-1.2
V
I
I
Input current at maximum input voltage
V
CC
= MAX, V
I
= 7.0V
100
A
I
IH
High-level input current
V
CC
= MAX, V
I
= 2.7V
20
A
I
IL
Low-level input current
V
CC
= MAX, V
I
= 0.5V
-0.6
mA
I
OZH
Off-state output current, high-level voltage applied
V
CC
= MAX, V
O
= 2.7V
50
A
I
OZL
Off-state output current, low-level voltage applied
V
CC
= MAX, V
O
= 0.5V
-50
A
I
OS
Short-circuit output current
3
V
CC
= MAX
-60
-150
mA
I
CC
Supply current (total)
V
CC
= MAX
35
60
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25
C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
Philips Semiconductors
Product specification
74F2373
Octal transparent latch with 30
equivalent output
termination (3-State)
1999 Feb 01
5
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
amb
= +25
C
T
amb
= 0
C to +70
C
SYMBOL
PARAMETER
TEST
V
CC
= +5.0V
V
CC
= +5.0V
10%
UNIT
CONDITION
C
L
= 50pF, R
L
= 500
C
L
= 50pF, R
L
= 500
MIN
TYP
MAX
MIN
MAX
t
PLH
t
PHL
Propagation delay
Dn to Qn
Waveform 2
3.0
2.0
5.3
3.7
8.0
6.0
3.0
2.0
9.0
7.0
ns
t
PLH
t
PHL
Propagation delay
E to Qn
Waveform 1
5.0
3.0
9.0
4.0
12.0
8.0
5.0
3.0
12.5
8.5
ns
t
PZH
t
PZL
Output enable time
to high or low level
Waveform 4
Waveform 5
2.0
2.0
5.0
5.6
12.0
8.0
2.0
2.0
12.5
8.5
ns
t
PHZ
t
PLZ
Output disable time
from high or low level
Waveform 4
Waveform 5
2.0
2.0
4.5
3.8
6.5
5.5
2.0
2.0
7.5
6.5
ns
AC SETUP REQUIREMENTS
LIMITS
T
amb
= +25
C
T
amb
= 0
C to +70
C
SYMBOL
PARAMETER
TEST
V
CC
= +5.0V
V
CC
= +5.0V
10%
UNIT
CONDITION
C
L
= 50pF, R
L
= 500
C
L
= 50pF, R
L
= 500
MIN
TYP
MAX
MIN
MAX
t
su
(H)
t
su
(L)
Setup time, high or low level
Dn to E
Waveform 3
0
1.0
0
1.0
ns
t
h
(H
)
t
h (
L
)
Hold time, high or low level
Dn to E
Waveform 3
3.0
3.0
3.0
3.0
ns
t
w
(H)
E Pulse width, high
Waveform 1
3.5
4.0
ns
AC WAVEFORMS
For all waveforms, V
M
= 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
tPHL
E
VM
VM
VM
tw(H)
VM
VM
Qn
tPLH
SF00259
Waveform 1. Propagation delay for enable to output
and enable pulse width
Dn
VM
VM
VM
VM
tPHL
tPLH
Qn
SF00260
Waveform 2. Propagation delay for data to output
VM
VM
VM
VM
VM
VM
tsu(L)
th(L)
tsu(H)
th(H)
E
Dn
SF00261
Waveform 3. Data setup time and hold times
Qn, Qn
VM
VM
VM
tPHZ
tPZH
OEn
VOH -0.3V
0V
SF00263
Waveform 4. 3-State output enable time to high level
and output disable time from high level