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Электронный компонент: N74F256D

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Philips
Semiconductors
74F256
Dual addressable latch
Product specification
IC15 Data Handbook
1988 Nov 29
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
74F256
Dual addressable latch
2
1988 Nov 29
8530359 95207
FEATURES
Combines dual demultiplexer and 8-bit latch
Serial-to-parallel capability
Output from each storage bit available
Random (addressable) data entry
Easily expandable
Common reset input
Useful as dual 1-of-4 active High decoder
DESCRIPTION
The 74F256 dual addressable latch has four distinct modes of
operation which are selectable by controlling the Master Reset (MR)
and Enable (E) inputs (see Function Table). In the addressable latch
mode, data at the Data inputs is written into the addressed latches.
The addressed latches will follow the Data input with all
unaddressed latches remaining in their previous states. In the
memory mode, all latches remain in their previous states and are
unaffected by the Data or Address inputs. To eliminate the possibility
of entering erroneous data in the latches, the enable should be held
High (inactive) while the address lines are changing. In the dual
1-of-4 decoding or demultiplexing mode (MR=E=Low), addressed
outputs will follow the level of the Data inputs, with all other outputs
Low. In the Master Reset mode, all outputs are Low and unaffected
by the Address and Data inputs.
PIN CONFIGURATION
16
15
14
13
12
11
10
7
6
5
4
3
2
1
9
8
VCC
A0
A1
Da
Q0a
Q1a
Q2a
Q3a
GND
MR
E
Db
Q3b
Q2b
Q1b
Q0b
SF00805
TYPE
TYPICAL
PROPAGATION
DELAY
TYPICAL SUPPLY
CURRENT (TOTAL)
74F256
7.0ns
28mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
10%,
T
amb
= 0
C to +70
C
PKG DWG #
16-pin plastic DIP
N74F256N
SOT38-4
16-pin plastic SO
N74F256D
SOT109-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
Da, Db
Port A, port B inputs
1.0/1.0
20
A/0.6mA
A0, A1
Address inputs
1.0/1.0
20
A/0.6mA
E
Enable (active Low)
1.0/1.0
20
A/0.6mA
MR
Master Reset inputs (active Low)
1.0/1.0
20
A/0.6mA
Q0a Q3a
Port A outputs
50/33
1.0mA/20mA
Q0b Q3b
Port B outputs
50/33
1.0mA/20mA
NOTE:
One (1.0) FAST unit load is defined as: 20
A in the High state and 0.6mA in the Low state.
Philips Semiconductors
Product specification
74F256
Dual addressable latch
1988 Nov 29
3
LOGIC SYMBOL
VCC = Pin 16
GND = Pin 8
E
A0
A1
MR
14
1
2
15
SF00806
Q0a Q1a Q2a Q3a
Q0b Q1b Q2b Q3b
4
5
6
7
9
10
11
12
3
13
Da
Db
IEC/IEEE SYMBOL
Z5
3
13
15
5, 7D
1
G4
C7
4R
SF00807
Z6
1
2
14
6, 8D
1
0
1
2
3
C8
4R
0
1
2
3
0
G
0
3
1
4
5
6
7
9
10
11
12
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING MODE
MR
E
D
A0
A1
Q0
Q1
Q2
Q3
OPERATING MODE
L
H
X
X
X
L
L
L
L
Master Reset
L
L
d
L
L
Q=d
L
L
L
Demultiplex (active-High decoder when D=H)
L
L
d
H
L
L
Q=d
L
L
L
L
d
L
H
L
L
Q=d
L
L
L
d
H
H
L
L
L
Q=d
H
H
X
X
X
q0
q1
q2
q3
Store (do nothing)
H
L
d
L
L
Q=d
q1
q2
q3
H
L
d
H
L
q0
Q=d
q2
q3
Addressable Latch
H
L
d
L
H
q0
q1
Q=d
q3
Addressable Latch
H
L
d
H
H
q0
q1
q2
Q=d
H = High voltage level
L
= Low voltage level
X = Don't care
d
= High or Low data one setup time prior to the Low-to-High Enable transition
q
= Lower case letters indicate the state of the referenced output established during the last cycle in which it was addressed or cleared.
Philips Semiconductors
Product specification
74F256
Dual addressable latch
1988 Nov 29
4
LOGIC DIAGRAM
V
CC
= Pin 16
GND = Pin 8
SF00808
12
11
10
9
7
6
5
4
Q3b
Q2b
Q1b
Q0b
Q3a
Q2a
Q1a
Q0a
Db
Da
13
3
14
15
2
1
A0
A1
MR
E
Philips Semiconductors
Product specification
74F256
Dual addressable latch
1988 Nov 29
5
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
V
CC
Supply voltage
0.5 to +7.0
V
V
IN
Input voltage
0.5 to +7.0
V
I
IN
Input current
30 to +5
mA
V
OUT
Voltage applied to output in High output state
0.5 to V
CC
V
I
OUT
Current applied to output in Low output state
40
mA
T
amb
Operating free-air temperature range
0 to +70
C
T
stg
Storage temperature range
65 to +150
C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
MIN
NOM
MAX
V
CC
Supply voltage
4.5
5.0
5.5
V
V
IH
High-level input voltage
2.0
V
V
IL
Low-level input voltage
0.8
V
I
IK
Input clamp current
18
mA
I
OH
High-level output current
1
mA
I
OL
Low-level output current
20
mA
T
amb
Operating free-air temperature range
0
70
C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST
LIMITS
UNIT
CONDITIONS
1
MIN
TYP
2
MAX
V
OH
High-level output voltage
V
CC
= MIN, V
IL
= MAX,
10%V
CC
2.5
V
V
IH
= MIN, I
OL
= MAX
5%V
CC
2.7
3.4
V
V
OL
Low-level output voltage
V
CC
= MIN, V
IL
= MAX,
10%V
CC
0.35
0.50
V
V
IH
= MIN, I
OL
= MAX
5%V
CC
0.35
0.50
V
V
IK
Input clamp voltage
V
CC
= MIN, I
I
= I
IK
0.73
-1.2
V
I
I
Input current at maximum input voltage
V
CC
= MAX, V
I
= 7.0V
100
A
I
IH
High-level input current
V
CC
= MAX, V
I
= 2.7V
20
A
I
IL
Low-level input current
V
CC
= MAX, V
I
= 0.5V
0.6
mA
I
OS
Short-circuit output current
3
V
CC
= MAX
60
150
mA
I
CC
Supply current (total)
I
CCH
V
CC
= MAX
21
42
mA
I
CCL
33
60
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25
C.
3. To reduce the effect of external noise during test.
4. Not more than one output should be shorted at a time. For testing I
OS
, the use of High-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.