Document Outline
- FEATURES
- DESCRIPTION
- PIN CONFIGURATION
- ORDERING INFORMATION
- INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
- LOGIC SYMBOL
- IEC/IEEE SYMBOL (IEEE/IEC)
- FUNCTION TABLE
- LOGIC DIAGRAM
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS
- DC ELECTRICAL CHARACTERISTICS
- AC ELECTRICAL CHARACTERISTICS
- AC SETUP REQUIREMENTS
- AC WAVEFORMS
- TEST CIRCUIT AND WAVEFORMS
Philips Semiconductors
Product specification
74F604
Dual octal latch (3-State)
1
1990 Mar 01
8530029 98991
FEATURES
High impedance NPN base inputs for reduced loading
(20
A in High and Low states)
Stores 16-bitwide Data inputs, multiplexed 8-bit outputs
3-State outputs
Power supply current 75mA typical
DESCRIPTION
The 74F604 multiplexed latch is ideal for storing data from two input
buses, A or B, and providing data from either the A or B latches to
the output bus. Organized as 8-bit A and B latches, the latch outputs
are connected by pairs to eight 2-input multiplexers. A Select
(SELECT A/B) input determines whether the A or B latch contents
are multiplexed to the eight 3-State outputs. Data entered from the B
inputs are selected when SELECT A/B is Low; data from the A
inputs are selected when SELECT A/B is High. Data enters the
latches when the Latch Enable (LE) input is Low and is latched on
the LE rising edge. The outputs are enabled when LE is High and
disabled when LE is Low.
PIN CONFIGURATION
28
27
26
25
24
23
22
7
6
5
4
3
2
1
A2
V
CC
B5
A6
B6
A5
A4
B4
LE
SELECT A/B
B1
A0
B0
A1
SF01115
21
8
B2
A7
20
19
18
17
16
13
12
11
10
9
Q1
Q6
Q5
Q4
Q7
B7
Q2
A3
B3
Q3
15
14
GND
Q0
TYPE
TYPICAL
PROPAGATION
DELAY
TYPICAL SUPPLY CURRENT
(TOTAL)
74F604
7.5ns
75mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
10%, T
amb
= 0
C to +70
C
28-pin plastic DIP
N74F604N
28-pin plastic SOL
N74F604D
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
A0A7, B0B7
Data inputs
1.0/0.033
20
A/20
A
SELECT A/B
Select input
1.0/0.033
20
A/20
A
LE
Latch Enable input (active Low)
1.0/0.033
20
A/20
A
Q0Q7
Data outputs
150/40
3mA/24mA
NOTE:
One (1.0) FAST unit load is defined as: 20
A in the High state and 0.6mA in the Low state.
Philips Semiconductors
Product specification
74F604
Dual octal latch (3-State)
1990 Mar 01
2
LOGIC SYMBOL
2
1
LE
SELECT A/B
3
A0
A1
A2
A3
SF01116
VCC = Pin 28
GND = Pin 14
4
5
6
A4
A5
A6
7
A7
8
9
10
15
Q0
Q1
Q2 Q3
13
12
11
Q4 Q5
Q6
16
Q7
17
18
19
27
26 25 24
23 22 21 20
B0
B1
B2
B3
B4
B5
B6
B7
IEC/IEEE SYMBOL (IEEE/IEC)
SF01117
5
1D 2
G2
E1
2
1
25
24
23
26
21
20
22
1D 2
4
EN
19
1
18
17
16
11
12
13
15
10
27
9
8
6
7
3
FUNCTION TABLE
INPUTS
OUTPUTS
A0A7
B0B7
SELECT A/B
LE
Q0Q7
A data
B data
L
B data
A data
B data
H
B data
X
X
X
L
Z
X
X
L
H
B latched data
X
X
H
H
A latched data
H = High voltage level
L
= Low voltage level
X = Don't care
Z = High impedance "off" state
= Low-to-High clock transition
Philips Semiconductors
Product specification
74F604
Dual octal latch (3-State)
1990 Mar 01
3
LOGIC DIAGRAM
VCC = Pin 28
GND = Pin 14
SF01118
D
E
D
E
SELECT A/B
LE
A0
B0
2
1
3
4
D
E
D
E
A1
B1
5
6
D
E
D
E
A2
B2
7
8
D
E
D
E
A3
B3
9
10
D
E
D
E
A4
B4
27
26
D
E
D
E
A5
B5
25
24
D
E
D
E
A6
B6
23
22
D
E
D
E
A7
B7
21
20
15
13
12
11
16
17
18
19
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Philips Semiconductors
Product specification
74F604
Dual octal latch (3-State)
1990 Mar 01
4
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
V
CC
Supply voltage
0.5 to +7.0
V
V
IN
Input voltage
0.5 to +7.0
V
I
IN
Input current
30 to +5
mA
V
OUT
Voltage applied to output in High output state
0.5 to +V
CC
V
I
OUT
Current applied to output in Low output state
48
mA
T
amb
Operating free-air temperature range
0 to +70
C
T
stg
Storage temperature range
65 to +150
C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN
NOM
MAX
UNIT
V
CC
Supply voltage
4.5
5.0
5.5
V
V
IH
High-level input voltage
2.0
V
V
IL
Low-level input voltage
0.8
V
I
IK
Input clamp current
18
mA
I
OH
High-level output current
3
mA
I
OL
Low-level output current
24
mA
T
amb
Operating free-air temperature range
0
70
C
Philips Semiconductors
Product specification
74F604
Dual octal latch (3-State)
1990 Mar 01
5
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS
1
LIMITS
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
1
MIN
TYP
2
MAX
UNIT
V
OH
High-level output voltage
V
CC
= MIN, V
IL
= MAX,
10%V
CC
2.4
V
V
OH
High-level output voltage
V
CC
MIN, V
IL
MAX,
V
IH
= MIN, I
OH
= MAX
5%V
CC
2.7
3.4
V
V
OL
Low-level output voltage
V
CC
= MIN, V
IL
= MAX,
10%V
CC
0.35
0.50
V
V
OL
Low-level output voltage
V
CC
MIN, V
IL
MAX,
V
IH
= MIN, I
OL
= MAX
5%V
CC
0.35
0.50
V
V
IK
Input clamp voltage
V
CC
= MIN, I
I
= I
IK
0.73
1.2
V
I
I
Input current at maximum input
voltage
V
CC
= 0.0V, V
I
= 7.0V
100
A
I
IH
High-level input current
V
CC
= MAX, V
I
= 2.7V
20
A
I
IL
Low-level input current
V
CC
= MAX, V
I
= 0.5V
20
A
I
OZH
Off state output current,
High-level voltage applied
V
CC
= MAX, V
O
= 2.7V
50
A
I
OZL
Off state output current,
Low-level voltage applied
V
CC
= MAX, V
O
= 0.5V
50
A
I
OS
Short-circuit output current
3
V
CC
= MAX
60
150
mA
I
S
l
(
l)
I
CCH
V
MAX
An, Bn, SELECT A/B = 4.5V, LE =
60
82
mA
I
CC
Supply current (total)
I
CCL
V
CC
= MAX
An, Bn, SELECT A/B=GND, LE =
75
100
mA
I
CC
Supply current (total)
I
CCZ
V
CC
= MAX
An, Bn, SELECT A/B = GND,
LE = GND
75
100
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25
C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST
LIMITS
UNIT
SYMBOL
PARAMETER
TEST
CONDITION
V
CC
= +5V
T
amb
= +25
C
C
L
= 50pF, R
L
= 500
V
CC
= +5V
10%
T
amb
= 0
C to +70
C
C
L
= 50pF, R
L
= 500
UNIT
MIN
TYP
MAX
MIN
MAX
t
PLH
t
PHL
Propagation delay
SELECT A/B to Qn (B latch)
Waveform 1
5.0
6.0
7.0
8.5
9.0
10.5
4.5
5.5
10.0
11.5
ns
t
PLH
t
PHL
Propagation delay
SELECT A/B to Qn (A latch)
Waveform 2
6.0
4.0
8.0
6.5
10.0
8.5
5.5
3.5
11.5
9.0
ns
t
PZH
t
PZL
Output Enable time
to High or Low level
Waveform 4
Waveform 5
5.0
5.0
7.5
7.5
9.5
9.5
4.5
4.5
10.5
11.0
ns
t
PHZ
t
PLZ
Output Disable time
from High or Low level
Waveform 4
Waveform 5
5.0
5.0
7.0
7.0
9.5
9.5
4.5
4.5
11.0
11.0
ns
Philips Semiconductors
Product specification
74F604
Dual octal latch (3-State)
1990 Mar 01
6
AC SETUP REQUIREMENTS
SYMBOL
PARAMETER
TEST
LIMITS
UNIT
SYMBOL
PARAMETER
TEST
CONDITION
V
CC
= +5V
T
amb
= +25
C
C
L
= 50pF, R
L
= 500
V
CC
= +5V
10%
T
amb
= 0
C to +70
C
C
L
= 50pF, R
L
= 500
UNIT
MIN
TYP
MAX
MIN
MAX
t
s
(H)
t
s
(L)
Setup time, High or Low
An, Bn to LE
Waveform 3
1.0
2.0
2.0
3.0
ns
t
h
(H)
t
h
(L)
Hold time, High or Low
An, Bn to LE
Waveform 3
0
1.0
0
1.5
ns
t
W
(L)
LE Pulse width, Low
Waveform 3
5.0
6.0
ns
AC WAVEFORMS
For all waveforms, V
M
= 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VM
VM
tPLH
tPHL
SELECT A/B
Qn
VM
SF01119
VM
Waveform 1. Propagation Delay, SELECT A/B To Output
(B latched data=Low. LE=H)
VM
VM
tPLH
tPHL
SELECT A/B
Qn
VM
SF01120
VM
Waveform 2. Propagation Delay, SELECT A/B to Output
(A latched data=Low. LE=H)
SF01121
V
M
V
M
V
M
V
M
V
M
An, Bn
LE
t
s
(H)
t
s
(L)
t
h
(L)
t
h
(H)
V
M
V
M
t
w
(L)
Waveform 3. Data Setup and Hold Times,
Latch Enable Pulse Width
V
M
V
M
V
M
t
PHZ
t
PZH
LE
Qn
V
OH
-0.3V
0V
SF01122
Waveform 4. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
V
M
V
M
V
M
t
PLZ
t
PZL
LE
Qn
V
OL
+0.3V
SF01123
Waveform 5. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
Philips Semiconductors
Product specification
74F604
Dual octal latch (3-State)
1990 Mar 01
7
TEST CIRCUIT AND WAVEFORMS
tw
90%
VM
10%
90%
VM
10%
90%
VM
10%
90%
VM
10%
NEGATIVE
PULSE
POSITIVE
PULSE
tw
AMP (V)
0V
0V
tTHL (tf
)
INPUT PULSE REQUIREMENTS
rep. rate
t
w
t
TLH
t
THL
1MHz
500ns
2.5ns
2.5ns
Input Pulse Definition
VCC
family
74F
D.U.T.
PULSE
GENERATOR
RL
CL
RT
VIN
VOUT
Test Circuit for 3-State Outputs
DEFINITIONS:
R
L
= Load resistor;
see AC electrical characteristics for value.
C
L
= Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
R
T
= Termination resistance should be equal to Z
OUT
of
pulse generators.
tTHL (tf
)
tTLH (tr
)
tTLH (tr
)
AMP (V)
amplitude
3.0V
1.5V
V
M
RL
7.0V
SF00777
TEST
SWITCH
t
PLZ
closed
t
PZL
closed
All other
open
SWITCH POSITION
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