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Электронный компонент: N74F646N

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Philips
Semiconductors
74F646, 74F646A
Octal transceiver/register, non-inverting
(3-State)
74F648, 74F648A
Octal transceiver/register, inverting
(3-State)
Product specification
IC15 Data Handbook
1990 Sep 25
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
74F646/A/74F648/A
Transceivers/registers
2
1990 Sep 25
853-1124 00515
FEATURES
Combines 74F245 and two 74F374 type functions in one chip
High impedance base inputs for reduced loading (70
A in high
and low states)
Independent registers for A and B buses
Multiplexed real-time and stored data
Choice of non-inverting and inverting data paths
Controlled ramp outputs for 74F646A/74F648A
3-state outputs
300 mil wide 24-pin slim dip package
DESCRIPTION
The 74F646/74F646A and 74F648/74F648A transceivers/registers
consist of bus transceiver circuits with 3state outputs, Dtype
flipflops, and control circuitry arranged for multiplexed transmission
of data directly from the input bus or the internal registers. Data on
the A or B bus will be clocked into the registers as the appropriate
clock pin goes high. Output enable (OE) and DIR pins are provided
to control the transceiver function. In the transceiver mode, data
present at the high impedance port may be stored in either the A or
B register or both.
The select (SAB, SBA) pins determine whether data is stored or
transferred through the device in realtime. The DIR determines
which bus will receive data when the OE is active low. In the
isolation mode (OE = high), data from bus A may be stored in the B
register and/or data from bus B may be stored in the A register.
When an output function is disabled, the input function is still
enabled and may be used to store and transmit data. Only one of
the two buses, A or B may be driven at a time.
TYPE
TYPICAL f
max
TYPICAL SUPPLY CURRENT ( TOTAL)
74F646/74F648
115MHz
140mA
74F646A/74F648A
185MHz
105mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
PKG DWG #
V
CC
= 5V
10%, T
amb
= 0
C to +70
C
24pin plastic slim DIP
(300mil)
N74F646N, N74F646AN, N74F648N, N74F648AN
SOT222-1
24pin plastic SOL
N74F646D, N74F646AD, N74F648D, N74F648AD
SOT137-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/
LOW
LOAD VALUE HIGH/
LOW
A0 A7, B0 B7
A and B inputs
3.5/0.116
70
A/70
A
CPAB
AtoB clock input
1.0/0.033
20
A/20
A
CPBA
BtoA clock input
1.0/0.033
20
A/20
A
SAB
AtoB select input
1.0/0.033
20
A/20
A
SBA
BtoA select input
1.0/0.033
20
A/20
A
DIR
Data flow directional control enable input
1.0/0.033
20
A/20
A
OE
Output enable input
1.0/0.033
20
A/20
A
A0 A7, B0 B7
A, B outputs for N74F646A/N74F648A
750/80
15mA/48mA
A0 A7, B0 B7
A, B outputs for N74F646/N74F648
750/106.7
15mA/64mA
NOTE: One (1.0) FAST unit load is defined as: 20
A in the high state and 0.6mA in the low state.
Philips Semiconductors
Product specification
74F646/A/74F648/A
Transceivers/registers
1990 Sep 25
3
PIN CONFIGURATION
24
23
22
21
20
19
18
17
16
15
14
13
12
10
11
9
8
7
6
5
4
3
2
1
VCC
74F646/646A
CPAB
SAB
DIR
A0
A1
A2
A3
A4
A5
A6
A7
GND
CPBA
SBA
OE
B0
B1
B2
B3
B4
B5
B6
B7
SF00386
LOGIC SYMBOL
CPAB
SAB
DIR
CPBA
SBA
OE
B0 B1
B2 B3
B4 B5
B6 B7
1
2
3
23
22
21
A0
A1 A2
A3 A4
A5 A6
A7
4
5
6
7
8
9
10
11
20
19
18
17
16
15
14
13
V
CC
= Pin 24
GND = Pin 12
74F646/646A
SF00387
IEC/IEEE SYMBOL
2
1
C4
G5
G7
C6
20
19
18
17
16
15
14
13
7
7
5
5
6D
4D
5
6
7
8
9
10
11
1
1
1
1
G3
3 EN1 [BA]
3 EN2 [AB]
23
22
1
2
4
74F646/646A
21
3
/
SF00388
LOGIC DIAGRAM
VCC = Pin 24
GND = Pin 12
A0
OE
B0
1D
C1
1D
C1
DIR
CPBA
SBA
CPAB
SAB
I of 8 channels
to 7 other channels
74F646/646A
3
23
22
1
21
2
4
20
SF00393
Philips Semiconductors
Product specification
74F646/A/74F648/A
Transceivers/registers
1990 Sep 25
4
PIN CONFIGURATION
74F648/648A
24
23
22
21
20
19
18
17
16
15
14
13
12
10
11
9
8
7
6
5
4
3
2
1
VCC
CPAB
SAB
DIR
A0
A1
A2
A3
A4
A5
A6
A7
GND
CPBA
SBA
OE
B0
B1
B2
B3
B4
B5
B6
B7
SF00389
LOGIC SYMBOL
V
CC
= Pin 24
GND = Pin 12
CPAB
SAB
DIR
CPBA
SBA
OE
B0 B1
B2 B3
B4 B5
B6 B7
1
2
3
23
22
21
A0 A1
A2 A3
A4 A5
A6 A7
4
5
6
7
8
9
10
11
20
19
18
17
16
15
14
13
74F648/648A
SF00390
IEC/IEEE SYMBOL
2
1
C4
G5
G7
C6
20
19
18
17
16
15
14
13
7
7
5
5
6D
4D
5
6
7
8
9
10
11
1
1
1
1
G3
3 EN1 [BA]
3 EN2 [AB]
23
22
1
2
4
74F648/648A
21
3
SF00391
LOGIC DIAGRAM
A0
OE
B0
1D
C1
1D
C1
DIR
CPBA
SBA
CPAB
SAB
I of 8 channels
to 7 other channels
74F648/648A
20
21
3
23
22
1
2
4
SF00400
Philips Semiconductors
Product specification
74F646/A/74F648/A
Transceivers/registers
1990 Sep 25
5
FUNCTION TABLE
INPUTS
DATA I/O
OPERATING MODE
OE
DIR
CPAB
CPBA
SAB
SBA
An
Bn
74F646/74F646A
74F648/74F648A
X
X
X
X
X
Input
Unspecified*
Store A, B unspecified*
Store A, B unspecified*
X
X
X
X
X
Unspecified*
Input
Store B, A unspecified*
Store B, A unspecified*
H
X
X
X
Input
Input
Store A and B data
Store A and B data
H
X
H or L
H or L
X
X
Input
Input
Isolation, hold storage
Isolation, hold storage
L
L
X
X
X
L
Output
Input
Real time B data to A bus
Real time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
Stored B data to A bus
L
H
X
X
L
X
Input
Output
Real time A data to B bus
Real time A data to B bus
L
H
H or L
X
H
X
Input
Output
Stored A data to B bus
Stored A data to B bus
NOTES:
1. H = Highvoltage level
2. L
= Lowvoltage level
3. X = Don't care
4.
= Lowtohigh clock transition
5. *
= The data output function may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are
always enabled, i.e., data at the bus pins will be stored on every lowtohigh transition of the clock.
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
V
CC
Supply voltage
0.5 to +7.0
V
V
IN
Input voltage
0.5 to +7.0
V
I
IN
Input current
30 to +5
mA
V
OUT
Voltage applied to output in high output state
0.5 to V
CC
V
I
OUT
Current applied to output in low output state
74F646A, 74F648A
72
mA
74F646, 74F648
128
mA
T
amb
Operating free air temperature range
0 to +70
C
T
stg
Storage temperature range
65 to +150
C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
MIN
NOM
MAX
V
CC
Supply voltage
4.5
5.0
5.5
V
V
IH
Highlevel input voltage
2.0
V
V
IL
Lowlevel input voltage
0.8
V
I
Ik
Input clamp current
18
mA
I
OH
Highlevel output current
15
mA
I
OL
Lowlevel output current
74F646A, 74F648A
48
mA
74F646, 74F648
64
mA
T
amb
Operating free air temperature range
0
+70
C
Philips Semiconductors
Product specification
74F646/A/74F648/A
Transceivers/registers
1990 Sep 25
6
The following examples demonstrate the four fundamental
busmanagement functions that can be performed with the
74F646/646A and 74F648/648A. The select pins determine whether
data is stored or transferred through the device in real time. The
output enable pins determine the direction of the data flow.
BUS MANAGEMENT FUNCTIONS
REAL TIME BUS TRANSFER
BUS B TO BUS A
REAL TIME BUS TRANSFER
BUS A TO BUS B
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
OE DIR CPAB CPBA SAB SBA
L
L
X
X
X
L
BUS A
BUS A
BUS A
BUS A
BUS B
BUS B
BUS B
BUS B
OE DIR CPAB CPBA SAB SBA
L
H
X
X
L
X
OE DIR CPAB CPBA SAB SBA
X
X
X
X
X
X
X
X
X
X
H
X
X
X
OE DIR CPAB CPBA SAB SBA
L
L
X
H or L
X
H
L
H
H or L
X
H
X
SF00392
Philips Semiconductors
Product specification
74F646/A/74F648/A
Transceivers/registers
1990 Sep 25
7
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST
LIMITS
UNIT
CONDITIONS
1
MIN
TYP
2
MAX
V
CC
= MIN,
I
OH
= 3mA
10%V
CC
2.4
V
V
OH
High-level output voltage
V
IL
= MAX,
5%V
CC
2.7
3.4
V
V
IH
= MIN
I
OH
=
15mA
10%V
CC
2.0
V
V
OL
Low-level output voltage
All
V
CC
= MIN,
V
IL
= MAX,
I
OL
= 48mA
10%V
CC
0.38
0.55
V
74F646/74F648 only
V
IH
= MIN
I
OL
= 64mA
5%V
CC
0.42
0.55
V
V
IK
Input clamp voltage
V
CC
= MIN, I
I
= I
IK
0.73
-1.2
V
I
I
Input current at
others
V
CC
= 0.0V, V
I
= 7.0V
100
A
maximum input voltage
A0A7, B0B7
V
CC
= MAX, V
I
= 5.5V
1
mA
I
IH
Highlevel input current
OE, DIR, CPAB,
V
CC
= MAX, V
I
= 2.7V
20
A
I
IL
Lowlevel input current
CPBA, SAB, SBA
V
CC
= MAX, V
I
= 0.5V
20
A
I
OZH
+ I
IH
Offstate output current,
highlevel voltage applied
A0 A7, B0 B7
V
CC
= MAX, V
O
= 2.7V
70
A
I
OZL
+ I
IL
Offstate output current,
lowlevel voltage applied
V
CC
= MAX, V
O
= 0.5V
70
A
I
OS
Shortcircuit output current
3
74F646, 74F648
V
CC
= MAX
-100
-225
mA
I
O
Output current
4
74F646A, 74F648A
V
CC
= MAX, V
0
= 2.25V
-60
-150
mA
74F646,
I
CCH
125
165
mA
74F648
I
CCL
V
CC
= MAX
160
210
mA
I
CC
Supply current (total)
I
CCZ
135
160
mA
74F646A,
I
CCH
100
145
mA
74F648A
I
CCL
V
CC
= MAX
110
155
mA
I
CCZ
105
155
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
Unless otherwise specified, V
X
= V
CC
for all test conditions.
2. All typical values are at V
CC
= 5V, T
amb
= 25
C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
4. I
O
is tested under conditions that produce current approximately one half of the true shortcircuit output current (I
OS
).
Philips Semiconductors
Product specification
74F646/A/74F648/A
Transceivers/registers
1990 Sep 25
8
AC ELECTRICAL CHARACTERISTICS FOR 74F646
LIMITS
T
amb
= +25
C
T
amb
= 0
C to +70
C
SYMBOL
PARAMETER
TEST CONDITION
V
CC
= +5.0V
V
CC
= +5.0V
10%
UNIT
C
L
= 50pF, R
L
= 500
C
L
= 50pF, R
L
= 500
MIN
TYP
MAX
MIN
MAX
f
max
Maximum clock frequency
Waveform 1
100
115
90
MHz
t
PLH
t
PHL
Propagation delay
CPAB or CPBA to An or Bn
Waveform 1
5.5
5.5
7.5
8.0
10.0
10.0
5.0
5.0
11.5
11.0
ns
t
PLH
t
PHL
Propagation delay
An to Bn or Bn to An
Waveform 2
4.0
4.0
6.0
6.5
9.0
8.0
4.0
4.0
10.0
10.0
ns
t
PLH
t
PHL
Propagation delay
SAB or SBA to An or Bn
Waveform 2, 3
5.0
5.0
7.0
6.5
8.5
8.5
4.5
4.5
10.5
9.5
ns
t
PZH
t
PZL
Output enable time
OE to An or Bn
Waveform 5
Waveform 6
5.0
6.5
7.0
8.5
10.0
11.0
4.5
6.0
11.0
12.5
ns
t
PZH
t
PZL
Output enable time
DIR to An or Bn
Waveform 5
Waveform 6
4.5
6.0
6.5
8.5
9.0
11.0
4.0
5.5
10.0
12.5
ns
t
PHZ
t
PLZ
Output disable time
OE to An or Bn
Waveform 5
Waveform 6
6.5
6.5
9.0
9.0
11.5
11.5
6.0
6.0
12.5
13.5
ns
t
PHZ
t
PLZ
Output disable time
DIR to An or Bn
Waveform 5
Waveform 6
5.5
5.5
8.5
8.5
11.0
11.0
4.5
5.0
13.0
12.5
ns
AC SETUP REQUIREMENTS FOR 74F646
LIMITS
T
amb
= +25
C
T
amb
= 0
C to +70
C
SYMBOL
PARAMETER
TEST CONDITION
V
CC
= +5.0V
V
CC
= +5.0V
10%
UNIT
C
L
= 50pF, R
L
= 500
C
L
= 50pF, R
L
= 500
MIN
TYP
MAX
MIN
MAX
t
su
(H)
t
su
(L)
Setup time, high or low
An or Bn to CPAB or CPBA
Waveform 4
4.5
4.5
5.0
5.0
ns
t
h
(H
)
t
h (
L
)
Hold time, high or low
An or Bn to CPAB or CPBA
Waveform 4
0
0
0
0
ns
t
w
(H)
t
w
(L)
Pulse width, high or low
CPAB or CPBA
Waveform 1
4.0
6.0
4.0
6.0
ns
Philips Semiconductors
Product specification
74F646/A/74F648/A
Transceivers/registers
1990 Sep 25
9
AC ELECTRICAL CHARACTERISTICS FOR 74F648
LIMITS
T
amb
= +25
C
T
amb
= 0
C to +70
C
SYMBOL
PARAMETER
TEST CONDITION
V
CC
= +5.0V
V
CC
= +5.0V
10%
UNIT
C
L
= 50pF, R
L
= 500
C
L
= 50pF, R
L
= 500
MIN
TYP
MAX
MIN
MAX
f
max
Maximum clock frequency
Waveform 1
100
115
90
MHz
t
PLH
t
PHL
Propagation delay
CPAB or CPBA to An or Bn
Waveform 1
5.0
5.0
7.0
7.5
9.5
9.5
4.5
4.5
11.0
11.0
ns
t
PLH
t
PHL
Propagation delay
An to Bn or Bn to An
Waveform 3
3.0
4.0
6.0
6.0
8.5
8.5
2.5
3.5
9.5
9.5
ns
t
PLH
t
PHL
Propagation delay
SAB or SBA to An or Bn
Waveform 2,3
4.5
4.5
7.0
6.5
8.5
8.5
4.5
4.5
10.5
9.5
ns
t
PZH
t
PZL
Output enable time
OE to An or Bn
Waveform 5
Waveform 6
4.5
6.0
7.0
8.5
10.0
11.0
4.5
5.5
11.0
12.5
ns
t
PZH
t
PZL
Output enable time
DIR to An or Bn
Waveform 5
Waveform 6
4.5
6.0
7.0
8.5
10.0
11.0
4.0
5.5
11.0
12.5
ns
t
PHZ
t
PLZ
Output disable time
OE to An or Bn
Waveform 5
Waveform 6
6.0
6.0
9.0
8.5
11.5
12.0
6.0
6.0
12.5
13.5
ns
t
PHZ
t
PLZ
Output disable time
DIR to An or Bn
Waveform 5
Waveform 6
5.0
5.0
9.0
9.0
12.5
12.5
4.5
5.0
14.0
14.0
ns
AC SETUP REQUIREMENTS FOR 74F648
LIMITS
T
amb
= +25
C
T
amb
= 0
C to +70
C
SYMBOL
PARAMETER
TEST CONDITION
V
CC
= +5.0V
V
CC
= +5.0V
10%
UNIT
C
L
= 50pF, R
L
= 500
C
L
= 50pF, R
L
= 500
MIN
TYP
MAX
MIN
MAX
t
su
(H)
t
su
(L)
Setup time, high or low
An or Bn to CPAB or CPBA
Waveform 4
4.0
4.0
5.0
5.0
ns
t
h
(H
)
t
h (
L
)
Hold time, high or low
An or Bn to CPAB or CPBA
Waveform 4
0
0
0
0
ns
t
w
(H)
t
w
(L)
Pulse width, high or low
CPAB or CPBA
Waveform 1
3.5
6.5
4.0
7.0
ns
Philips Semiconductors
Product specification
74F646/A/74F648/A
Transceivers/registers
1990 Sep 25
10
AC ELECTRICAL CHARACTERISTICS FOR 74F646A
LIMITS
T
amb
= +25
C
T
amb
= 0
C to +70
C
SYMBOL
PARAMETER
TEST CONDITION
V
CC
= +5.0V
V
CC
= +5.0V
10%
UNIT
C
L
= 50pF, R
L
= 500
C
L
= 50pF, R
L
= 500
MIN
TYP
MAX
MIN
MAX
f
max
Maximum clock frequency
Waveform 1
165
185
150
MHz
t
PLH
t
PHL
Propagation delay
CPAB or CPBA to An or Bn
Waveform 1
5.5
4.5
7.0
7.0
10.5
9.5
4.5
4.0
11.0
10.0
ns
t
PLH
t
PHL
Propagation delay
An to Bn or Bn to An
Waveform 2
4.0
2.0
6.0
5.0
9.0
8.0
3.5
2.0
10.0
8.0
ns
t
PLH
t
PHL
Propagation delay
SAB or SBA to An or Bn
Waveform 2, 3
4.5
3.5
6.5
8.0
9.5
10.0
4.0
3.0
10.0
11.5
ns
t
PZH
t
PZL
Output enable time
OE to An or Bn
Waveform 5
Waveform 6
3.0
3.0
5.5
5.5
9.0
10.0
2.5
2.5
10.0
10.5
ns
t
PZH
t
PZL
Output enable time
DIR to An or Bn
Waveform 5
Waveform 6
3.0
3.5
5.0
6.0
8.0
8.5
3.0
3.0
8.5
9.5
ns
t
PHZ
t
PLZ
Output disable time
OE to An or Bn
Waveform 5
Waveform 6
1.5
2.5
4.0
5.5
6.5
8.0
1.0
2.0
8.0
9.5
ns
t
PHZ
t
PLZ
Output disable time
DIR to An or Bn
Waveform 5
Waveform 6
2.0
3.0
4.5
5.0
7.5
8.0
1.5
2.0
8.5
8.5
ns
AC SETUP REQUIREMENTS FOR 74F646A
LIMITS
T
amb
= +25
C
T
amb
= 0
C to +70
C
SYMBOL
PARAMETER
TEST CONDITION
V
CC
= +5.0V
V
CC
= +5.0V
10%
UNIT
C
L
= 50pF, R
L
= 500
C
L
= 50pF, R
L
= 500
MIN
TYP
MAX
MIN
MAX
t
su
(H)
t
su
(L)
Setup time, high or low
An or Bn to CPAB or CPBA
Waveform 4
3.5
4.0
4.0
4.5
ns
t
h
(H
)
t
h (
L
)
Hold time, high or low
An or Bn to CPAB or CPBA
Waveform 4
0
0
0
0
ns
t
w
(H)
t
w
(L)
Pulse width, high or low
CPAB or CPBA
Waveform 1
3.5
3.5
4.5
4.0
ns
Philips Semiconductors
Product specification
74F646/A/74F648/A
Transceivers/registers
1990 Sep 25
11
AC ELECTRICAL CHARACTERISTICS FOR 74F648A
LIMITS
T
amb
= +25
C
T
amb
= 0
C to +70
C
SYMBOL
PARAMETER
TEST CONDITION
V
CC
= +5.0V
V
CC
= +5.0V
10%
UNIT
C
L
= 50pF, R
L
= 500
C
L
= 50pF, R
L
= 500
MIN
TYP
MAX
MIN
MAX
f
max
Maximum clock frequency
Waveform 1
160
185
135
ns
t
PLH
t
PHL
Propagation delay
CPAB or CPBA to An or Bn
Waveform 1
5.0
5.5
7.0
7.5
9.5
10.0
4.5
4.5
10.5
10.5
ns
t
PLH
t
PHL
Propagation delay
An to Bn or Bn to An
Waveform 3
2.5
4.0
4.5
6.0
7.5
8.5
2.0
4.0
8.5
9.5
ns
t
PLH
t
PHL
Propagation delay
SAB or SBA to An or Bn
Waveform 2, 3
4.0
4.5
7.0
7.0
9.5
9.5
3.5
4.5
11.5
10.0
ns
t
PZH
t
PZL
Output enable time
OE to An or Bn
Waveform 5
Waveform 6
3.5
4.5
6.5
6.5
10.0
10.0
3.5
4.0
11.0
11.5
ns
t
PZH
t
PZL
Output enable time
DIR to An or Bn
Waveform 5
Waveform 6
3.5
4.0
5.5
6.5
8.5
9.5
3.0
4.0
9.0
10.0
ns
t
PHZ
t
PLZ
Output disable time
OE to An or Bn
Waveform 5
Waveform 6
2.5
4.0
4.0
6.5
6.5
9.0
2.0
3.5
8.0
10.0
ns
t
PHZ
t
PLZ
Output disable time
DIR to An or Bn
Waveform 5
Waveform 6
2.5
2.5
5.0
5.0
8.5
8.0
2.0
3.5
9.0
9.0
ns
AC SETUP REQUIREMENTS FOR 74F648A
LIMITS
T
amb
= +25
C
T
amb
= 0
C to +70
C
SYMBOL
PARAMETER
TEST CONDITION
V
CC
= +5.0V
V
CC
= +5.0V
10%
UNIT
C
L
= 50pF, R
L
= 500
C
L
= 50pF, R
L
= 500
MIN
TYP
MAX
MIN
MAX
t
su
(H)
t
su
(L)
Setup time, high or low
An or Bn to CPAB or CPBA
Waveform 4
4.0
4.0
4.5
4.5
ns
t
h
(H
)
t
h (
L
)
Hold time, high or low
An or Bn to CPAB or CPBA
Waveform 4
0
0
0
0
ns
t
w
(H)
t
w
(L)
Pulse width, high or low
CPAB or CPBA
Waveform 1
3.5
3.5
4.0
3.5
ns
AC WAVEFORMS
CPBA
or
CPAB
VM
VM
VM
tw(H)
1/fmax
VM
VM
tPLH
tw(L)
tPHL
An or Bn
SF00394
Waveform 1. Propagation delay for clock input to output clock
pulse width, and maximum clock frequency
SF00395
V
M
V
M
V
M
V
M
Bn or An
An or Bn
t
PLH
t
PHL
SBA or SAB
An or Bn
Waveform 2. Propagation delay for An to Bn or Bn to An and
SAB or SBA to An or Bn
Philips Semiconductors
Product specification
74F646/A/74F648/A
Transceivers/registers
1990 Sep 25
12
AC WAVEFORMS (Continued)
VM
VM
VM
VM
tPHL
tPLH
An or Bn
Bn or An
SBA or SAB
An or Bn
SF00396
Waveform 3. Propagation delay for An to Bn or Bn to An and
SAB or SBA to An or Bn
VM
VM
VM
VM
VM
VM
tsu(L)
th(L)
tsu(H)
th(H)
An or Bn
CPBA
or
CPAB
SF00397
Waveform 4. Data setup time and hold times
VM
VM
VM
tPHZ
tPZH
OE
VOH -0.3V
0V
An or Bn
DIR
SF00398
Waveform 5. 3-state output enable time to high level and
output disable time from high level
VM
VM
VM
tPLZ
tPZL
VOL +0.3V
3.5V
OE
DIR
An or Bn
SF00399
Waveform 6. 3-state output enable time to low level and output
disable time from low level
NOTES:
1. For all waveforms, V
M
= 1.5V.
2. The shaded areas indicate when the input is permitted to change for predictable output performance.
TEST CIRCUIT AND WAVEFORM
tw
90%
VM
10%
90%
VM
10%
90%
VM
10%
90%
VM
10%
NEGATIVE
PULSE
POSITIVE
PULSE
tw
AMP (V)
0V
0V
tTHL (tf
)
INPUT PULSE REQUIREMENTS
rep. rate
t
w
t
TLH
t
THL
1MHz
500ns
2.5ns
2.5ns
Input Pulse Definition
VCC
family
74F
D.U.T.
PULSE
GENERATOR
RL
CL
RT
VIN
VOUT
Test Circuit for Open Collector Outputs
DEFINITIONS:
R
L
= Load resistor;
see AC electrical characteristics for value.
C
L
= Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
R
T
= Termination resistance should be equal to Z
OUT
of
pulse generators.
tTHL (tf
)
tTLH (tr
)
tTLH (tr
)
AMP (V)
amplitude
3.0V
1.5V
V
M
RL
7.0V
SF00128
TEST
SWITCH
t
PLZ
closed
t
PZL
closed
All other
open
SWITCH POSITION
Philips Semiconductors
Product specification
74F646/A/74F648/A
Transceivers/registers
1990 Sep 25
13
DIP24:
plastic dual in-line package; 24 leads (300 mil)
SOT222-1
Philips Semiconductors
Product specification
74F646/A/74F648/A
Transceivers/registers
1990 Sep 25
14
SO24:
plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
Philips Semiconductors
Product specification
74F646/A/74F648/A
Transceivers/registers
1990 Sep 25
15
NOTES
Philips Semiconductors
Product specification
74F646/A/74F648/A
Transceivers/registers
yyyy mmm dd
16
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code
Date of release: 10-98
Document order number:
9397-750-05151
Philips
Semiconductors
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
[1]
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
Data sheet status
[1]
Please consult the most recently issued datasheet before initiating or completing a design.