Philips Semiconductors
Product specification
NE/SE564
Phase-locked loop
1
1994 Aug 31
853-0908 13720
DESCRIPTION
The NE/SE564 is a versatile, high guaranteed frequency
phase-locked loop designed for operation up to 50MHz. As shown
in the Block Diagram, the NE/SE564 consists of a VCO, limiter,
phase comparator, and post detection processor.
FEATURES
Operation with single 5V supply
TTL-compatible inputs and outputs
Guaranteed operation to 50MHz
External loop gain control
Reduced carrier feedthrough
No elaborate filtering needed in FSK applications
Can be used as a modulator
Variable loop gain (externally controlled)
APPLICATIONS
High speed modems
FSK receivers and transmitters
Frequency Synthesizers
PIN CONFIGURATIONS
V+
LOOP FILTER
D, N Packages
TTL OUTPUT
LOOP GAIN CONTROL
INPUT TO PHASE COMP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
FROM VCO
LOOP FILTER
FM/RF INPUT
BIAS FILTER
GND
HYSTERESIS SET
ANALOG OUT
FREQ. SET CAP
VCO OUT 2
V+
VCO OUT TTL
FREQ. SET CAP
TOP VIEW
SR01025
Figure 1. Pin Configuration
Signal generators
Various satcom/TV systems
pin configuration
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
DWG #
16-Pin Plastic Small Outline (SO) Package
0 to +70
C
NE564D
SOT109-1
16-Pin Plastic Dual In-Line Package (DIP)
0 to +70
C
NE564N
SOT38-4
16-Pin Plastic Dual In-Line Package (DIP)
-55 to +125
C
SE564N
SOT38-4
BLOCK DIAGRAM
LIMITER
VCO
PHASE
COMPARATOR
SCHMITT
TRIGGER
RETRIEVER
DC
AMPLIFIER
POST DETECTION
PROCESSOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V+
SR01026
Figure 2. Block Diagram
Philips Semiconductors
Product specification
NE/SE564
Phase-locked loop
1994 Aug 31
2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNITS
V+
Supply voltage
Pin 1
Pin 10
14
6
V
V
I
OUT
Sink Max (Pin 9) and sourcing (Pin 11)
11
mA
I
BIAS
Bias current adjust pin (sinking)
1
mA
P
D
Power dissipation
600
mW
T
A
Operating ambient temperature
NE
0 to +70
C
SE
-55 to +125
C
T
STG
Storage temperature range
-65 to +150
C
NOTE:
Operation above 5V will require heatsinking of the case.
DC AND AC ELECTRICAL CHARACTERISTICS
V
CC
= 5V; T
A
= 0 to 25
C; f
O
= 5MHz, I
2
= 400
A; unless otherwise specified.
LIMITS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
SE564
NE564
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
Maximum VCO frequency
C
1
= 0 (stray)
50
65
45
60
MHz
Lock range
Input > 200mV
RMS
T
A
= 25
C
T
A
= 125
C
T
A
= -55
C
T
A
= 0
o
C
T
A
= 70
C
40
20
50
70
30
80
40
70
70
40
% of f
O
Capture range
Input > 200mV
RMS
, R
2
= 27
20
30
20
30
% of f
O
VCO frequency drift with
temperature
f
O
= 5MHz,
T
A
= -55
C to +125
C
T
A
= 0 to +70
C
= 0 to +70
C
f
O
= 5MHz,
T
A
= -55
C to +125
C
T
A
= 0 to +70
C
500
300
1500
800
600
500
PPM/
o
C
VCO free-running frequency
C
1
= 91pF
R
C
= 100
"Internal"
4
5
6
3.5
5
6.5
MHz
VCO frequency change with
supply voltage
V
CC
= 4.5V to 5.5V
3
8
3
8
% of f
O
Demodulated output voltage
Modulation frequency: 1kHz
f
O
= 5MHz, input deviation:
2%T = 25
C
1%T = 25
C
1%T = 0
C
1%T = -55
C
1%T = 70
C
1%T = 125
C
16
8
6
12
28
14
10
16
16
8
28
14
13
15
mV
RMS
mV
RMS
mV
RMS
mV
RMS
mV
RMS
mV
RMS
Distortion
Deviation: 1% to 8%
1
1
%
S/N
Signal-to-noise ratio
Std. condition, 1% to 10% dev.
40
40
dB
AM rejection
Std. condition, 30% AM
35
35
dB
Demodulated output at oper-
ating voltage
Modulation frequency: 1kHz
f
O
= 5MHz, input deviation: 1%
V
CC
= 4.5V
V
CC
= 5.5V
7
8
12
14
7
8
12
14
mV
RMS
mV
RMS
I
CC
Supply current
V
CC
= 5V I
1
, I
10
45
60
45
60
mA
Output
"1" output leakage current
"0" output voltage
V
OUT
= 5V, Pins 16, 9
I
OUT
= 2mA, Pins 16, 9
I
OUT
= 6mA, Pins 16, 9
1
0.3
0.4
20
0.6
0.8
1
0.3
0.4
20
0.6
0.8
A
V
V
Philips Semiconductors
Product specification
NE/SE564
Phase-locked loop
1994 Aug 31
3
TYPICAL PERFORMANCE CHARACTERISTICS
1000
8
6
4
2
100
8
6
4
2
10
0.7
0.8
0.9
1.0
1.1
1.2
1.3
VCC 5V
fo = 5MHz
IPIN = 400
A
2
IPIN = 0
A
2
INPUT
SIGNAL
LEVEL
mV
NORMALIZED LOCK RANGE
105
106
104
103
102
102
103
104
105
10
1
.1
1
10
FREQUENCY kHz
CAP
ACIT
ANCE pF
FREQUENCY: 50MHz
1.01
1.00
0.99
0.98
0.97
0.96
600
A
400
200
0
+200
BIAS CURENT (
A), PIN 2
NORMALIZED VCO FREQUENCY
VCO FREQUENCY: 50MHz
600
A 400
200
0
+200
+400
BIAS CURENT (
A), PIN 2
NORMALIZED VCO FREQUENCY
1.10
1.05
1.00
0.95
0.90
BIAS CURRENT: -- 200
A
FREQUENCY: 5MHz
FREQUENCY: 500MHz
BIAS CURRENT: -- 200
A
1.10
1.05
1.00
0.95
0.90
50
25
25
0
25
50
75
100
125
TEMPERATURE (IN
o
C)
NORMALIZED VCO FREQUENCY
Lock Range vs Signal Input
VCO Capacitor vs Frequency
Typical Noirmalized VCO
Frequency as a Function of
Pin 2 Bias Current
Typical Noirmalized VCO
Frequency as a Function of
Pin 2 Bias Current
Typical Noirmalized VCO
Frequency as a Function of
Temperature
SR01027
Figure 3. Typical Performance Characteristics
Philips Semiconductors
Product specification
NE/SE564
Phase-locked loop
1994 Aug 31
4
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
IBIAS = 200
A
VCO FREQUENCY
IN MHz
IBIAS = 00
A
1.6
1.4
1.2
0
fo = 1.0MHz
400
200
200
400
600
800
VDIN mV
.8
.6
IBIAS = 800
A
40
60
100
120
140
160
0 PHASE
ERROR IN
DEGREES
800
600
400
200
200
400
600
800
VD PHASE COMPARATOR'S
OUTPUT VOLTAGE IN mV
IBIAS = 800
A
IBIAS = 400
A
IBIAS = 0
A
Variation of the Comparator's Output Voltage
vs Phase Error and Bias Current (K
D
)
VCO Output Frequency as a Function of
Input Voltage and Bias Current (K
O
)
SR01028
Figure 4. Typical Performance Characteristics (cont.)
TEST CIRCUIT
+5V
INPUT
C3
0.1
F
1K
C2
C2
R2
430pF
R2
430pF
R1
R3
1
2
10
16
9
3
14
13
12
8
5
4
7
6
564
15
pF
VCO
OUYPUT
390
DEMODULATED
OUTPUT
C1
0.1
F
1K
SR01029
Figure 5. Test Circuit
Philips Semiconductors
Product specification
NE/SE564
Phase-locked loop
1994 Aug 31
5
FUNCTIONAL DESCRIPTION
(Figure 6)
The NE564 is a monolithic phase-locked loop with a post detection
processor. The use of Schottky clamped transistors and optimized
device geometries extends the frequency of operation to greater
than 50MHz.
In addition to the classical PLL applications, the NE564 can be used
as a modulator with a controllable frequency deviation.
The output of the PLL can be written as shown in the following
equation:
V
O
=
(f
IN
- f
O
)
K
VCO
(1)
K
VCO
= conversion gain of the VCO
f
IN
= frequency of the input signal
f
O
= free-running frequency of the VCO
The process of recovering FSK signals involves the conversion of
the PLL output into logic compatible signals. For high data rates, a
considerable amount of carrier will be present at the output of the
PLL due to the wideband nature of the loop filter. To avoid the use
of complicated filters, a comparator with hysteresis or Schmitt trigger
is required. With the conversion gain of the VCO fixed, the output
voltage as given by Equation 1 varies according to the frequency
deviation of f
IN
from f
O
. Since this differs from system to system, it
is necessary that the hysteresis of the Schmitt trigger be capable of
being changed, so that it can be optimized for a particular system.
This is accomplished in the 564 by varying the voltage at Pin 15
which results in a change of the hysteresis of the Schmitt trigger.
For FSK signals, an important factor to be considered is the drift in
the free-running frequency of the VCO itself. If this changes due to
temperature, according to Equation 1 it will lead to a change in the
DC levels of the PLL output, and consequently to errors in the digital
output signal. This is especially true for narrowband signals where
the deviation in f
IN
itself may be less than the change in f
O
due to
temperature. This effect can be eliminated if the DC or average
value of the signal is retrieved and used as the reference to the
comparator. In this manner, variations in the DC levels of the PLL
output do not affect the FSK output.
VCO Section
Due to its inherent high-frequency performance, an emitter-coupled
oscillator is used in the VCO. In the circuit, shown in the equivalent
schematic, transistors Q21 and Q23 with current sources Q25 - Q26
form the basic oscillator. The approximate free-running frequency of
the oscillator is shown in the following equation:
f
O
1
22 R
C
(C
1
+ C
S
)
(2)
R
C
= R
19
= R
20
= 100
(INTERNAL)
C
1
= external frequency setting capacitor
C
S
= stray capacitance
Variation of V
D
(phase detector output voltage) changes the
frequency of the oscillator. As indicated by Equation 2, the
frequency of the oscillator has a negative temperature coefficient
due to the monolithic resistor. To compensate for this, a current I
R
with negative temperature coefficient is introduced to achieve a low
frequency drift with temperature.
Phase Comparator Section
The phase detection processor consists of a doubled-balanced
modulator with a limiter amplifier to improve AM rejection.
Schottky-clamped vertical PNPs are used to obtain TTL level inputs.
The loop gain can be varied by changing the current in Q
4
and Q
15
which effectively changes the gain of the differential amplifiers. This
can be accomplished by introducing a current at Pin 2.
Post Detection Processor Section
The post detection processor consists of a unity gain
transconductance amplifier and comparator. The amplifier can be
used as a DC retriever for demodulation of FSK signals, and as a
post detection filter for linear FM demodulation. The comparator has
adjustable hysteresis so that phase jitter in the output signal can be
eliminated.
As shown in the equivalent schematic, the DC retriever is formed by
the transconductance amplifier Q
42
- Q
43
together with an external
capacitor which is connected at the amplifier output (Pin 14). This
forms an integrator whose output voltage is shown in the following
equation:
V
O
=
g
M
C
2
(3)
V
IN
dt
g
M
= transconductance of the amplifier
C
2
= capacitor at the output (Pin 14)
V
IN
= signal voltage at amplifier input
With proper selection of C
2
, the integrator time constant can be
varied so that the output voltage is the DC or average value of the
input signal for use in FSK, or as a post detection filter in linear
demodulation.
The comparator with hysteresis is made up of Q
49
- Q
50
with
positive feedback being provided by Q
47
- Q
48
. The hysteresis is
varied by changing the current in Q
52
with a resulting variation in the
loop gain of the comparator. This method of hysteresis control,
which is a DC control, provides symmetric variation around the
nominal value.
Design Formula
The free-running frequency of the VCO is shown by the following
equation:
(4)
f
O
1
22 R
C
(C
1
+ C
S
)
R
C
= 100
C
1
= external cap in farads
C
S
= stray capacitance
The loop filter diagram shown is explained by the following equation:
(5)
f
S
=
1
1 + sRC
3
(First Order)
R = R
12
= R
13
= 1.3k
(Internal)*
By adding capacitors to Pins 4 and 5, a pole is added to the loop
transfer at
=
1
RC
3
NOTE:
*Refer to Figure 6.
Philips Semiconductors
Product specification
NE/SE564
Phase-locked loop
1994 Aug 31
6
EQUIVALENT SCHEMATIC
Q41
Q46
LIMITER
PHASE
COMPARATOR
VCO
AMPLIFIER
DC RETRIEVER
SCHMITT TRIGGER
1
7
5
3
2
8
6
14
1
15
16
10
11
9
12
13
900
10k
10k
10k
10k
10k
2k
R3
2k
10k
10k
10k
10k
750
750
680
4.3k
1.3k
1.3k
Q1
Q2 Q3
Q4
Q5
Q15
Q7
Q6
Q9
Q10
Q11
Q12
Q13
Q14
6.8k
6.8k
D1
D2
D3
D4
Q16
D5
D10
D11
Q30
Q29
Q33
Q31
Q32
Q34
Q36
Q31
Q42
Q22
Q45
R26
Q37
Q39
R29
D12
R27
R48
Q42
Q49
Q50
Q44
QR
Q24
Q23
Q22
Q21
R36
100
R35
100
Q28
Q27
Q40
Q41
Q47
Q48
D11
Q58
R23
R22
R21
R33
R34
Q35
100
Q20
Q25
Q26
R20
R19
Q14
Q15
R17
4.3k
R16
R18
D7
D6
D9
D8
Q17
6.2k
62k
R10 500
R1
1
500
R12
10K
R34
6.2K
R33
6.2K
R1
R4
R2
2k
R5
R6
R8
R7
1k
R8
1k
R12
R10
R1
1
R13
.75mA
R14
SR01030
Figure 6. Equivalent Schematic
LOCK RANGE ADJUSTMENT
FM INPUT
BIAS FILTER
LOOP FILTER
ANALOG OUT
POST DETECTION FILTER
FREQUENCY SET CAP
1k
1k
5V
5V
80pF
1kHz
.01
F
0.01
F
0.1
F
0.01
F
I
2
0.47
F
fO = 5MHz
fM = 1kHz
fO = 5MHz
6
7
3
1
8
10
9
12
13
14
15
5
4
11
2
16
564
SR01031
Figure 7. FM Demodulator at 5V
Philips Semiconductors
Product specification
NE/SE564
Phase-locked loop
1994 Aug 31
7
APPLICATIONS
FM Demodulator
The NE564 can be used as an FM demodulator. The connections
for operation at 5V and 12V are shown in Figures 7 and 8,
respectively. The input signal is AC coupled with the output signal
being extracted at Pin 14. Loop filtering is provided by the
capacitors at Pins 4 and 5 with additional filtering being provided by
the capacitor at Pin 14. Since the conversion gain of the VCO is not
very high, to obtain sufficient demodulated output signal the
frequency deviation in the input signal should be 1% or higher.
Modulation Techniques
The NE564 phase-locked loop can be modulated at either the loop
filter ports (Pins 4 and 5) or the input port (Pin 6) as shown in Figure
9. The approximate modulation frequency can be determined from
the frequency conversion gain curve shown in Figure 10. This curve
will be appropriate for signals injected into Pins 4 and 5 as shown in
Figure 9.
LOCK RANGE ADJUSTMENT
FM INPUT
BIAS
LOOP FILTER
ANALOG OUT
POST
FREQUENCY SET CAP
1k
1k
12V
80pF
1kHz
.01
F
0.01
F
0.1
F
0.01
F
I
2
0.47
F
fO = 5MHz
fM = 1kHz
fO = 5MHz
6
7
3
1
8
10
9
12
13
14
15
5
4
11
2
16
.01
F
200
564
DETECTION
FILTER
FILTER
SR01032
Figure 8. FM Demodulator at 12V
FSK Demodulation
The 564 PLL is particularly attractive for FSK demodulation since it
contains an internal voltage comparator and VCO which have TTL
compatible inputs and outputs, and it can operate from a single 5V
power supply. Demodulated DC voltages associated with the mark
and space frequencies are recovered with a single external
capacitor in a DC retriever without utilizing extensive filtering
networks. An internal comparator, acting as a Schmitt trigger with
an adjustable hysteresis, shapes the demodulated voltages into
compatible TTL output levels. The high-frequency design of the 564
enables it to demodulate FSK at high data rates in excess of 1.0M
baud.
Figure 10 shows a high-frequency FSK decoder designed for input
frequency deviations of +1.0MHz centered around a free-running
frequency of 10.8MHz. the value of the timing capacitance required
was estimated from Figure 8 to be approximately 40pF. A trimmer
capacitor was added to fine tune f
O
' 10.8MHz.
MODULATING
FREQUENCY SET CAP
1k
2k
5V
5V
80pF
.01
F
I
2
0.47
F
fO = 5MHz
6
7
3
1
8
10
9
12
13
14
15
5
4
11
2
16
564
MODULATED OUTPUT
(TTL)
5V
FINE FREQUENCY
ADJUSTMENT
INPUT
1kHz
1kHz
1k
SR01033
Figure 9. Modulator
The lock range graph indicates that the +1.0MHz frequency
deviations will be within the lock range for input signal levels greater
than approximately 50mV with zero Pin 2 bias current. (While
strictly this figure is appropriate only for 50MHz, it can be used as a
guide for lock range estimates at other f
O
' frequencies).
The hysteresis was adjusted experimentally via the 10k
potentiometer and 2k
bias arrangement to give the waveshape
shown in Figure 12 for 20k, 500k, 2M baud rates with square wave
FSK modulation. Note the magnitude and phase relationships of the
phase comparators' output voltages with respect to each other and
to the FSK output. The high-frequency sum components of the input
and VCO frequency also are viable as noise on the phase
comparator's outputs.
OUTLINE OF SETUP PROCEDURE
1. Determine operating frequency of the VCO: IF
N in feedback
loop, then
f
O
= N x f
IN
.
2. Calculate value of the VCO frequency set capacitor:
C
O
1
2200 f
O
3. Set I
2
(current sinking into Pin 2) for
100
A. After operation is
obtained, this value may be adjusted for best dynamic behavior,
and replace with fixed resistor value of R
2
=
V
CC
*
1.3V
I
B
2
.
4. Check VCO output frequency with digital counter at Pin 9 of
device (loop open, VCO to
det.). Adjust C
O
trim or frequency
adj. Pins 4 - 5 for exact center frequency, if needed.
5. Close loop and inject input signal to Pin 6. Monitor Pins 3 and 6
with two-channel scope. Lock should occur with
3 - 6
equal to
90
o
(phase error).
Philips Semiconductors
Product specification
NE/SE564
Phase-locked loop
1994 Aug 31
8
6. If pulsed burst or ramp frequency is used for input signal, special
loop filter design may be required in place of simple single
capacitor filter on Pins 4 and 5. (See PLL application section)
7. The input signal to Pin 6 and the VCO feedback signal to Pin 3
must have a duty cycle of 50% for proper operation of the phase
detector. Due to the nature of a balanced mixer if signals are not
50% in duty cycle, DC offsets will occur in the loop which tend to
create an artificial or biased VCO.
8. For multiplier circuits where phase jitter is a problem, loop filter
capacitors may be increased to a value of 10 - 50
F on Pins 4,
5. Also, careful supply decoupling may be necessary. This
includes the counter chain V
CC
lines.
1
2
6
7
3
9
11
4
5
10
15
16
14
12
13
8
+5V
BIAS
ADJ
2k
FSK
INPUT
1k
1k
+5V
300pF
300pF
HYSTERESIS
ADJUST
10k
2k
1.2k
FSK
OUTPUT
020pF
33pF
NE564
510
0.1
F
10k
0.1
F
0.22
F
0.22
F
10
F/8V
*510
*NOTE:
Use R9-11 only if rise time is critical.
SR01034
Figure 10. 10.8MHz FSK Decoder Using the 564
Philips Semiconductors
Product specification
NE/SE564
Phase-locked loop
1994 Aug 31
9
SR01035
Figure 11. Phase Comparator (Pins 4 and 5) and FSK (Pin 16) Outputs
BIAS ADJUST
+5V
CER.
INPUT SIGNAL
NE564
DET.
VCO
OUTPUT
LOOP
FILTER
VCO
6
7
3
8
12
13
9
11
5
4
10
1
2
.47
F CER.
.47
F
.33
F
.33
F
f = NxfT
CO
.47
F
fT
NxfT
*510
1k
2k
I2
10k
N
510
*NOTE:
Use R9-11 only if rise time is critical.
Figure 12. NE564 Phase-Locked Frequency Multiplier
PDF 
ZIP