Philips Semiconductors

Product data

80C552/83C552

Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM

2002 Sep 03

853-1467 28849

DESCRIPTION

The 80C552/83C552 (hereafter generically referred to as 8XC552)
Single-Chip 8-Bit Microcontroller is manufactured in an advanced
CMOS process and is a derivative of the 80C51 microcontroller
family. The 8XC552 has the same instruction set as the 80C51.
Three versions of the derivative exist:

83C552--8 kbytes mask programmable ROM

80C552--ROMless version of the 83C552

87C552--8 kbytes EPROM (described in a separate chapter)

The 8XC552 contains a non-volatile 8k

8 read-only program

memory (83C552), a volatile 256

8 read/write data memory, five

8-bit I/O ports, one 8-bit input port, two 16-bit timer/event counters
(identical to the timers of the 80C51), an additional 16-bit timer
coupled to capture and compare latches, a 15-source,
two-priority-level, nested interrupt structure, an 8-input ADC, a dual
DAC pulse width modulated interface, two serial interfaces (UART
and I

C-bus), a "watchdog" timer and on-chip oscillator and timing

circuits. For systems that require extra capability, the 8XC552 can
be expanded using standard TTL compatible memories and logic.

In addition, the 8XC552 has two software selectable modes of
power reduction--idle mode and power-down mode. The idle mode
freezes the CPU while allowing the RAM, timers, serial ports, and
interrupt system to continue functioning. The power-down mode
saves the RAM contents but freezes the oscillator, causing all other
chip functions to be inoperative.

The device also functions as an arithmetic processor having
facilities for both binary and BCD arithmetic plus bit-handling
capabilities. The instruction set consists of over 100 instructions: 49
one-byte, 45 two-byte, and 17 three-byte. With a 16 MHz (24 MHz)
crystal, 58% of the instructions are executed in 0.75

s (0.5

s) and

40% in 1.5

s (1

s). Multiply and divide instructions require 3

s).

FEATURES

80C51 central processing unit

8 ROM expandable externally to 64 kbytes

ROM code protection

An additional 16-bit timer/counter coupled to four capture registers
and three compare registers

Two standard 16-bit timer/counters

256

8 RAM, expandable externally to 64 kbytes

Capable of producing eight synchronized, timed outputs

A 10-bit ADC with eight multiplexed analog inputs

Two 8-bit resolution, pulse width modulation outputs

Five 8-bit I/O ports plus one 8-bit input port shared with analog
inputs

C-bus serial I/O port with byte oriented master and slave

functions

Full-duplex UART compatible with the standard 80C51

On-chip watchdog timer

Three speed ranges:

3.5 to 16 MHz

3.5 to 24 MHz (ROM, ROMless only)

Three operating ambient temperature ranges:

P83C552xBx: 0

C to +70

P83C552xFx: 40

C to +85

(XTAL frequency max. 24 MHz)

P83C552xHx: 40

C to +125

(XTAL frequency max. 16 MHz)

LOGIC SYMBOL

SU01691

POR

ADC0-7

CMT0
CMT1

CMSR0-5

RST

XTAL1
XTAL2

ALE

PSEN

AVref+
AVref

STADC

PWM0
PWM1

POR

LOW ORDER

ADDRESS AND

DATA BUS

POR

CT0I
CT1I
CT2I
CT3I
T2
RT2
SCL
SDA

RxD/DATA

TxD/CLOCK

INT0
INT1
T0
T1
WR
RD

VSS
VDD

AVSS

AVDD

HIGH ORDER

ADDRESS AND

DATA BUS

Philips Semiconductors

Product data

80C552/83C552

Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM

2002 Sep 03

PIN CONFIGURATIONS

Plastic Leaded Chip Carrier

NC*

P3.7/RD

P3.6/WR

P5.0/ADC0

P4.3/CMSR3

P4.4/CMSR4

P4.5/CMSR5

P4.6/CMT0

P4.7/CMT1

P1.0/CT0I

RST

P1.1/CT1I

P1.2/CT2I

P1.4/T2

P1.3/CT3I

PLASTIC LEADED CHIP CARRIER

SU00932

P1.5/RT2

P1.6/SCL

P1.7/SDA

P3.0/RxD

P3.2/INT0

P3.1/TxD

P3.4/T0

P3.5/T1

NC*

AL2

AL1

P2.1/A09

P2.2/A10

P2.3/A1

P2.4/A12

REF+

REF

P0.0/AD0

P0.1/AD1

P0.3/AD3

P0.2/AD2

P0.4/AD4

P0.5/AD5

P0.7/AD7

P0.6/AD6

ALE

PSEN

P2.7/A15

P2.5/A13

P2.6/A14

P4.2/CMSR2

P4.1/CMSR1

P4.0/CMSR0

PWM1

PWM0

ADC

P5.1/ADC1

P5.2/ADC2

P5.3/ADC3

P5.4/ADC4

P5.5/ADC5

P5.6/ADC6

P5.7/ADC7

P3.3/INT1

P2.0/A08

* Do not connect.

Philips Semiconductors

Product data

80C552/83C552

Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM

2002 Sep 03

Plastic Quad Flat Pack

P4.1/CMSR1

P4.2/CMSR2

NC*

P4.3/CMSR3

P4.4/CMSR4

P4.6/CMT0

P4.5/CMSR5

P4.7/CMT1

RST

P1.1/CT1I

P1.0/CT0I

PLASTIC QUAD FLAT PACK

SU00931

P1.2/CT2I

P1.3/CT3I

P1.4/T2

P1.5/RT2

P1.7/SDA

P1.6/SCL

P3.0/RxD

P3.1/TxD

NC*

P3.2/INT0

NC*

P3.3/INT1

PP3.4/T0

P3.5/T1

P3.6/WR

P3.7/RD

NC*

AL2

AL1

NC*

P2.0/A08

P2.1/A09

P2.2/A10

P5.7/ADC7

NC*

REF+

P0.0/AD0

REF

P0.1/AD1

P0.2/AD2

P0.4/AD4

P0.3/AD3

P0.5/AD5

P0.6/AD6

P0.7/AD7

PSEN

ALE

P2.7/A15

P2.6/A14

NC*

P2.5/A13

NC*

P2.4/A12

P2.3/A11

P4.0/SMSR0

NC*

PWM1

PWM0

ADC

P5.0/ADC0

P5.1/ADC1

P5.2/ADC2

P5.3/ADC3

P5.4/ADC4

P5.5/ADC5

P5.6/ADC6

* Do not connect.
IC = Internally connected (do not use).

Philips Semiconductors

Product data

80C552/83C552

Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM

2002 Sep 03

BLOCK DIAGRAM

SU01692

CPU

ADC

8-BIT INTERNAL BUS

TxD

RxD

CT0I-CT3I

RT2

CMSR0-CMSR5

CMT0, CMT1

RST

XTAL1

XTAL2

ALE

PSEN

INT0

INT1

VDD

VSS

PWM0

PWM1

REF

STADC

ADC0-7 SDA

SCL

ALTERNATE FUNCTION OF PORT 0

AD0-7

A8-15

T0, T1

TWO 16-BIT

TIMER/EVENT

COUNTERS

PROGRAM

MEMORY

8k x 8 ROM

DATA

MEMORY

256 x 8 RAM

DUAL

PWM

SERIAL

I2C PORT

80C51 CORE

EXCLUDING

ROM/RAM

PARALLEL I/O

PORTS AND

EXTERNAL BUS

SERIAL

UART
PORT

8-BIT

PORT

FOUR

16-BIT

CAPTURE

LATCHES

16-BIT

TIMER/
EVENT

COUNTERS

16-BIT

COMPARA-

TORS

wITH

REGISTERS

COMPARA-

TOR

OUTPUT

SELECTION

WATCHDOG

TIMER

ALTERNATE FUNCTION OF PORT 1

ALTERNATE FUNCTION OF PORT 2

ALTERNATE FUNCTION OF PORT 3

ALTERNATE FUNCTION OF PORT 4

ALTERNATE FUNCTION OF PORT 5

Philips Semiconductors

Product data

80C552/83C552

Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM

2002 Sep 03

ORDERING INFORMATION

PHILIPS

PART ORDER NUMBER

PART MARKING

DRAWING

NUMBER

TEMPERATURE (

AND PACKAGE

FREQ

(MHz)

ROMless

ROM

(

)

P80C552EBA

P83C552EBA/xxx

SOT188-2

0 to +70,

Plastic Leaded Chip Carrier

P80C552EBB

P83C552EBB/xxx

SOT318-2

0 to +70,

Plastic Quad Flat Pack

P80C552EFA

P83C552EFA/xxx

SOT188-2

40 to +85,

Plastic Leaded Chip Carrier

P80C552EFB

P83C552EFB/xxx

SOT318-2

40 to +85,

Plastic Quad Flat Pack

P80C552EHA

P83C552EHA/xxx

SOT188-2

40 to +125,

Plastic Leaded Chip Carrier

P80C552EHB

P83C552EHB/xxx

SOT318-2

40 to +125,

Plastic Quad Flat Pack

P80C552IBA

P83C552IBA/xxx

SOT188-2

0 to +70,

Plastic Leaded Chip Carrier

P80C552IBB

P83C552IBB/xxx

SOT318-2

0 to +70,

Plastic Quad Flat Pack

P80C552IFA

P83C552IFA/xxx

SOT188-2

40 to +85,

Plastic Leaded Chip Carrier

P80C552IFB

P83C552IFB/xxx

SOT318-2

40 to +85,

Plastic Quad Flat Pack

NOTE:
1. xxx denotes the ROM code number.
2. For EPROM device specification, refer to

87C552 datasheet.

Philips Semiconductors

Product data

80C552/83C552

Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM

2002 Sep 03

PIN DESCRIPTION

PIN NO.

MNEMONIC

PLCC

QFP

TYPE

NAME AND FUNCTION

Digital Power Supply: +5 V power supply pin during normal operation, idle and
power-down mode.

STADC

Start ADC Operation: Input starting analog to digital conversion (ADC operation can also
be started by software). This pin must not float.

PWM0

Pulse Width Modulation: Output 0.

PWM1

Pulse Width Modulation: Output 1.

Enable Watchdog Timer: Enable for T3 watchdog timer and disable power-down mode.
This pin must not float.

P0.0-P0.7

57-50

58-51

I/O

Port 0: Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written
to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory. In
this application it uses strong internal pull-ups when emitting 1s.

P1.0-P1.7

16-23

10-17

I/O

Port 1: 8-bit I/O port. Alternate functions include:

16-21

10-15

I/O

(P1.0-P1.5): Quasi-bidirectional port pins.

22-23

16-17

I/O

(P1.6, P1.7): Open drain port pins.

16-19

10-13

CT0I-CT3I (P1.0-P1.3): Capture timer input signals for timer T2.

T2 (P1.4): T2 event input.

RT2 (P1.5): T2 timer reset signal. Rising edge triggered.

I/O

SCL (P1.6): Serial port clock line I

C-bus.

I/O

SDA (P1.7): Serial port data line I

C-bus.

Port 1 is also used to input the lower order address byte during EPROM programming and
verification. A0 is on P1.0, etc.

P2.0-P2.7

39-46

38-42,

45-47

I/O

Port 2: 8-bit quasi-bidirectional I/O port.
Alternate function: High-order address byte for external memory (A08-A15).

P3.0-P3.7

24-31

18-20,

23-27

I/O

Port 3: 8-bit quasi-bidirectional I/O port. Alternate functions include:

RxD(P3.0): Serial input port.

TxD (P3.1): Serial output port.

INT0 (P3.2): External interrupt.

INT1 (P3.3): External interrupt.

T0 (P3.4): Timer 0 external input.

T1 (P3.5): Timer 1 external input.

WR (P3.6): External data memory write strobe.

RD (P3.7): External data memory read strobe.

P4.0-P4.7

7-14

80, 1-2

4-8

I/O

Port 4: 8-bit quasi-bidirectional I/O port. Alternate functions include:

7-12

80, 1-2

4-6

CMSR0-CMSR5 (P4.0-P4.5): Timer T2 compare and set/reset outputs on a match with
timer T2.

13, 14

7, 8

CMT0, CMT1 (P4.6, P4.7): Timer T2 compare and toggle outputs on a match with timer T2.

P5.0-P5.7

68-62,

71-64,

Port 5: 8-bit input port.

ADC0-ADC7 (P5.0-P5.7): Alternate function: Eight input channels to ADC.

RST

I/O

Reset: Input to reset the 8XC552. It also provides a reset pulse as output when timer T3
overflows.

XTAL1

Crystal Input 1: Input to the inverting amplifier that forms the oscillator, and input to the
internal clock generator. Receives the external clock signal when an external oscillator is
used.

XTAL2

Crystal Input 2: Output of the inverting amplifier that forms the oscillator. Left open-circuit
when an external clock is used.

Philips Semiconductors

Product data

80C552/83C552

Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM

2002 Sep 03

PIN DESCRIPTION (Continued)

PIN NO.

MNEMONIC

PLCC

QFP

TYPE

NAME AND FUNCTION

36, 37

34-36

Two Digital ground pins.

PSEN

Program Store Enable: Active-low read strobe to external program memory.

ALE

Address Latch Enable: Latches the low byte of the address during accesses to external
memory. It is activated every six oscillator periods. During an external data memory
access, one ALE pulse is skipped. ALE can drive up to eight LS TTL inputs and handles
CMOS inputs without an external pull-up.

External Access: When EA is held at TTL level high, the CPU executes out of the internal
program ROM provided the program counter is less than 8192. When EA is held at TTL
low level, the CPU executes out of external program memory. EA is not allowed to float.

REF

Analog to Digital Conversion Reference Resistor: Low-end.

REF+

Analog to Digital Conversion Reference Resistor: High-end.

Analog Ground

Analog Power Supply

NOTE:
1. To avoid "latch-up" effect at power-on, the voltage on any pin at any time must not be higher or lower than V

+ 0.5 V or V

0.5 V,

respectively.

OSCILLATOR CHARACTERISTICS

XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator, as shown in the logic symbol, page 2.

To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.

RESET

A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-on reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-on, the voltage on
V

and RST must come up at the same time for a proper start-up.

IDLE MODE

In the idle mode, the CPU puts itself to sleep while some of the
on-chip peripherals stay active. The instruction to invoke the idle
mode is the last instruction executed in the normal operating mode
before the idle mode is activated. The CPU contents, the on-chip
RAM, and all of the special function registers remain intact during
this mode. The idle mode can be terminated either by any enabled
interrupt (at which time the process is picked up at the interrupt

service routine and continued), or by a hardware reset which starts
the processor in the same manner as a power-on reset.

POWER-DOWN MODE

In the power-down mode, the oscillator is stopped and the
instruction to invoke power-down is the last instruction executed.
Only the contents of the on-chip RAM are preserved. A hardware

reset is the only way to terminate the power-down mode. The control

bits for the reduced power modes are in the special function register
PCON. Table 1 shows the state of the I/O ports during low current
operating modes.

ROM CODE PROTECTION (83C552)

The 83C552 has an additional security feature. ROM code
protection may be selected by setting a maskprogrammable
security bit (i.e., user dependent). This feature may be requested
during ROM code submission. When selected, the ROM code is
protected and cannot be read out at any time by any test mode or by
any instruction in the external program memory space.

The MOVC instructions are the only instructions that have access to
program code in the internal or external program memory. The EA
input is latched during RESET and is "don't care" after RESET
(also if the security bit is not set). This implementation prevents
reading internal program code by switching from external program
memory to internal program memory during a MOVC instruction or
any other instruction that uses immediate data.

Table 1. External Pin Status During Idle and Power-Down Modes

MODE

PROGRAM

MEMORY

ALE

PSEN

PORT 0

PORT 1

PORT 2

PORT 3

PORT 4

PWM0/

PWM1

Idle

Internal

Data

Idle

External

Float

Data

Address

Data

Power-down

Internal

Data

Power-down

External

Float

Data

Philips Semiconductors

Product data

80C552/83C552

Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM

2002 Sep 03

Serial Control Register (S1CON) See Table 2

CR2

ENS1

STA

STO

CR1

CR0

S1CON (D8H)

Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation.

Table 2. Serial Clock Rates

BIT FREQUENCY (kHz) AT f

OSC

CR2

CR1

CR0

6 MHZ

12 MHz

16 MHz

24 MHz

OSC

DIVIDED BY

62.5

256

107

224

83.3

125

192

100

150

160

6.25

12.5

960

100

133

200

120

100

200

267

400

0.24 < 62.5

0.49 < 62.5

0.65 < 55.6

0.98 < 50.0

(256 (reload value Timer 1))

0 < 255

0 < 254

0 < 253

0 <251

reload value Timer 1 in Mode 2.

NOTES:
1. These frequencies exceed the upper limit of 100kHz of the I

C-bus specification and cannot be used in an I

C-bus application.

2. At f

OSC

= 24 MHz the maximum I

C bus rate of 100kHz cannot be realized due to the fixed divider rates.

ABSOLUTE MAXIMUM RATINGS

1, 2, 3

PARAMETER

RATING

UNIT

Storage temperature range

65 to +150

Voltage on any other pin to V

0.5 to +6.5

Input, output DC current on any single I/O pin

5.0

Power dissipation
(based on package heat transfer limitations, not device power consumption)

1.0

NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.

3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V

unless otherwise

noted.

DEVICE SPECIFICATIONS

SUPPLY VOLTAGE (V)

FREQUENCY (MHz)

TYPE

MIN

MAX

MIN

MAX

TEMPERATURE RANGE (

P83(0)C552EBx

4.5

5.5

3.5

0 to +70

P83(0)C552EFx

4.5

5.5

3.5

40 to +85

P83(0)C552EHx

4.5

5.5

3.5

40 to +125

P83(0)C552IBx

4.5

5.5

3.5

0 to +70

P83(0)C552IFx

4.5

5.5

3.5

40 to +85

Philips Semiconductors

Product data

80C552/83C552

Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM

2002 Sep 03

DC ELECTRICAL CHARACTERISTICS

, AV

= 0 V; V

, AV

= 5 V

10%

TEST

LIMITS

SYMBOL

PARAMETER

CONDITIONS

MIN

MAX

UNIT

Supply current operating:

See notes 1 and 2

P83(0)C552EBx

OSC

= 16 MHz

P83(0)C552EFx

OSC

= 16 MHz

P83(0)C552EHx

OSC

= 16 MHz

P83(0)C552IBx

OSC

= 24 MHz

P83(0)C552IFx

OSC

= 24 MHz

Idle mode:

See notes 1 and 3

P83(0)C552EBx

OSC

= 16 MHz

P83(0)C552EFx

OSC

= 16 MHz

P83(0)C552EHx

OSC

= 16 MHz

P83(0)C552IBx

OSC

= 24 MHz

12.5

P83(0)C552IFx

OSC

= 24 MHz

12.5

Power-down current:

See notes 1 and 4;

2 V < V

< V

max

P83(0)C552xBx

P83(0)C552xFx

P83(0)C552xHx

150

Inputs

Input low voltage, except EA, P1.6, P1.7

0.5

0.2V

0.1

IL1

Input low voltage to EA

0.5

0.2V

0.3

IL2

Input low voltage to P1.6/SCL, P1.7/SDA

0.5

0.3V

Input high voltage, except XTAL1, RST, P1.6/SCL, P1.7/SDA

0.2V

+0.9

+0.5

IH1

Input high voltage, XTAL1, RST

0.7V

+0.5

IH2

Input high voltage, P1.6/SCL, P1.7/SDA

0.7V

6.0

Logical 0 input current, ports 1, 2, 3, 4, except P1.6, P1.7

= 0.45 V

Logical 1-to-0 transition current, ports 1, 2, 3, 4, except P1.6, P1.7

See note 6

650

IL1

Input leakage current, port 0, EA, STADC, EW

0.45 V < V

< V

IL2

Input leakage current, P1.6/SCL, P1.7/SDA

0 V < V

< 6 V

0 V < V

< 5.5 V

IL3

Input leakage current, port 5

0.45 V < V

< V

Outputs

Output low voltage, ports 1, 2, 3, 4, except P1.6, P1.7

= 1.6mA

0.45

OL1

Output low voltage, port 0, ALE, PSEN, PWM0, PWM1

= 3.2mA

0.45

OL2

Output low voltage, P1.6/SCL, P1.7/SDA

= 3.0mA

0.4

Output high voltage, ports 1, 2, 3, 4, except P1.6/SCL, P1.7/SDA

= 60

2.4

= 25

0.75V

= 10

0.9V

OH1

Output high voltage (port 0 in external bus mode, ALE,
PSEN PWM0 PWM1)

= 400

2.4

PSEN, PWM0, PWM1)

= 150

0.75V

= 40

0.9V

OH2

Output high voltage (RST)

= 400

2.4

= 120

0.8V

RST

Internal reset pull-down resistor

150

Pin capacitance

Test freq = 1 MHz,

amb

= 25

Philips Semiconductors

Product data

80C552/83C552

Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM

2002 Sep 03

DC ELECTRICAL CHARACTERISTICS (Continued)

TEST

LIMITS

SYMBOL

PARAMETER

CONDITIONS

MIN

MAX

UNIT

Analog Inputs

Analog supply current: operating: (16 MHz)

Port 5 = 0 to AV

1.2

Analog supply current: operating: (24 MHz)

Port 5 = 0 to AV

1.0

Idle mode:

P83(0)C552EBx

P83(0)C552EFx

P83(0)C552EHx

100

P83(0)C552IBx

P83(0)C552IFx

Power-down mode:

2 V < AV

< AV

max

P83(0)C552xBx

P83(0)C552xFx

P83(0)C552xHx

100

Analog input voltage

0.2

+0.2

REF

Reference voltage:

REF

0.2

REF+

+0.2

REF

Resistance between AV

REF+

and AV

REF

Analog input capacitance

ADS

Sampling time

ADC

Conversion time (including sampling time)

50t

Differential non-linearity

10, 11, 12

LSB

Integral non-linearity

10, 13

LSB

Offset error

10, 14

LSB

Gain error

10, 15

0.4

Absolute voltage error

10, 16

LSB

CTC

Channel to channel matching

LSB

Crosstalk

between inputs of port 5

0100kHz

NOTES FOR DC ELECTRICAL CHARACTERISTICS:
1. See Figures 10 through 15 for I

test conditions.

2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t

= t

= 10 ns; V

= V

+ 0.5 V;

= V

0.5 V; XTAL2 not connected; EA = RST = Port 0 = EW = V

; STADC = V

3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t

= t

= 10 ns; V

= V

+ 0.5 V;

= V

0.5 V; XTAL2 not connected; Port 0 = EW = V

; EA = RST = STADC = V

4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = EW = V

;

EA = RST = STADC = XTAL1 = V

5. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I

C specification, so an input voltage below 1.5 V will be recognized as a

logic 0 while an input voltage above 3.0 V will be recognized as a logic 1.

6. Pins of ports 1 (except P1.6, P1.7), 2, 3, and 4 source a transition current when they are being externally driven from 1 to 0. The transition

current reaches its maximum value when V

is approximately 2 V.

7. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V

s of ALE and ports 1 and 3. The noise is due

to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I

can exceed these conditions provided that no

single output sinks more than 5mA and no more than two outputs exceed the test conditions.

8. Capacitive loading on ports 0 and 2 may cause the V

on ALE and PSEN to momentarily fall below the 0.9 V

specification when the

address bits are stabilizing.

9. The following condition must not be exceeded: V

0.2 V < AV

< V

+ 0.2 V.

10. Conditions: AV

REF

= 0 V; AV

= 5.0 V, AV

REF+

(80C552, 83C552) = 5.12 V. ADC is monotonic with no missing codes. Measurement by

continuous conversion of AV

= 20 mV to 5.12 V in steps of 0.5 mV.

11. The differential non-linearity (DL

) is the difference between the actual step width and the ideal step width. (See Figure 1.)

12. The ADC is monotonic; there are no missing codes.
13. The integral non-linearity (IL

) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset error. (See Figure 1.)

Philips Semiconductors

Product data

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Single-chip 8-bit microcontroller with 10-bit A/D,
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2002 Sep 03

14. The offset error (OS

) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and

a straight line which fits the ideal transfer curve. (See Figure 1.)

15. The gain error (G

) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error),

and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. (See Figure 1.)

16. The absolute voltage error (A

) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated

ADC and the ideal transfer curve.

17. This should be considered when both analog and digital signals are simultaneously input to port 5.

SU01693

1018

1019

1020

1021

1022

1023

1018

1019

1020

1021

1022

1023

1024

Code
Out

(2)

(1)

(5)

(4)

(3)

1 LSB
(ideal)

Offset
error
OSe

Gain
error
Ge

AVIN (LSBideal)

1 LSB =

AVREF+

AVREF

1024

(1)

Example of an actual transfer curve.

(2)

The ideal transfer curve.

(3)

Differential non-linearity (DLe).

(4)

Integral non-linearity (ILe).

(5)

Center of a step of the actual transfer curve.

Figure 1. ADC Conversion Characteristic

Philips Semiconductors

Product data

80C552/83C552

Single-chip 8-bit microcontroller with 10-bit A/D,
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2002 Sep 03

AC ELECTRICAL CHARACTERISTICS

1, 2

16 MHz version

16 MHz CLOCK

VARIABLE CLOCK

SYMBOL

FIGURE

PARAMETER

MIN

MAX

MIN

MAX

UNIT

1/t

CLCL

Oscillator frequency

3.5

MHz

LHLL

ALE pulse width

CLCL

AVLL

Address valid to ALE low

CLCL

LLAX

Address hold after ALE low

CLCL

LLIV

ALE low to valid instruction in

150

CLCL

100

LLPL

ALE low to PSEN low

CLCL

PLPH

PSEN pulse width

143

CLCL

PLIV

PSEN low to valid instruction in

CLCL

105

PXIX

Input instruction hold after PSEN

PXIZ

Input instruction float after PSEN

CLCL

AVIV

Address to valid instruction in

208

CLCL

105

PLAZ

PSEN low to address float

Data Memory

RLRH

RD pulse width

275

CLCL

100

WLWH

WR pulse width

275

CLCL

100

RLDV

RD low to valid data in

148

CLCL

165

RHDX

Data hold after RD

RHDZ

Data float after RD

CLCL

LLDV

ALE low to valid data in

350

CLCL

150

AVDV

Address to valid data in

398

CLCL

165

LLWL

3, 4

ALE low to RD or WR low

138

238

CLCL

+50

AVWL

3, 4

Address valid to WR low or RD low

120

CLCL

130

QVWX

Data valid to WR transition

CLCL

Data before WR

288

CLCL

150

WHQX

Data hold after WR

CLCL

RLAZ

RD low to address float

WHLH

3, 4

RD or WR high to ALE high

103

CLCL

+40

External Clock

CHCX

High time

CLCX

Low time

CLCH

Rise time

CHCL

Fall time

Serial Timing Shift Register Mode

(Test Conditions: T

amb

= 0

C to +70

C; V

= 0 V; Load Capacitance = 80 pF)

XLXL

Serial port clock cycle time

0.75

12t

CLCL

QVXH

Output data setup to clock rising edge

492

10t

CLCL

133

XHQX

Output data hold after clock rising edge

CLCL

117

XHDX

Input data hold after clock rising edge

XHDV

Clock rising edge to input data valid

492

10t

CLCL

133

NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
3. t

CLCL

= 1/f

OSC

= one oscillator clock period.

CLCL

= 83.3ns at f

OSC

= 12 MHz.

CLCL

= 62.5ns at f

OSC

= 16 MHz.

4. These values are characterized but not 100% production tested.

Philips Semiconductors

Product data

80C552/83C552

Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM

2002 Sep 03

AC ELECTRICAL CHARACTERISTICS (Continued)

1, 2

24 MHz version

24 MHz CLOCK

VARIABLE CLOCK

SYMBOL

FIGURE

PARAMETER

MIN

MAX

MIN

MAX

UNIT

1/t

CLCL

Oscillator frequency

3.5

MHz

LHLL

ALE pulse width

CLCL

AVLL

Address valid to ALE low

CLCL

LLAX

Address hold after ALE low

CLCL

LLIV

ALE low to valid instruction in

102

CLCL

LLPL

ALE low to PSEN low

CLCL

PLPH

PSEN pulse width

CLCL

PLIV

PSEN low to valid instruction in

CLCL

PXIX

Input instruction hold after PSEN

PXIZ

Input instruction float after PSEN

CLCL

AVIV

Address to valid instruction in

128

CLCL

PLAZ

PSEN low to address float

Data Memory

RLRH

RD pulse width

150

CLCL

100

WLWH

WR pulse width

150

CLCL

100

RLDV

RD low to valid data in

118

CLCL

RHDX

Data hold after RD

RHDZ

Data float after RDxs

CLCL

LLDV

ALE low to valid data in

183

CLCL

150

AVDV

Address to valid data in

210

CLCL

165

LLWL

3, 4

ALE low to RD or WR low

175

CLCL

+50

AVWL

3, 4

Address valid to WR low or RD low

CLCL

QVWX

Data valid to WR transition

CLCL

Data before WR

162

CLCL

130

WHQX

Data hold after WR

CLCL

RLAZ

RD low to address float

WHLH

3, 4

RD or WR high to ALE high

CLCL

+25

External Clock

CHCX

High time

CLCX

Low time

CLCH

Rise time

CHCL

Fall time

Serial Timing Shift Register Mode

(Test Conditions: T

amb

= 0

C to +70

C; V

= 0 V; Load Capacitance = 80 pF)

XLXL

Serial port clock cycle time

0.5

12t

CLCL

QVXH

Output data setup to clock rising edge

283

10t

CLCL

133

XHQX

Output data hold after clock rising edge

CLCL

XHDX

Input data hold after clock rising edge

XHDV

Clock rising edge to input data valid

283

10t

CLCL

133

CLCL

= 1/f

OSC

= one oscillator clock period.

CLCL

= 41.7ns at f

OSC

= 24 MHz.

Philips Semiconductors

Product data

80C552/83C552

Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM

2002 Sep 03

AC ELECTRICAL CHARACTERISTICS (Continued)

SYMBOL

PARAMETER

INPUT

OUTPUT

C Interface (Refer to Figure 9)

HD;STA

START condition hold time

14 t

CLCL

> 4.0

LOW

SCL low time

16 t

CLCL

> 4.7

HIGH

SCL high time

14 t

CLCL

> 4.0

SCL rise time

SCL fall time

0.3

< 0.3

SU;DAT1

Data set-up time

250ns

> 20 t

CLCL

SU;DAT2

SDA set-up time (before rep. START cond.)

250ns

> 1

SU;DAT3

SDA set-up time (before STOP cond.)

250ns

> 8 t

CLCL

HD;DAT

Data hold time

0ns

> 8 t

CLCL

SU;STA

Repeated START set-up time

14 t

CLCL

> 4.7

SU;STO

STOP condition set-up time

14 t

CLCL

> 4.0

BUF

Bus free time

14 t

CLCL

> 4.7

SDA rise time

SDA fall time

0.3

< 0.3

NOTES:
1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1

3. Spikes on the SDA and SCL lines with a duration of less than 3 t

CLCL

will be filtered out. Maximum capacitance on bus-lines SDA and

SCL = 400 pF.

4. t

CLCL

= 1/f

OSC

= one oscillator clock period at pin XTAL1. For 62 ns, 42 ns < t

CLCL

< 285 ns (16 MHz, 24 MHz > f

OSC

> 3.5 MHz) the SI01

interface meets the I

C-bus specification for bit-rates up to 100 kbit/s.

Philips Semiconductors

Product data

80C552/83C552

Single-chip 8-bit microcontroller with 10-bit A/D,
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2002 Sep 03

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has five characters. The first character is always
`t' (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal. The
designations are:
A Address
C Clock
D Input data
H Logic level high
I Instruction (program memory contents)
L Logic level low, or ALE
P PSEN

Q Output data
R RD signal
t Time
V Valid
W WR signal
X No longer a valid logic level
Z Float
Examples: t

AVLL

= Time for address valid to

ALE low.

LLPL

= Time for ALE low to

PSEN low.

SU01694

PXIZ

ALE

PSEN

PORT 0

PORT 2

A8A15

A0A7

AVLL

PXIX

LLAX

INSTR IN

PLIV

LHLL

PLPH

LLIV

PLAZ

LLPL

AVIV

Figure 2. External Program Memory Read Cycle

SU01695

ALE

PSEN

PORT 0

PORT 2

A0A7

FROM RI OR DPL

DATA IN

A0A7 FROM PCL

INSTR IN

P2.0P2.7 OR A8A15 FROM DPH

A8A15 FROM PCH

WHLH

LLDV

LLWL

RLRH

LLAX

RLAZ

AVLL

RHDX

RHDZ

AVWL

AVDV

RLDV

Figure 3. External Data Memory Read Cycle

Philips Semiconductors

Product data

80C552/83C552

Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM

2002 Sep 03

SU01699

VDD0.5

0.45 V

0.2 VDD+0.9

0.2 VDD0.1

NOTE:

AC INPUTS DURING TESTING ARE DRIVEN AT VDD0.5 FOR A LOGIC `1' AND
0.45 V FOR A LOGIC `0'. TIMING MEASUREMENTS ARE MADE AT VIH MIN FOR A
LOGIC `1' AND VIL MAX FOR A LOGIC `0'.

Figure 7. AC Testing Input/Output

SU01700

VLOAD

VLOAD+0.1 V

VLOAD0.1 V

VOH0.1 V

VOL+0.1 V

NOTE:
FOR TIMING PURPOSES, A PORT IS NO LONGER FLOATING WHEN A 100MV
CHANGE FROM LOAD VOLTAGE OCCURS, AND BEGINS TO FLOAT WHEN A
100 mV CHANGE FROM THE LOADED VOH/VOL LEVEL OCCURS. IOH/IOL

> +

20mA.

TIMING

REFERENCE

POINTS

Figure 8. Float Waveform

SU01701

tRD

tSU;STA

tBUF

tSU;STO

0.7 VCC

0.3 VCC

0.7 VCC

0.3 VCC

tFD

tRC

tFC

tHIGH

tLOW

tHD;STA

tSU;DAT1

tHD;DAT

tSU;DAT2

tSU;DAT3

START condition

repeated START condition

SDA
(INPUT/OUTPUT)

SCL
(INPUT/OUTPUT)

STOP condition

START or repeated START condition

Figure 9. Timing SIO1 (I

C) Interface

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Product data

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Single-chip 8-bit microcontroller with 10-bit A/D,
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2002 Sep 03

SU01702

f (MHz)

(1)

NOTE:
These values are valid only within the frequency specifications of the device under test.

IDD

, I

D mA

(2)

(3)

(4)

(1)

Maximum operating mode; VDD = 6 V

(2)

Maximum operating mode; VDD = 4 V

(3)

Maximum idle mode; VDD = 6 V

(4)

Maximum idle mode; VDD = 4 V

Figure 10. 16 MHz Version Supply Current (I

) as a Function of Frequency at XTAL1 (f

OSC)

SU01703

f (MHz)

(1)

NOTE:
These values are valid only within the frequency specifications of the device under test.

(2)

(3)

(4)

(1)

Maximum operating mode; VDD =

5.5 V

(2)

Maximum operating mode; VDD =

4.5 V

(3)

Maximum idle mode; VDD = 5.5 V

(4)

Maximum idle mode; VDD = 4.5 V

IDD

, I

D mA

Figure 11. 24 MHz Version Supply Current (I

) as a Function of Frequency at XTAL1 (f

OSC)

Philips Semiconductors

Product data

80C552/83C552

Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM

2002 Sep 03

SU01704

VDD

RST

XTAL1

XTAL2

VSS

VDD

IDD

(NC)

CLOCK SIGNAL

VDD

P1.6
P1.7

STADC

AVSS

AVref

Figure 12. I

Test Condition, Active Mode

All other pins are disconnected

SU01705

VDD

RST

XTAL1

XTAL2

VSS

VDD

IDD

(NC)

CLOCK SIGNAL

VDD

P1.6
P1.7

STADC

AVSS

AVref

Figure 13. I

Test Condition, Idle Mode

All other pins are disconnected

SU01706

VDD0.5

0.5 V

0.7VDD

0.2VDD0.1

CHCL

CLCL

CLCH

CLCX

CHCX

Figure 14. Clock Signal Waveform for I

Tests in Active and

Idle Modes t

CLCH

= t

CHCL

= 5ns

SU01707

VDD

RST

XTAL1

XTAL2

VSS

VDD

IDD

(NC)

VDD

P1.6
P1.7

STADC

AVSS

AVref

Figure 15. I

Test Condition, Power Down Mode

All other pins are disconnected. V

= 2 V to 5.5 V

NOTES:
1. Active Mode:

a. The following pins must be forced to V

: EA, RST, Port 0, and EW.

b. The following pins must be forced to V

: STADC, AV

, and AV

ref

c. Ports 1.6 and 1.7 should be connected to V

through resistors of sufficiently high value such that the sink current into these pins cannot

exceed the I

OL1

spec of these pins.

d. The following pins must be disconnected: XTAL2 and all pins not specified above.

2. Idle Mode:

a. The following pins must be forced to V

: Port 0 and EW.

b. The following pins must be forced to V

: RST, STADC, AV

,, AV

ref

, and EA.

c. Ports 1.6 and 1.7 should be connected to V

through resistors of sufficiently high value such that the sink current into these pins cannot

exceed the I

OL1

spec of these pins. These pins must not have logic 0 written to them prior to this measurement.

d. The following pins must be disconnected: XTAL2 and all pins not specified above.

3. Power Down Mode:

a. The following pins must be forced to V

: Port 0 and EW.

b. The following pins must be forced to V

: RST, STADC, XTAL1, AV

,, AV

ref

, and EA.

c. Ports 1.6 and 1.7 should be connected to V

through resistors of sufficiently high value such that the sink current into these pins cannot

exceed the I

OL1

spec of these pins. These pins must not have logic 0 written to them prior to this measurement.

d. The following pins must be disconnected: XTAL2 and all pins not specified above.

Philips Semiconductors

Product data

80C552/83C552

Single-chip 8-bit microcontroller with 10-bit A/D,
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2002 Sep 03

Purchase of Philips I

C components conveys a license under the Philips' I

C patent

to use the components in the I

C system provided the system conforms to the

C specifications defined by Philips. This specification can be ordered using the

code 9398 393 40011.

Definitions

Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Contact information

For additional information please visit
http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.

Koninklijke Philips Electronics N.V. 2002

Date of release: 09-02

Document order number:

9397 750 10294

Philips

Semiconductors

Data sheet status

[1]

Objective data

Preliminary data

Product data

Product
status

[2]

Development

Qualification

Production

Definitions

This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.

This data sheet contains data from the preliminary specification. Supplementary data will be
published at a later date. Philips Semiconductors reserves the right to change the specification
without notice, in order to improve the design and supply the best possible product.

This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply.
Changes will be communicated according to the Customer Product/Process Change Notification
(CPCN) procedure SNW-SQ-650A.

Data sheet status

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

http://www.semiconductors.philips.com.

Document Outline

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Document Outline

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