Document Outline

CONTENTS
1 FEATURES
2 GENERAL DESCRIPTION
- 2.1 Versions: P80CL31 and P80C51
3 APPLICATIONS
4 ORDERING INFORMATION
5 BLOCK DIAGRAM
6 FUNCTIONAL DIAGRAM
7 PINNING INFORMATION
- 7.1 Pinning
- 7.2 Pin description
8 FUNCTIONAL DESCRIPTION OVERVIEW
- 8.1 General
- 8.2 CPU timing
9 MEMORY ORGANIZATION
- 9.1 Program Memory
- 9.2 Data Memory
- 9.3 Special Function Registers (SFRs)
- 9.4 Addressing
10 I/O FACILITIES
- 10.1 Ports
- 10.2 Port options
- 10.3 Port 0 options
- 10.4 SET/RESET options
11 TIMERS/EVENT COUNTERS
12 REDUCED POWER MODES
- 12.1 Idle mode
- 12.2 Power-down mode
- 12.3 Wake-up from Power-down mode
- 12.4 Power Control Register (PCON)
- 12.5 Status of external pins
13 STANDARD SERIAL INTERFACE SIO0: UART
- 13.1 Multiprocessor communications
- 13.2 Serial Port Control and Status Register (S0CON)
- 13.3 Baud rates
14 INTERRUPT SYSTEM
- 14.1 External interrupts INT2 to INT9
- 14.2 Interrupt priority
- 14.3 Interrupt registers
15 OSCILLATOR CIRCUITRY
16 RESET
- 16.1 External reset using the RST pin
- 16.2 Power-on-reset
17 MASK OPTIONS FOR P80CL31 AND P80C51
- 17.1 P80CL31: ROMless version
- 17.2 P80C51: 5 V standard version
18 SPECIAL FUNCTION REGISTERS OVERVIEW
19 INSTRUCTION SET
20 LIMITING VALUES
21 DC CHARACTERISTICS FOR P80CL31 AND P80CL51
22 DC CHARACTERISTICS FOR P80C51
23 AC CHARACTERISTICS
24 P85CL000HFZ PIGGY-BACK SPECIFICATION
- 24.1 General description
- 24.2 Feature differences/additional features with respect to P80CL51
- 24.3 Common specification/feature differences between P85CL000HFZ and P83CL410/P80CL51
25 PACKAGE OUTLINES
- SOT129-1
- SOT158-1
- SOT307-2
26 SOLDERING
- 26.2 DIP
- 26.3 QFP and VSO
27 DEFINITIONS
28 LIFE SUPPORT APPLICATIONS

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

CONTENTS

FEATURES

GENERAL DESCRIPTION

2.1

Versions: P80CL31 and P80C51

APPLICATIONS

ORDERING INFORMATION

BLOCK DIAGRAM

FUNCTIONAL DIAGRAM

PINNING INFORMATION

7.1

Pinning

7.2

Pin description

FUNCTIONAL DESCRIPTION OVERVIEW

8.1

General

8.2

CPU timing

MEMORY ORGANIZATION

9.1

Program Memory

9.2

Data Memory

9.3

Special Function Registers (SFRs)

9.4

Addressing

I/O FACILITIES

10.1

Ports

10.2

Port options

10.3

Port 0 options

10.4

SET/RESET options

TIMERS/EVENT COUNTERS

REDUCED POWER MODES

12.1

Idle mode

12.2

Power-down mode

12.3

Wake-up from Power-down mode

12.4

Power Control Register (PCON)

12.5

Status of external pins

STANDARD SERIAL INTERFACE SIO0:
UART

13.1

Multiprocessor communications

13.2

Serial Port Control and Status Register
(S0CON)

13.3

Baud rates

INTERRUPT SYSTEM

14.1

External interrupts INT2 to INT9

14.2

Interrupt priority

14.3

Interrupt registers

OSCILLATOR CIRCUITRY

RESET

16.1

External reset using the RST pin

16.2

Power-on-reset

MASK OPTIONS FOR P80CL31 AND P80C51

17.1

P80CL31: ROMless version

17.2

P80C51: 5V standard version

SPECIAL FUNCTION REGISTERS
OVERVIEW

INSTRUCTION SET

LIMITING VALUES

DC CHARACTERISTICS FOR P80CL31 AND
P80CL51

DC CHARACTERISTICS FOR P80C51

AC CHARACTERISTICS

P85CL000HFZ `PIGGY-BACK'
SPECIFICATION

24.1

General description

24.2

Feature differences/additional features with
respect to P80CL51

24.3

Common specification/feature differences
between P85CL000HFZ and
P83CL410/P80CL51

PACKAGE OUTLINES

SOLDERING

26.1

Introduction

26.2

DIP

26.3

QFP and VSO

DEFINITIONS

LIFE SUPPORT APPLICATIONS

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

FEATURES

Full static 80C51 Central Processing Unit

8-bit CPU, ROM, RAM, I/O in a 40-lead DIP,
40-lead VSO or 44-lead QFP package

128 bytes on-chip RAM Data Memory

4 kbytes on-chip ROM Program Memory for P80CL51

External memory expandable up to 128 kbytes: RAM up
to 64 kbytes and ROM up to 64 kbytes

Four 8-bit ports; 32 I/O lines

Two 16-bit Timer/Event counters

On-chip oscillator suitable for RC, LC, quartz crystal or
ceramic resonator

Thirteen source, thirteen vector, nested interrupt
structure with two priority levels

Full duplex serial port (UART)

Enhanced architecture with:

non-page oriented instructions

direct addressing

four 8-byte RAM register banks

stack depth limited only by available internal RAM

(maximum 128 bytes)

multiply, divide, subtract and compare instructions

Reduced power consumption through Power-down and
Idle modes

Wake-up via external interrupts at Port 1

Frequency range: 0 to 16 MHz (P80C51: 3.5 MHz min.)

Supply voltage: 1.8 to 6.0 V (P80C51: 5.0 V

10%)

Very low current consumption

Operating ambient temperature range:

40 to +85

GENERAL DESCRIPTION

The P80CL31; P80CL51 (hereafter generally referred to
as the P80CLx1) is manufactured in an advanced CMOS
technology. The P80CLx1 has the same instruction set as
the 80C51, consisting of over 100 instructions:
49 one-byte, 46 two-byte, and 16 three-byte. The device
operates over a wide range of supply voltages and has low
power consumption; there are two software selectable
modes for power reduction: Idle and Power-down.
For emulation purposes, the P85CL000 (piggy-back
version) with 256 bytes of RAM is recommended.

This data sheet details the specific properties of the
P80CL31; P80CL51. For details of the 80C51 core see
"Data Handbook IC20".

2.1

Versions: P80CL31 and P80C51

The P80CL31 is the ROMless version of the P80CL51.
The mask options on the P80CL31 are fixed as follows:

All ports have option `1S' (standard, HIGH after reset)

Oscillator option: Oscillator 3

Power-on-reset option: OFF.

The P80C51 is a restricted-voltage range version of the
P80CL51. The operating voltage is 5.0 V

10%.

APPLICATIONS

The P80CLx1 is especially suited for real-time applications
such as instrumentation, industrial control, intelligent
computer peripherals and consumer products.
The P80CLx1 also functions as an arithmetic processor
having facilities for both binary and BCD arithmetic plus
bit-handling capabilities.

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

7.2

Pin description

Table 1

Pin description for DIP40 (SOT190-1), VSO40 (SOT319-2) and QFP44 (SOT307-2) packages

For more extensive description of the port pins see Chapter 10 "I/O facilities".

SYMBOL

PIN

DESCRIPTION

DIP40

VSO40

QFP44

P1.0/INT2

Port 1: 8-bit bidirectional I/O port (P1.0 to P1.7). Port pins that have
logic 1s written to them are pulled HIGH by internal pull-ups, and in this
state can be used as inputs. As inputs, Port 1 pins that are externally
pulled LOW will source current (I

, see Chapter 21) due to the internal

pull-ups. Port 1 output buffers can sink/source 4 LS TTL loads.

Alternative functions:

INT2 to INT9 are external interrupt inputs.

P1.1/INT3

P1.2/INT4

P1.3/INT5

P1.4/INT6

P1.5/INT7

P1.6/INT8

P1.7/INT9

RST

Reset: a HIGH level on this pin for two machine cycles while the oscillator
is running resets the device.

P3.0/RXD/data

Port 3: 8-bit bidirectional I/O port (P3.0 to P3.7).
Same characteristics as Port 1.

Alternative functions:

RXD/data is the serial port receiver data input (asynchronous) or data

input/output (synchronous)

TXD/clock is the serial port receiver data output (asynchronous) or

clock output (synchronous)

INT0 and INT1 are external interrupts 0 and 1

T0 and T1 are external inputs for timers 0 and 1

WR is the external Data Memory write strobe

RD is the external Data Memory read strobe.

P3.1/TXD/clock

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

P3.6/WR

P3.7/RD

XTAL2

Crystal oscillator output: output of the inverting amplifier of the oscillator.
Left open when external clock is used.

XTAL1

Crystal oscillator input: input to the inverting amplifier of the oscillator,
also the input for an externally generated clock source.

Ground: circuit ground potential.

P2.0 to P2.7
A8 to A15

21 to 28

18 to 25

Port 2: 8-bit bidirectional I/O port (P2.0 to P2.7) with internal pull-ups.
Same characteristics as Port 1.

High-order addressing: Port 2 emits the high-order address byte
(A8 to A15) during accesses to external memory that use 16-bit
addresses (MOVX @DPTR). In this application it uses the strong internal
pull-ups when emitting logic 1s. During accesses to external memory that
use 8-bit addresses (MOVX @Ri), Port 2 emits the contents of the P2
Special Function Register.

PSEN

Program Store Enable. Output read strobe to external Program Memory.
When executing code out of external Program Memory, PSEN is activated
twice each machine cycle. However, during each access to external Data
Memory two PSEN activations are skipped.

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

ALE

Address Latch Enable. Output pulse for latching the low byte of the
address during access to external memory. ALE is emitted at a constant
rate of

osc

, and may be used for external timing or clocking purposes

(assuming MOVX instructions are not used).

External Access. When EA is held HIGH the CPU executes out of internal
program memory (unless the program counter exceeds 0FFFH). Holding
EA LOW forces the CPU to execute out of external memory regardless of
the value of the program counter.

P0.7 to P0.0
AD7 to AD0

32 to 39

30 to 37

Port 0: 8-bit open-drain bidirectional I/O port. As an open-drain output
port it can sink 8 LS TTL loads. Port 0 pins that have logic 1s written to
them float, and in that state will function as high impedance inputs.

Low-order addressing: Port 0 is also the multiplexed low-order address
and data bus during access to external memory. The strong internal
pull-ups are used while emitting logic 1s within the low order address.

Power supply.

n.c.

6, 17, 28,

Not connected.

SYMBOL

PIN

DESCRIPTION

DIP40

VSO40

QFP44

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

FUNCTIONAL DESCRIPTION OVERVIEW

This chapter gives a brief overview of the device.
The detailed functional description is in the following
chapters as follows:

Chapter 9 "Memory organization"

Chapter 10 "I/O facilities"

Chapter 11 "Timers/event counters"

Chapter 12 "Reduced power modes"

Chapter 13 "Standard serial interface SIO0: UART"

Chapter 14 "Interrupt system"

Chapter 15 "Oscillator circuitry"

Chapter 16 "Reset".

8.1

General

The P80CLx1 is a stand-alone high-performance CMOS
microcontroller designed for use in real-time applications
such as instrumentation, industrial control, intelligent
computer peripherals and consumer products.

The device provides hardware features, architectural
enhancements and new instructions to function as a
controller for applications requiring up to 64 kbytes of
Program Memory and/or up to 64 kbytes of Data Memory.

The P80CLx1 contains 4 kbytes Program Memory (ROM;
P80CL51 only); a static 128 bytes Data Memory (RAM);
32 I/O lines; two16-bit timer/event counters;
a thirteen-source, two priority-level, nested interrupt
structure and on-chip oscillator and timing circuit.
A standard UART serial interface is also provided.

The device has two software-selectable modes of reduced
activity for power reduction:

Idle mode; freezes the CPU while allowing the timers,
serial I/O and interrupt system to continue functioning.

Power-down mode; saves the RAM contents but
freezes the oscillator causing all other chip functions to
be inoperative.

8.2

CPU timing

A machine cycle consists of a sequence of 6 states. Each
state lasts for two oscillator periods, thus a machine cycle
takes 12 oscillator periods or 1

s if the oscillator

frequency (f

osc

) is 12 MHz.

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

MEMORY ORGANIZATION

The P80CLx1 has 4 kbytes of Program Memory (ROM;
P80CL51 only) plus 128 bytes of Data Memory (RAM) on
board.The device has separate address spaces for
Program and Data Memory (see Fig.5). Using Port latches
P0 and P2, the P80CLx1 can address a maximum of
64 kbytes of program memory and a maximum of
64 kbytes of data memory. The CPU generates both read
(RD) and write (WR) signals for external Data Memory
accesses, and the read strobe (PSEN) for external
Program Memory.

9.1

Program Memory

The P80CL51 contains 4 kbytes of internal ROM. After
reset the CPU begins execution at location 0000H.
The lower 4 kbytes of Program Memory can be
implemented in either on-chip ROM or external Program
Memory.

If the EA pin is tied to V

, then Program Memory fetches

from addresses 0000H to 0FFFH are directed to the

internal ROM. Fetches from addresses 1000H to FFFFH
are directed to external ROM. Program Counter values
greater than 0FFFH are automatically addressed to
external memory regardless of the state of the EA pin.

9.2

Data Memory

The P80CLx1 contains 128 bytes of internal RAM and 25
Special Function Registers (SFR). The memory map
(Fig.5) shows the internal Data Memory space divided into
the lower 128, the upper 128, and the SFR space.
The lower 128 bytes of the internal RAM are organized as
mapped in Fig.6. The lowest 32 bytes are grouped into 4
banks of 8 registers. Program instructions refer to these
registers within a register bank as R0 through R7. Two bits
in the Program Status Word select which register bank is
in use. The next 16 bytes above the register banks form a
block of bit-addressable memory space. The 128 bits in
this area can be directly addressed by the single-bit
manipulation instructions. The remaining registers
(30H to 7FH) are directly and indirectly byte addressable.

Fig.5 Memory map.

handbook, full pagewidth

MLA559

INTERNAL
DATA RAM

255

127

EXTERNAL

(EA = 0)

INTERNAL

(EA = 1)

INTERNAL DATA MEMORY

EXTERNAL

DATA MEMORY

PROGRAM MEMORY

EXTERNAL

64K

4096

4095

OVERLAPPED SPACE

4095

SPECIAL

FUNCTION

REGISTERS

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

Fig.6 The lower 128 bytes of internal RAM.

handbook, halfpage

MLA560 - 1

07H

0FH

08H

17H

10H

1FH

18H

2FH

7FH

20H

30H

bit-addressable space

(bit addresses 0 to 7F)

4 banks of 8 registers

(R0 to R7)

9.3

Special Function Registers (SFRs)

The upper 128 bytes are the address locations of the
SFRs. Figure 7 shows the SFR space. The SFRs include
the port latches, timers, peripheral control, serial I/O
registers, etc. These registers can only be accessed by
direct addressing. There are 128 directly addressable
locations in the SFR address space (SFRs with addresses
divisible by eight).

9.4

Addressing

The P8xCL410 has five methods for addressing source
operands:

Direct

Immediate

Base-register plus index-register-indirect.

The first three methods can be used for addressing
destination operands. Most instructions have a
`destination/source' field that specifies the data type,
addressing methods and operands involved.
For operations other than MOVs, the destination operand
is also a source operand.

Access to memory addressing is as follows:

Registers in one of the four register banks through
register, direct or register-indirect

Internal RAM (128 bytes) through direct or
register-indirect

Special Function Registers through direct

External data memory through register-indirect

Program Memory look-up tables through base-register
plus index-register-indirect.

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

10 I/O FACILITIES

10.1

Ports

The P80CLx1 has 32 I/O lines treated as 32 individually
addressable bits or as four parallel 8-bit addressable ports.
Ports 0, 1, 2 and 3 perform the alternative functions
detailed below. To enable a port pin alternate function, the
port bit latch in its SFR must contain a logic 1.

Port 0 Provides the multiplexed low-order address and

data bus for expanding the device with standard
memories and peripherals.

Port 1 Provides the inputs for the external interrupts

INT2 to INT9.

Port 2 Provides the high-order address when expanding

the device with external Program or Data Memory.

Port 3 Pins can be configured individually to provide:

External interrupt request inputs: INT1 and INT0

Timer/counter inputs: T1 and T0

Control signals to read and write to external
memories: RD and WR

UART input and output: RXD/data and
TXD/clock.

Each port consists of a latch (SFRs P0 to P3), an output
driver and input buffer. Ports 1, 2, and 3 have internal
pull-ups Figure 8(a) shows that the strong transistor `p1' is
turned on for only 2 oscillator periods after a LOW-to-HIGH
transition in the port latch. When on, it turns on `p3' (a weak
pull-up) through the inverter. This inverter and `p3' form a
latch which holds the logic 1. In Port 0 the pull-up `p1' is
only on when emitting logic 1s for external memory
access. Writing a logic 1 to a Port 0 bit latch leaves both
output transistors switched off so that the pin can be used
as a high-impedance input.

10.2

Port options

The pins of port 1, port 2 and port 3 may be individually
configured with one of the following options. These options
are also shown in Fig.8.

Option 1 Standard Port; quasi-bidirectional I/O with

pull-up. The strong booster pull-up `p1' is turned
on for two oscillator periods after a
LOW-to-HIGH transition in the port latch;
Fig.8(a).

Option 2 Open-drain; quasi-bidirectional I/O with

n-channel open-drain output. Use as an output
requires the connection of an external pull-up
resistor; see Fig.8(b).

Option 3 Push-pull; output with drive capability in both

polarities. Under this option, pins can only be
used as outputs; see Fig.8(c).

10.3

Port 0 options

The definition of port options for Port 0 is slightly different.
Two cases are considered. First, access to external
memory (EA = 0 or access above the built-in memory
boundary) and second, I/O accesses.

10.3.1

XTERNAL MEMORY ACCESSES

Option 1 True logic 0 and logic 1 are written as address to

the external memory (strong pull-up to be used).

Option 2 An external pull-up resistor is required for

external accesses.

Option 3 Not allowed for external memory accesses as

the port can only be used as output.

10.3.2

I/O A

CCESSES

Option 1 When writing a logic 1 to the port latch, the

strong pull-up `p1' will be on for 2 oscillator
periods. No weak pull-up exists. Without an
external pull-up, this option can be used as a
high-impedance input.

Option 2 Open-drain; quasi-directional I/O with n-channel

open-drain output. Use as an output requires the
connection of an external pull-up resistor.
See Fig.8(b).

Option 3 Push-Pull; output with drive capability in both

polarities. Under this option pins can only be
used as outputs. See Fig.8(c).

10.4

SET/RESET options

Individual mask selection of the post-reset state is
available with any of the above pins. The required
selection is made by appending `S' or `R' to Options 1, 2,
or 3 above.

Option R RESET, at reset this pin will be initialized LOW.

Option S SET, at reset this pin will be initialized HIGH.

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

11 TIMERS/EVENT COUNTERS

The P80CLx1 contains two16-bit timer/event counter
registers; Timer 0 and Timer 1, which can perform the
following functions:

Measure time intervals and pulse durations

Count events

Generate interrupt requests.

In the `Timer' operating mode the register is incremented
every machine cycle. Since a machine cycle consists of 12
oscillator periods, the count rate is

osc

In the `Counter' operating mode, the register is
incremented in response to a HIGH-to-LOW transition.
Since it takes 2 machine cycles (24 oscillator periods) to
recognize a HIGH-to-LOW transition, the maximum count
rate is

osc

. To ensure a given level is sampled, it

should be held for at least one complete machine cycle.

Timer 0 and Timer 1 can be programmed independently to
operate in four modes:

Mode 0 8-bit timer or 8-bit counter each with divide-by-32

prescaler.

Mode 1 16-bit time-interval or event counter.

Mode 2 8-bit time-interval or event counter with automatic

reload upon overflow.

Mode 3 Timer 0 establishes TL0 and TH0 as two

separate counters.

12 REDUCED POWER MODES

There are two software selectable modes of reduced
activity for further power reduction: Idle and Power-down.

12.1

Idle mode

Idle mode operation permits the external interrupts, UART,
and timer blocks to continue to function while the clock to
the CPU is halted.

Idle mode is entered by setting the IDL bit in the Power
Control Register (PCON.0, see Table 2). The instruction
that sets IDL is the last instruction executed in the normal
operating mode before the Idle mode is activated.

Once in Idle mode, the CPU status is preserved along with
the Stack Pointer, Program Counter, Program Status
Word and Accumulator. The RAM and all other registers
maintain their data during Idle mode. The status of the
external pins during Idle mode is shown in Table 3.

The following functions remain active during the Idle
mode:

Timer 0 and Timer 1

UART

External interrupt.

These functions may generate an interrupt or reset; thus
ending the Idle mode.

There are two ways to terminate the Idle mode:

1. Activation of any enabled interrupt will cause IDL

(PCON.0) to be cleared by hardware thus terminating
the Idle mode. The interrupt is serviced, and following
the RETI instruction, the next instruction to be
executed will be the one following the instruction that
put the device in the Idle mode. The flag bits GF0
(PCON.2) and GF1 (PCON.3) may be used to
determine whether the interrupt was received during
normal execution or during the Idle mode.
For example, the instruction that writes to PCON.0 can
also set or clear one or both flag bits. When the Idle
mode is terminated by an interrupt, the service routine
can examine the status of the flag bits.

2. The second way of terminating the Idle mode is with an

external hardware reset. Since the oscillator is still
running, the hardware reset is required to be active for
two machine cycles (24 oscillator periods) to complete
the reset operation. Reset redefines all SFRs but does
not affect the on-chip RAM.

12.2

Power-down mode

Operation in Power-down mode freezes the oscillator.
The internal connections which link both Idle and
Power-down signals to the clock generation circuit are
shown in Fig.9.

Power-down mode is entered by setting the PD bit in the
Power Control Register (PCON.1, see Table 2).
The instruction that sets PD is the last executed prior to
going into the Power-down mode.

Once in the Power-down mode, the oscillator is stopped.
The contents of the on-chip RAM and the SFRs are
preserved. The port pins output the value held by their
respective SFRs. ALE and PSEN are held LOW.

In the Power-down mode, V

may be reduced to

minimize circuit power consumption. The supply voltage
must not be reduced until the Power-down mode is
entered, and must be restored before the hardware reset
is applied which will free the oscillator. Reset should not be
released until the oscillator has restarted and stabilized.

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

12.3

Wake-up from Power-down mode

When in Power-down mode the controller can be
woken-up with either the external interrupts INT2 to INT9,
or a reset operation. The wake-up operation has two basic
approaches as explained in Section 12.3.1; 12.3.2 and
illustrated in Fig.10.

12.3.1

AKE

UP USING

INT2

INT9

If any of the interrupts INT2 to INT9 are enabled, the
device can be woken-up from the Power-down mode with
the external interrupts. To ensure that the oscillator is
stable before the controller restarts, the internal clock will
remain inactive for 1536 oscillator periods. This is
controlled by an on-chip delay counter.

12.3.2

AKE

UP USING

RST

To wake-up the P80CLx1, the RST pin must be kept HIGH
for a minimum of 24 periods. The on-chip delay counter is
inactive. The user must ensure that the oscillator is stable
before any operation is attempted.

12.4

Power Control Register (PCON)

See Tables 2 and 3. Idle and Power-down modes are
activated by software using this SFR. PCON is not
bit-addressable.

12.5

Status of external pins

The status of the external pins during Idle and Power-down
mode is shown in Table 4. If the Power-down mode is
activated whilst accessing external Program Memory, the
port data that is held in the Special Function Register P2 is
restored to Port 2.

If the data is a logic 1, the port pin is held HIGH during the
Power-down mode by the strong pull-up transistor `p1';
see Fig.8(a).

Table 2

Power Control Register (address 87H)

Table 3

Description of PCON bits

Table 4

Status of external pins during Idle and Power-down modes

SMOD

GF1

GF0

IDL

BIT

SYMBOL

DESCRIPTION

SMOD

Double Baud rate bit; see description of UART

6, 5, 4

reserved

3 and 2

GF1 and GF0 General purpose flag bits

Power-down bit; setting this bit activates the Power-down mode

IDL

Idle mode bit; setting this bit activates the Idle mode

MODE

MEMORY

ALE

PSEN

PORT 0

PORT 1

PORT 2

PORT 3

PORT 4

Idle

internal

port data

external

floating

port data

address

port data

Power-down

internal

port data

external

floating

port data

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

13 STANDARD SERIAL INTERFACE SIO0: UART

This serial port is full duplex which means that it can
transmit and receive simultaneously. It is also
receive-buffered and can commence reception of a
second byte before a previously received byte has been
read from the register. (However, if the first byte has not
been read by the time the reception of the second byte is
complete, one of the bytes will be lost). The serial port
receive and transmit registers are both accessed via the
Special Function Register S0BUF. Writing to S0BUF loads
the transmit register and reading S0BUF accesses a
physically separate receive register.

The serial port can operate in 4 modes:

Mode 0 Serial data enters and exits through RXD. TXD

outputs the shift clock. Eight bits are
transmitted/received (LSB first). The baud rate is
fixed at

osc

Mode 1 10 bits are transmitted (through TXD) or received

(through RXD): a start bit (logic 0), 8 data bits
(LSB first), and a stop bit (logic 1). On receive,
the stop bit goes into RB8 in Special Function
Register S0CON. The baud rate is variable.

Mode 2 11 bits are transmitted (through TXD) or received

(through RXD): start bit (logic 0), 8 data bits (LSB
first), a programmable 9

data bit, and a stop bit

(logic 1). On transmit, the 9

data bit (TB8 in

S0CON) can be assigned the value of a logic 0 or
logic 1. Or, for example, the parity bit (P, in the
PSW) could be moved into TB8. On receive, the
9

data bit goes into RB8 in S0CON, while the

stop bit is ignored. The baud rate is
programmable to either

osc

Mode 3 11 bits are transmitted (through TXD) or received

(through RXD): a start bit (logic 0), 8 data bits
(LSB first), a programmable 9

data bit and a

stop bit (logic 1). In fact, Mode 3 is the same as
Mode 2 in all respects except baud rate.
The baud rate in Mode 3 is variable.

In all four modes, transmission is initiated by any
instruction that uses S0BUF as a destination register.
Reception is initiated in Mode 0 by the condition RI = 0 and
REN = 1. Reception is initiated in the other modes by the
incoming start bit if REN = 1.

13.1

Multiprocessor communications

Modes 2 and 3 have a special provision for multiprocessor
communications. In these modes, 9 data bits are received.
The 9

bit goes into RB8. The following bit is the stop bit.

The port can be programmed such that when the stop bit
is received, the serial port interrupt will be activated, but
only if RB8 = 1. This feature is enabled by setting bit SM2
in S0CON. One use of this feature, in multiprocessor
systems, is as follows.

When the master processor wants to transmit a block of
data to one of several slaves, it first sends out an address
byte which identifies the target slave. An address byte
differs from a data byte in that the 9

bit is HIGH in an

address byte and LOW in a data byte. With SM2 = 1,
no slave will be interrupted by a data byte. An address
byte, however, will interrupt all slaves, so that each slave
can examine the received byte and see if it is being
addressed. The addressed slave will clear its SM2 bit and
prepare to receive the data bytes that will be sent. The
slaves that were not being addressed leave their SM2 bits
set and go on about their business, ignoring the coming
data bytes.

SM2 has no effect in Mode 0, and in Mode 1 can be used
to check the validity of the stop bit. In a Mode 1 reception,
if SM2 = 1, the receive interrupt will not be activated unless
a valid stop bit is received.

13.2

Serial Port Control and Status Register
(S0CON)

The Serial Port Control and Status Register is the Special
Function Register S0CON. The register contains not only
the mode selection bits, but also the 9

data bit for transmit

and receive (TB8 and RB8), and the serial port interrupt
bits (TI and RI).

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

Table 5

Serial Port Control Register (address 98H)

Table 6

Description of S0CON bits

Table 7

Selection of the serial port modes

SM0

SM1

SM2

REN

TB8

RB8

BIT

SYMBOL

DESCRIPTION

SM0

These bits are used to select the serial port mode; see Table 7.

SM1

SM2

Enables the multiprocessor communication feature in Modes 2 and 3. In these modes, if
SM2 = 1, then RI will not be activated if the received 9

data bit (RB8) is a logic 0.

In Mode 1, if SM2 = 1, then RI will not be activated unless a valid stop bit was received.
In Mode 0, SM2 should be a logic 0.

REN

Enables serial reception and is set by software to enable reception, and cleared by
software to disable reception.

TB8

Is the 9

data bit that will be transmitted in Modes 2 and 3; set or cleared by software as

desired.

RB8

In Modes 2 and 3, is the 9

data bit received. In Mode 1, if SM2 = 0 then RB8 is the stop

bit that was received; in Mode 0, RB8 is not used.

The transmit interrupt flag. Set by hardware at the end of the 8

bit time in Mode 0, or

at the beginning of the stop bit time in the other modes, in any serial transmission. Must
be cleared by software.

The receive interrupt flag. Set by hardware at the end of the 8

bit time in Mode 0, or

halfway through the stop bit time in the other modes, in any serial transmission (except
see SM2). Must be cleared by software.

SM0

SM1

MODE

DESCRIPTION

BAUD RATE

Mode 0

Shift register

osc

Mode 1

8-bit UART

variable

Mode 2

9-bit UART

osc

Mode 3

9-bit UART

variable

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

13.3

Baud rates

The baud rate in Mode 0 is fixed and may be calculated as:

The baud rate in Mode 2 depends on the value of the
SMOD bit in Special Function Register PCON and may be
calculated as:

If SMOD = 0 (value on reset), the baud rate is

osc

If SMOD = 1, the baud rate is

osc

The baud rates in Modes 1 and 3 are determined by the
Timer 1 or Timer 2 overflow rate.

13.3.1

SING

IMER

TO GENERATE BAUD RATES

When Timer 1 is used as the Baud Rate Generator, the
baud rates in Modes 1 and 3 are determined by the
Timer 1 overflow rate and the value of the SMOD bit as

Baud Rate

osc

--------

Baud Rate

SMOD

-----------------

osc

follows:

The Timer 1 interrupt should be disabled in this
application. The Timer itself can be configured for either
`timer' or `counter' operation in any of its 3 running modes.
In most typical applications, it is configured for `timer'
operation, in the Auto-reload mode (high nibble of
TMOD = 0010B). In this case the baud rate is given by the
formula:

By configuring Timer 1 to run as a 16-bit timer (high nibble
of TMOD = 0001B), and using the Timer 1 interrupt to do
a 16-bit software reload, very low baud rates can be
achieved. Table 8 lists commonly used baud rates and
how they can be obtained from Timer 1.

Baud Rate

SMOD

-----------------

Timer 1 Overflow Rate.

Baud Rate

SMOD

-----------------

osc

256

TH1

(

)

{

}

--------------------------------------------------------

Table 8

Commonly used baud rates generated by Timer 1

Notes

1. Maximum in Mode 0.

2. X = don't care.

3. Maximum in Mode 2.

4. Maximum in Modes 1 and 3.

BAUD RATE (kbits/s)

osc

(MHz)

SMOD

C/T

TIMER 1 MODE

RELOAD VALUE

1330.0

(1)

16.000

(2)

500.0

(3)

16.000

83.3

(4)

16.000

Mode 2

FFH

19.2

11.059

Mode 2

FDH

9.6

11.059

Mode 2

FDH

4.8

11.059

Mode 2

FAH

2.4

11.059

Mode 2

F4H

1.2

11.059

Mode 2

E8H

137.5

11.986

Mode 2

1DH

110.0

6.000

Mode 2

72H

110.0

12.000

Mode 1

FEEBH

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

14 INTERRUPT SYSTEM

External events and the real-time-driven on-chip
peripherals require service by the CPU at unpredictable
times. To tie the asynchronous activities of these functions
to normal program execution a multiple-source,
two-priority-level, nested interrupt system is provided.
The system is shown in Fig.19. The P80CLx1
acknowledges interrupt requests from thirteen sources as
follows:

INT0 to INT9

Timer 0 and Timer 1

UART.

Each interrupt vectors to a separate location in Program
Memory for its service routine. Each source can be
individually enabled or disabled by corresponding bits in
the Interrupt Enable Registers (IEN0 and IEN1).
The priority level is selected via the Interrupt Priority
Registers (IP0 and IP1). All enabled sources can be
globally disabled or enabled. Figure 19 shows the interrupt
system.

14.1

External interrupts INT2 to INT9

Port 1 lines serve an alternative purpose as eight
additional interrupts INT2 to INT9. When enabled, each of
these lines may wake-up the device from the Power-down
mode. Using the Interrupt Polarity Register (IX1), each pin
may be initialized to be either active HIGH or active LOW.
IRQ1 is the Interrupt Request Flag Register. If the interrupt
is enabled, each flag will be set on an interrupt request but
must be cleared by software, i.e. via the interrupt software
or when the interrupt is disabled.

Port 1 interrupts are level sensitive. A Port 1 interrupt will
be recognized when a level (HIGH or LOW depending on
the Interrupt Polarity Register) on P1.n is held active for at
least one machine cycle. The interrupt request is not
serviced until the next machine cycle. Figure 20 shows the
external interrupt configuration.

14.2

Interrupt priority

Each interrupt source can be set to either a high priority or
to a low priority. If a low priority interrupt is received
simultaneously with a high priority interrupt, the high
priority interrupt will be dealt with first.

If interrupts of the same priority are requested
simultaneously, the processor will branch to the interrupt
polled first, according to the sequence shown in Table 9
and in Fig.19. The `vector address' is the ROM location
where the appropriate interrupt service routine starts.

Table 9

Interrupt vector polling sequence

A low priority interrupt routine can only be interrupted by a
high priority interrupt. A high priority interrupt routine
cannot be interrupted.

SYMBOL

VECTOR

ADDRESS (HEX)

SOURCE

X0 (first)

0003

External 0

002B

UART

0053

External 5

000B

Timer 0

005B

External 6

0013

External 1

003B

External 2

0063

External 7

001B

Timer 1

0043

External 3

006B

External 8

004B

External 4

X9 (last)

0073

External 9

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

14.3.1

NTERRUPT

NABLE

EGISTER

(IEN0)

Bit values: 0 = interrupt disabled; 1 = interrupt enabled.

Table 11 Interrupt Enable Register (SFR address A8H)

Table 12 Description of IEN0 bits

14.3.2

NTERRUPT

NABLE

EGISTER

(IEN1)

Bit values: 0 = interrupt disabled; 1 = interrupt enabled.

Table 13 Interrupt Enable Register (SFR address E8H)

Table 14 Description of IEN1 bits

ES0

ET1

EX1

ET0

EX0

BIT

SYMBOL

DESCRIPTION

general enable/disable control. If EA = 0, no interrupt is enabled; if EA = 1, any
individually enabled interrupt will be accepted

reserved

ES0

enable UART SIO interrupt

ET1

enable Timer 1 interrupt (T1)

EX1

enable external interrupt 1

ET0

enable Timer 0 interrupt (T0)

EX0

enable external interrupt 0

EX9

EX8

EX7

EX6

EX5

EX4

EX3

EX2

BIT

SYMBOL

DESCRIPTION

EX9

enable external interrupt 9

EX8

enable external interrupt 8

EX7

enable external interrupt 7

EX6

enable external interrupt 6

EX5

enable external interrupt 5

EX4

enable external interrupt 4

EX3

enable external interrupt 3

EX2

enable external interrupt 2

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

14.3.3

NTERRUPT

RIORITY

EGISTER

(IP0)

Bit values: 0 = low priority; 1 = high priority.

Table 15 Interrupt Priority Register (SFR address B8H)

Table 16 Description of IP0 bits

14.3.4

NTERRUPT

RIORITY

EGISTER

(IP1)

Bit values: 0 = low priority; 1 = high priority.

Table 17 Interrupt Priority Register (SFR address F8H)

Table 18 Description of IP1 bits

PS0

PT1

PX1

PT0

PX0

BIT

SYMBOL

DESCRIPTION

reserved

PS0

UART SIO interrupt priority level

PT1

Timer 1 interrupt priority level

PX1

external interrupt 1 priority level

PT0

Timer 0 interrupt priority level

PX0

external interrupt 0 priority level

PX9

PX8

PX7

PX6

PX5

PX4

PX3

PX2

BIT

SYMBOL

DESCRIPTION

PX9

external interrupt 9 priority level

PX8

external interrupt 8 priority level

PX7

external interrupt 7 priority level

PX6

external interrupt 6 priority level

PX5

external interrupt 5 priority level

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

14.3.5

NTERRUPT

OLARITY

EGISTER

(IX1)

Writing either a logic 1 or logic 0 to any Interrupt Polarity Register bit sets the polarity level of the corresponding external
interrupt to an active HIGH or active LOW respectively.

Table 19 Interrupt Polarity Register (SFR address E9H)

Table 20 Description of IX1 bits

14.3.6

NTERRUPT

EQUEST

LAG

EGISTER

(IRQ1)

Table 21 Interrupt Request Flag Register (SFR address C0H)

Table 22 Description of IRQ1 bits

PX4

external interrupt 4 priority level

PX3

external interrupt 3 priority level

PX2

external interrupt 2 priority level

IL9

IL8

IL7

IL6

IL5

IL4

IL3

IL2

BIT

SYMBOL

DESCRIPTION

IL9

external interrupt 9 polarity level

IL8

external interrupt 8 polarity level

IL7

external interrupt 7 polarity level

IL6

external interrupt 6 polarity level

IL5

external interrupt 5 polarity level

IL4

external interrupt 4 polarity level

IL3

external interrupt 3 polarity level

IL2

external interrupt 2 polarity level

IQ9

IQ8

IQ7

IQ6

IQ5

IQ4

IQ3

IQ2

BIT

SYMBOL

DESCRIPTION

IQ9

external interrupt 9 request flag

IQ8

external interrupt 8 request flag

IQ7

external interrupt 7 request flag

IQ6

external interrupt 6 request flag

IQ5

external interrupt 5 request flag

IQ4

external interrupt 4 request flag

IQ3

external interrupt 3 request flag

IQ2

external interrupt 2 request flag

BIT

SYMBOL

DESCRIPTION

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

15 OSCILLATOR CIRCUITRY

The on-chip oscillator circuitry of the P80CLx1 is a
single-stage inverting amplifier biased by an internal
feedback resistor. The oscillator circuit is shown in Fig.22.
For operation as a standard quartz oscillator, no external
components are needed, except for the 32 kHz option.
When using external capacitors, ceramic resonators, coils
and RC networks to drive the oscillator, five different
configurations are supported (see Table 23 and Fig.21).

In the Power-down mode the oscillator is stopped and
XTAL1 is pulled HIGH. The oscillator inverter is switched
off to ensure no current will flow regardless of the voltage
at XTAL1, for configurations (a), (b), (c), (d), (e) and (g) of
Fig.21.

To drive the device with an external clock source, apply the
external clock signal to XTAL1, and leave XTAL2 to float,
as shown in Fig.21(f). There are no requirements on the
duty cycle of the external clock, since the input to the
internal clocking circuitry is buffered by a flip-flop.

Various oscillator options are provided for optimum
on-chip oscillator performance; these are specified in
Table 23 and shown in Fig.21. The required option should
be stated when ordering.

Table 23 Oscillator options

OPTION

APPLICATION

Oscillator 1

for 32 kHz clock applications with external trimmer for frequency adjustment; a 4.7 M

bias resistor

is needed for use in parallel with the crystal; see Fig.21(c)

Oscillator 2

low-power, low-frequency operations using LC components; see Fig.21(e)

Oscillator 3

medium frequency range applications

Oscillator 4

high frequency range applications

RC oscillator

RC oscillator configuration; see Figs 21(g) and 23

handbook, full pagewidth

MLA577

VDD

XTAL1

XTAL2

(d)

XTAL1

XTAL2

(e)

XTAL1

XTAL2

(f)

XTAL1

XTAL2

(g)

n.c.

XTAL1

XTAL2

(b)

XTAL1

XTAL2

(c)

XTAL1

XTAL2

(a)

STANDARD

QUARTZ

OSCILLATOR

QUARTZ OSCILLATOR

WITH EXTERNAL

CAPACITORS

32 kHz

OSCILLATOR

CERAMIC

RESONATOR

LC - OSCILLATOR

EXTERNAL CLOCK

RC - OSCILLATOR

Fig.21 Oscillator configurations.

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

Table 25 Oscillator equivalent circuit parameters

The equivalent circuit data of the internal oscillator compares with that of matched crystals.

SYMBOL

PARAMETER

OPTION

CONDITION

MIN.

TYP.

MAX.

UNIT

transconductance

Oscillator 1; 32 kHz

amb

= +25

= 4.5 V

Oscillator 2

200

600

1000

Oscillator 3

400

1500

4000

Oscillator 4

1000

4000

10000

input capacitance

Oscillator 1; 32 kHz

3.0

Oscillator 2

8.0

Oscillator 3

8.0

Oscillator 4

8.0

output capacitance

Oscillator 1; 32 kHz

Oscillator 2

8.0

Oscillator 3

8.0

Oscillator 4

8.0

output resistance

Oscillator 1; 32 kHz

3800

Oscillator 2

Oscillator 3

Oscillator 4

5.0

Fig.24 Oscillator equivalent circuit diagram.

handbook, full pagewidth

MLA578

C1 i

R f

g m

C2 i

R 2

XTAL1

XTAL2

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

16 RESET

To initialize the P80CLx1 a reset is performed by either of
three methods:

Applying an external signal to the RST pin

Via Power-on-reset circuitry.

A reset leaves the internal registers as shown in
Chapter 18. The reset state of the port pins is
mask-programmable and can be defined by the user.

16.1

External reset using the RST pin

The reset input for the P80CLx1 is RST. A Schmitt trigger
is used at the input for noise rejection. The output of the
Schmitt trigger is sampled by the reset circuitry every
machine cycle. A reset is accomplished by holding the
RST pin HIGH for at least two machine cycles
(24 oscillator periods) while the oscillator is running.
The CPU responds by executing an internal reset. Port
pins adopt their reset state immediately after the RST goes
HIGH. During reset, ALE and PSEN are held HIGH.

The external reset is asynchronous to the internal clock.
The RST pin is sampled during state 5, phase 2 of every
machine cycle. After a HIGH is detected at the RST pin, an
internal reset is repeated until RST goes LOW.
The internal RAM is not affected by reset. When V

turned on, the RAM contents are indeterminate.

16.2

Power-on-reset

The device contains on-chip circuitry which switches the
port pins to the customer defined logic level as soon as
V

exceeds 1.3 V; if the mask option `ON' has been

chosen. As soon as the minimum supply voltage is
reached, the oscillator will start up. However, to ensure
that the oscillator is stable before the controller starts, the
clock signals are gated away from the CPU for a further
1536 oscillator periods. During that time the CPU is held in
a reset state. A hysteresis of approximately 50 mV at a
typical power-on switching level of 1.3 V will ensure
correct operation (see Fig.27).

The on-chip Power-on-reset circuitry can also be switched
off via the mask option `OFF'. This option reduces the
Power-down current to typically 800 nA and can be
chosen if external reset circuitry is used. For applications
not requiring the internal reset, option `OFF' should be
chosen.

An automatic reset can be obtained by connecting the RST
pin to V

via a 10

F capacitor. At power-on, the voltage

on the RST pin is equal to V

minus the capacitor voltage,

and decreases from V

as the capacitor charges through

the internal resistor (R

RST

) to ground. The larger the

capacitor, the more slowly V

RST

decreases. V

RST

must

remain above the lower threshold of the Schmitt trigger
long enough to effect a complete reset. The time required
is the oscillator start-up time, plus 2 machine cycles.
The Power-on-reset circuitry is shown in Fig.26.

Fig.25 Reset configuration.

handbook, halfpage

MLA580

SCHMITT

TRIGGER

RESET

CIRCUITRY

RST

Fig.26 Recommended Power-on-reset circuitry.

handbook, halfpage

VDD

RST

R RST

MLA582

P80CL31
P80CL51

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

Fig.27 Power-on-reset switching level.

handbook, full pagewidth

MLA581

SUPPLY
VOLTAGE

POWER-ON-RESET
(INTERNAL)

OSCILLATOR

CPU RUNNING

Start-up

time

1536 oscillator

periods delay

hysteresis

switching level

POR

17 MASK OPTIONS FOR P80CL31 AND P80C51

17.1

P80CL31: ROMless version

The P80CL31 is a low voltage ROMless version of the
P80CL51 microcontroller. The mask options for the
P80CL31 are fixed as follows:

Port options: all ports have option "1S", i.e. standard
port, HIGH after reset

Oscillator option: Oscillator 3

Power-on-reset option: OFF.

17.2

P80C51: 5 V standard version

The P80C51 is a 5 V version of the low voltage P80CL51
microcontroller. All functional features of the P80CL51 are
maintained in the P80C51 with the exception of the mask
options. The mask options on the P80C51 are fixed as
follows:

Port options: all ports have option "1S", i.e. standard
port, HIGH after reset

Oscillator option: Oscillator 3

Power-on-reset option: OFF.

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

18 SPECIAL FUNCTION REGISTERS OVERVIEW

The P80CLx1 has 25 SFRs available to the user.

Notes

1. Bit addressable register.

2. Port reset state determined by the customer.

ADDRESS

(HEX)

NAME

RESET VALUE

(B)

FUNCTION

IP1

(1)

00000000

Interrupt Priority Register (INT2 to INT9)

(1)

00000000

B Register

IX1

00000000

Interrupt Polarity Register

IEN1

(1)

00000000

Interrupt Enable Register 1

ACC

(1)

00000000

Accumulator

PSW

(1)

00000000

Program Status Word

IRQ1

(1)

00000000

Interrupt Request Flag Register

IP0

(1)

0000000

Interrupt Priority Register 0

(1)

XXXXXXXX

(2)

Digital I/O Port Register 3

IEN0

(1)

00000000

Interrupt Enable Register

(1)

XXXXXXXX

(2)

Digital I/O Port Register 2

S0BUF

XXXXXXXX

Serial Data Buffer Register 0

S0CON

(1)

00000000

Serial Port Control Register 0

(1)

XXXXXXXX

(2)

Digital I/O Port Register 1

TH1

00000000

Timer 1 High byte

TH0

00000000

Timer 0 High byte

TL1

00000000

Timer 1 Low byte

TL0

00000000

Timer 0 Low byte

TMOD

00000000

Timer 0 and 1 Mode Control Register

TCON

(1)

00000000

Timer 0 and 1 Control/External Interrupt Control Register

PCON

0XX00000

Power Control Register

DPH

00000000

Data Pointer High byte

DPL

00000000

Data Pointer Low byte

00000111

Stack Pointer

(1)

XXXXXXXX

(2)

Digital I/O Port Register 0

1997 Apr 15

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Product specification

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UART

P80CL31; P80CL51

19 INSTRUCTION SET

The P80CLx1 uses a powerful instruction set which permits the expansion of on-chip CPU peripherals and optimizes
byte efficiency and execution speed. Assigned opcodes add new high-power operation and permit new addressing
modes. The instruction set consists of 49 single-byte, 46 two-byte and 16 three-byte instructions. When using a 12 MHz
oscillator, 64 instructions execute in 1

s and 45 instructions execute in 2

s. Multiply and divide instructions execute in

For the description of the Data Addressing modes and Hexadecimal opcode cross-reference see Table 30.

Table 26 Instruction set description: Arithmetic operations

MNEMONIC

DESCRIPTION

BYTES

CYCLES

OPCODE

(HEX)

Arithmetic operations

ADD

A,Rr

add register to A

ADD

A,direct

add direct byte to A

ADD

A,@Ri

add indirect RAM to A

26, 27

ADD

A,#data

add immediate data to A

ADDC

A,Rr

add register to A with carry flag

ADDC

A,direct

add direct byte to A with carry flag

ADDC

A,@Ri

add indirect RAM to A with carry flag

36, 37

ADDC

A,#data

add immediate data to A with carry flag

SUBB

A,Rr

subtract register from A with borrow

SUBB

A,direct

subtract direct byte from A with borrow

SUBB

A,@Ri

subtract indirect RAM from A with borrow

96, 97

SUBB

A,#data

subtract immediate data from A with borrow

INC

increment A

INC

increment register

INC

direct

increment direct byte

INC

@Ri

increment indirect RAM

06, 07

DEC

decrement A

DEC

decrement register

DEC

direct

decrement direct byte

DEC

@Ri

decrement indirect RAM

16, 17

INC

DPTR

increment data pointer

MUL

multiply A and B

DIV

divide A by B

decimal adjust A

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

Table 27 Instruction set description: Logic operations

MNEMONIC

DESCRIPTION

BYTES

CYCLES

OPCODE

(HEX)

Logic operations

ANL

A,Rr

AND register to A

ANL

A,direct

AND direct byte to A

ANL

A,@Ri

AND indirect RAM to A

56, 57

ANL

A,#data

AND immediate data to A

ANL

direct,A

AND A to direct byte

ANL

direct,#data

AND immediate data to direct byte

ORL

A,Rr

OR register to A

ORL

A,direct

OR direct byte to A

ORL

A,@Ri

OR indirect RAM to A

46, 47

ORL

A,#data

OR immediate data to A

ORL

direct,A

OR A to direct byte

ORL

direct,#data

OR immediate data to direct byte

XRL

A,Rr

exclusive-OR register to A

XRL

A,direct

exclusive-OR direct byte to A

XRL

A,@Ri

exclusive-OR indirect RAM to A

66, 67

XRL

A,#data

exclusive-OR immediate data to A

XRL

direct,A

exclusive-OR A to direct byte

XRL

direct,#data

exclusive-OR immediate data to direct byte

CLR

clear A

CPL

complement A

rotate A left

RLC

rotate A left through the carry flag

rotate A right

RRC

rotate A right through the carry flag

SWAP

swap nibbles within A

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

Table 28 Instruction set description: Data transfer

Note

1. MOV A,ACC is not permitted.

MNEMONIC

DESCRIPTION

BYTES

CYCLES

OPCODE

(HEX)

Data transfer

MOV

A,Rr

move register to A

MOV

A,direct (note 1) move direct byte to A

MOV

A,@Ri

move indirect RAM to A

E6, E7

MOV

A,#data

move immediate data to A

MOV

Rr,A

move A to register

MOV

Rr,direct

move direct byte to register

MOV

Rr,#data

move immediate data to register

MOV

direct,A

move A to direct byte

MOV

direct,Rr

move register to direct byte

MOV

direct,direct

move direct byte to direct

MOV

direct,@Ri

move indirect RAM to direct byte

86, 87

MOV

direct,#data

move immediate data to direct byte

MOV

@Ri,A

move A to indirect RAM

F6, F7

MOV

@Ri,direct

move direct byte to indirect RAM

A6, A7

MOV

@Ri,#data

move immediate data to indirect RAM

76, 77

MOV

DPTR,#data 16

load data pointer with a 16-bit constant

MOVC

A,@A+DPTR

move code byte relative to DPTR to A

MOVC

A,@A+PC

move code byte relative to PC to A

MOVX

A,@Ri

move external RAM (8-bit address) to A

E2, E3

MOVX

A,@DPTR

move external RAM (16-bit address) to A

MOVX

@Ri,A

move A to external RAM (8-bit address)

F2, F3

MOVX

@DPTR,A

move A to external RAM (16-bit address)

PUSH

direct

push direct byte onto stack

POP

direct

pop direct byte from stack

XCH

A,Rr

exchange register with A

XCH

A,direct

exchange direct byte with A

XCH

A,@Ri

exchange indirect RAM with A

C6, C7

XCHD

A,@Ri

exchange LOW-order digit indirect RAM with A

D6, D7

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

Table 29 Instruction set description: Boolean variable manipulation, Program and machine control

MNEMONIC

DESCRIPTION

BYTES

CYCLES

OPCODE

(HEX)

Boolean variable manipulation

CLR

clear carry flag

CLR

bit

clear direct bit

SETB

set carry flag

SETB

bit

set direct bit

CPL

complement carry flag

CPL

bit

complement direct bit

ANL

C,bit

AND direct bit to carry flag

ANL

C,/bit

AND complement of direct bit to carry flag

ORL

C,bit

OR direct bit to carry flag

ORL

C,/bit

OR complement of direct bit to carry flag

MOV

C,bit

move direct bit to carry flag

MOV

bit,C

move carry flag to direct bit

Program and machine control

ACALL

addr11

absolute subroutine call

LCALL

addr16

long subroutine call

RET

return from subroutine

RETI

return from interrupt

AJMP

addr11

absolute jump

LJMP

addr16

long jump

SJMP

rel

short jump (relative address)

JMP

@A+DPTR

jump indirect relative to the DPTR

rel

jump if A is zero

JNZ

rel

jump if A is not zero

rel

jump if carry flag is set

JNC

rel

jump if carry flag is not set

bit,rel

jump if direct bit is set

JNB

bit,rel

jump if direct bit is not set

JBC

bit,rel

jump if direct bit is set and clear bit

CJNE

A,direct,rel

compare direct to A and jump if not equal

CJNE

A,#data,rel

compare immediate to A and jump if not equal

CJNE

Rr,#data,rel

compare immediate to register and jump if not equal

CJNE

@Ri,#data,rel compare immediate to indirect and jump if not equal

B6, B7

DJNZ

Rr,rel

decrement register and jump if not zero

DJNZ

direct,rel

decrement direct and jump if not zero

NOP

no operation

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

Table 30 Description of the mnemonics in the Instruction set

MNEMONIC

DESCRIPTION

Data addressing modes

working register R0-R7

direct

128 internal RAM locations and any special function register (SFR)

@Ri

indirect internal RAM location addressed by register R0 or R1 of the actual register bank

#data

8-bit constant included in instruction

#data 16

16-bit constant included as bytes 2 and 3 of instruction

bit

direct addressed bit in internal RAM or SFR.

addr16

16-bit destination address. Used by LCALL and LJMP;
the branch will be anywhere within the 64 kbytes Program Memory address space

addr11

111-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2 kbytes
page of Program Memory as the first byte of the following instruction

rel

signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps;
range is

128 to +127 bytes relative to first byte of the following instruction

Hexadecimal opcode cross-reference

8, 9, A, B, C, D, E, F

1, 3, 5, 7, 9, B, D, F

0, 2, 4, 6, 8, A, C, E

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

able 31

Instruction map

Note

MOV A, ACC is not a valid instruction.

First hexadecimal character of opcode

Second hexadecimal character of opcode

NOP

AJMP

addr1

LJMP

addr16

INC

direct

INC @Ri

INC Rr

01234567

JBC

bit,rel

ACALL

addr1

LCALL

addr16

RRC

DEC

direct

DEC @Ri

DEC Rr

01234567

bit,rel

AJMP

addr1

RET

ADD

A,#data

ADD

A,direct

ADD A,@Ri

ADD A,Rr

01234567

JNB

bit,rel

ACALL

addr1

RETI

RLC

ADDC

A,#data

ADDC

A,direct

ADDC A,@Ri

ADDC A,Rr

01234567

rel

AJMP

addr1

ORL

direct,A

ORL

direct,#data

ORL

A,#data

ORL

A,direct

ORL A,@Ri

ORL A,Rr

01234567

JNC

rel

ACALL

addr1

ANL

direct,A

ANL

direct,#data

ANL

A,#data

ANL

A,direct

ANL A,@Ri

ANL A,Rr

01234567

rel

AJMP

addr1

XRL

direct,A

XRL

direct,#data

XRL

A,#data

XRL

A,direct

XRL A,@Ri

XRL A,Rr

01234567

JNZ

rel

ACALL

addr1

ORL

C,bit

JMP

@A+DPTR

MOV

A,#data

MOV

direct,#data

MOV @Ri,#data

MOV Rr

,#data

01234567

SJMP

rel

AJMP

addr1

ANL

C,bit

MOVC

A,@A+PC

DIV

MOV

direct,direct

MOV direct,@Ri

MOV direct,Rr

01234567

MOV

DTPR,#data16

ACALL

addr1

MOV

bit,C

MOVC

A,@A+DPTR

SUBB

A,#data

SUBB

A,direct

SUBB A,@Ri

SUB A,Rr

01234567

ORL

C,/bit

AJMP

addr1

MOV

bit,C

INC

DPTR

MUL

MOV @Ri,direct

MOV Rr

,direct

01234567

ANL

C,/bit

ACALL

addr1

CPL

bit

CPL

CJNE

A,#data,rel

CJNE

A,direct,rel

CJNE @Ri,#data,rel

CJNE Rr

,#data,rel

01234567

PUSH

direct

AJMP

addr1

CLR

bit

CLR

XCH

A,direct

XCH A,@Ri

XCH A,Rr

01234567

POP

direct

ACALL

addr1

SETB

bit

SETB

DJNZ

direct,rel

XCHD A,@Ri

DJNZ Rr

,rel

01234567

MOVX

A,@DTPR

AJMP

addr1

MOVX A,@Ri

CLR

MOV

A,direct

(1)

MOV A,@Ri

MOV A,Rr

01234567

MOVX

@DTPR,A

ACALL

addr1

MOVX @Ri,A

CPL

MOV

direct,A

MOV @Ri,A

MOV Rr

01234567

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

20 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

21 DC CHARACTERISTICS FOR P80CL31 AND P80CL51

= 0 V; T

amb

40 to +85

C; all voltages with respect to V

unless otherwise specified.

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

supply voltage

0.5

+6.5

input voltage on any pin with respect to ground (V

)

0.5

+ 0.5

DC current on any input

5.0

+5.0

DC current on any output

5.0

+5.0

tot

total power dissipation

300

stg

storage temperature

+150

amb

operating ambient temperature

+85

operating junction temperature

+125

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

supply voltage

operating

= 0 V

1.8

6.0

RAM retention in Power-down
mode

1.0

Supply current (note 1, note 2)

operating supply current

Oscillator 1; f

clk

= 32 kHz; V

= 1.8 V;

amb

= 25

Oscillator 2; f

clk

= 3.58 MHz; V

= 3 V

2.5

Oscillator 3; f

clk

= 16 MHz; V

= 5 V

Oscillator 4; f

clk

= 16 MHz; V

= 5 V

Supply current (Idle mode) (note 2, note 3)

DD(idle)

supply current (Idle mode)

Oscillator 1; f

clk

= 32 kHz; V

= 1.8 V;

amb

= 25

Oscillator 2; f

clk

= 3.58 MHz; V

= 3 V

1.0

Oscillator 3; f

clk

= 16 MHz; V

= 5 V

Oscillator 4; f

clk

= 16 MHz; V

= 5 V

Supply current (Power-down mode) (note 2, note 4)

DD(pd)

supply current (Power-down mode) V

= 1.8 V; T

amb

= 25

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

Notes

1. The operating supply current is measured with all output pins disconnected; XTAL 1 driven with t

= t

= 10 ns;

= V

; V

= V

; XTAL 2 not connected; EA = RST = Port 0 = V

; all open drain outputs connected to V

2. Circuits with Power-on-reset option `OFF' are tested at V

DD(min)

= 1.8 V; within option `ON' (typically 1.3 V) they are

tested at V

DD(min)

= 2.3 V. Please note, option `ON' is only available on P80CL51.

3. The Idle mode supply current is measured with all output pins disconnected; XTAL 1 driven with t

= t

= 10 ns;

= V

. XTAL 2 not connected; EA = Port 0 = V

; RST = V

; all open drain outputs connected to V

4. The Power-down current is measured with all output pins disconnected; XTAL 1 not connected; EA = Port 0 = V

;

RST = V

; all open drain outputs connected to V

Inputs

LOW level input voltage

0.3V

HIGH level input voltage

0.7V

input current logic 0 (port 1,2,3)

= 5 V; V

= 0.4 V

100

= 2.5 V; V

= 0.4 V

ITL

input current logic 0, HIGH-
to-LOW transition (port 1,2,3)

= 5 V; V

= 0.5V

1.0

= 2.5 V; V

= 0.5V

500

input leakage current (port 0, EA)

< V

Port outputs

LOW level output current

= 5 V; V

= 0.4 V

1.6

= 2.5 V; V

= 0.4 V

0.7

HIGH level output current
(push-pull options)

= 5 V; V

= V

0.4 V

1.6

= 2.5 V; V

= V

0.4 V

0.7

RST

RST pull-down resistor

200

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

22 DC CHARACTERISTICS FOR P80C51

= 0 V; V

= 5.0V

10%; f

clk

= 3.5 to 16 MHz; T

amb

40 to +85

C all voltages with respect to V

unless

otherwise specified. Note that the Power-on-reset option is `OFF' and the Oscillator option is `Oscillator 3'.

Notes

1. The operating supply current is measured with all output pins disconnected; XTAL 1 driven with t

= t

= 10 ns;

= V

; V

= V

; XTAL 2 not connected; EA = RST = Port 0 = V

; all open drain outputs connected to V

2. The Idle mode supply current is measured with all output pins disconnected; XTAL 1 driven with t

= t

= 10 ns;

= V

. XTAL 2 not connected; EA = Port 0 = V

; RST = V

; all open drain outputs connected to V

3. The Power-down current is measured with all output pins disconnected; XTAL 1 not connected; EA = Port 0 = V

;

RST = V

; all open drain outputs connected to V

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

supply voltage

operating

= 0 V

4.5

5.5

RAM retention in Power-down
mode

1.0

operating supply current

clk

= 16 MHz; V

= 5.0 V; note 1

DD(idle)

supply current (Idle mode)

clk

= 16 MHz; V

= 5.0 V; note 2

DD(pd)

supply current (Power-down mode)

= 5.0 V; note 3

Inputs

LOW level input voltage

0.3V

HIGH level input voltage

0.7V

input current logic 0 (port 1,2,3)

= 0.4 V

100

input current logic 0, HIGH- to-LOW
transition (port 1,2,3)

= 0.5V

1.0

input leakage current (port 0, EA)

< V

Port outputs

LOW level output current

= 0.4 V

1.6

HIGH level output current (push-pull
options)

= V

0.4 V

1.6

RST

RST pull-down resistor

200

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

23 AC CHARACTERISTICS

= 5 V; V

= 0 V; T

amb

40 to +85

C; C

= 50 pF for Port 0, ALE and PSEN; C

= 40 pF for all other outputs

unless specified; t

CLK

= 1/ f

CLK

SYMBOL

PARAMETER

osc

= 12 MHz

osc

= VARIABLE

UNIT

MIN.

MAX.

MIN.

MAX.

Program Memory (Fig.32)

LHLL

ALE pulse width

127

CLK

AVLL

address valid to ALE LOW

CLK

LLAX

address hold after ALE LOW

CLK

LLIV

ALE LOW to valid instruction in

233

CLK

100

LLPL

ALE LOW to PSEN LOW

CLK

PLPH

PSEN pulse width

215

CLK

PLIV

PSEN LOW to valid instruction in

125

CLK

125

PXIX

input instruction hold after PSEN

PXIZ

input instruction float after PSEN

CLK

PXAV

PSEN to address valid

CLK

AVIV

address to valid instruction in

302

CLK

115

PLAZ

PSEN LOW to address float

External Data Memory (Figs 33 and 34)

RLRH

RD pulse width

400

CLK

100

WLWH

WR pulse width

400

CLK

100

LLAX

address hold after ALE LOW

CLK

RLDV

RD LOW to valid data in

150

CLK

165

RHDZ

data float after RD

CLK

LLDV

ALE LOW to valid data in

517

CLK

150

AVDV

address to valid data in

585

CLK

165

LLWL

ALE LOW to RD or WR LOW

200

300

CLK

+ 50

AVWL

address valid to RD or WR LOW

203

WHLH

RD or WR HIGH to ALE HIGH

123

CLK

+ 40

QVWX

data valid to WR transition

CLK

QVWH

data valid time WR HIGH

433

CLK

150

WHQX

data hold after WR

CLK

RLAZ

RD LOW to address float

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

Fig.35 Instruction cycle timing.

handbook, full pagewidth

MGD681

P1 P2

one machine cycle

XTAL1
INPUT

address

A0 - A7

inst.

address

A0 - A7

inst.

address

A0 - A7

inst.

address

A0 - A7

inst.

address A8 - A15

address

A0 - A7

inst.

address

A0 - A7

inst.

address

A0 - A7

data output or data input

address A8 - A15

address A8 - A15 or Port 2 output

address A8 - A15

old data

new data

sampling time of I/O port pins during input

SERIAL PORT
SHIFT CLOCK
(MODE 0)

PORT 0, 2, 3
INPUT

PORT 0, 2, 3
OUTPUT

PORT 2

BUS
(PORT 0)

read or

write of

external data

memory

PORT 2

BUS
(PORT 0)

external

program

memory

fetch

only active

during a write

to external

data memory

only active

during a read

from external
data memory

PSEN

ALE

dotted lines

are valid when

RD or WR are

active

old data

new data

PORT 1
OUTPUT

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

24 P85CL000HFZ `PIGGY-BACK' SPECIFICATION

The differences between the masked version and the
piggy-back are described below.

24.1

General description

The P85CL000HFZ is a piggy-back version with 256 bytes
of RAM used for emulation of the P80CL51 and the
P83CL410 microcontrollers. The P85CL000HFZ is
manufactured in an advanced CMOS technology.
The instruction set of the P85CL000HFZ is based on that
of the 8051. The device has low power consumption and a
wide supply voltage range. The P85CL000HFZ has two
software selectable modes of reduced activity for further
power reduction: Idle and Power-down. For timing and
AC/DC characteristics, please refer to the P80CL51
specifications.

24.2

Feature differences/additional features with
respect to P80CL51

No internal ROM

8-bit CPU, RAM, I/O in a single 40-lead package with
DIP pin-out

Socket for up to 16 kbytes external EPROM

256 bytes RAM, expandable externally to 64 kbytes

C-bus interface for serial transfer on two lines

On-chip oscillator: Oscillator 4 option only.

24.3

Common specification/feature differences between P85CL000HFZ and P83CL410/P80CL51

PARAMETER

P83CL410/P80CL51

P85CL000HFZ `PIGGY-BACK'

RAM size

128

256

ROM size

EPROM size dependent (max. 16K)

Port options

1, 2, 3

Oscillator options

Oscillator 1, 2, 3, 4, RC

Oscillator 4

Mechanical dimensions

standard dual in-line, small outline

same pin-out as SOT129-1, but larger
package size

Current consumption

(Oscillator 4) + I

EPROM

Voltage range

full

full, limited by EPROM

ESD

specification

not tested (different package)

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

UNIT

(1)

(2)

(1)

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

EIAJ

inches

0.3
0.1

2.45
2.25

0.25

0.42
0.30

0.22
0.14

15.6
15.2

7.6
7.5

0.762

2.25

12.3
11.8

1.15
1.05

0.6
0.3

7
0

0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Notes

1. Plastic or metal protrusions of 0.4 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

1.7
1.5

SOT158-1

92-11-17
95-01-24

detail X

(A )

pin 1 index

0.012
0.004

0.096
0.089

0.017
0.012

0.0087
0.0055

0.61
0.60

0.30
0.29

0.03

0.089

0.48
0.46

0.045
0.041

0.024
0.012

0.004

0.2

0.008

0.004

0.067
0.059

0.010

10 mm

scale

VSO40: plastic very small outline package; 40 leads

SOT158-1

max.

2.70

0.11

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

26 SOLDERING

26.1

Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"IC Package Databook" (order code 9398 652 90011).

26.2

DIP

26.2.1

OLDERING BY DIPPING OR BY WAVE

The maximum permissible temperature of the solder is
260

C; solder at this temperature must not be in contact

with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T

stg max

). If the

printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

26.2.2

EPAIRING SOLDERED JOINTS

Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300

C it may remain in

contact for up to 10 seconds. If the bit temperature is
between 300 and 400

C, contact may be up to 5 seconds.

26.3

QFP and VSO

26.3.1

EFLOW SOLDERING

Reflow soldering techniques are suitable for all QFP and
VSO packages.

The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

"Quality

Reference Manual" (order code 9397 750 00192).

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45

26.3.2

AVE SOLDERING

26.3.2.1

QFP

Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following
conditions must be observed:

A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.

The footprint must be at an angle of 45

to the board

direction and must incorporate solder thieves
downstream and at the side corners.

Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).

26.3.2.2

VSO

Wave soldering techniques can be used for all VSO
packages if the following conditions are observed:

A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

The longitudinal axis of the package footprint must be
parallel to the solder flow.

The package footprint must incorporate solder thieves at
the downstream end.

1997 Apr 15

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART

P80CL31; P80CL51

26.3.2.3

Method (QFP and VSO)

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260

C, and

maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150

C within

6 seconds. Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

26.3.3

EPAIRING SOLDERED JOINTS

Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300

C. When

using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320

27 DEFINITIONS

28 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

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Date of release: 1997 Apr 15

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