Philips
Semiconductors
82B715
I
2
C bus extender
Preliminary specification
Supesedes data of 1997 Apr 07
IC20 Data Handbook
1998 Jan 09
INTEGRATED CIRCUITS
Philips Semiconductors
Preliminary specification
82B715
I
2
C bus extender
2
1998 Jan 09
DESCRIPTION
The 82B715 is a bipolar integrated circuit intended for application in
I
2
C bus systems.
While retaining all the operating modes and features of the I
2
C
system it permits extension of the practical separation distance
between components on the I
2
C bus by buffering both the data
(SDA) and the clock (SCL) lines.
The I
2
C bus capacitance limit of 400pF restricts practical
communication distances to a few meters. Using one 82B715 at
each end of longer cables reduces the cable loading capacitance on
the I
2
C bus by a factor of 10 times and may allow the use of low
cost general purpose wiring to extend bus lengths.
FEATURES
Dual, bi-directional, unity voltage gain buffer
I
2
C bus compatible
Logic signal levels may include both supply and ground
X10 impedance transformation
Wide supply voltage range
PIN CONFIGURATIONS
1
2
3
4
N.C.
GND
SX
LY
SY
N.C.
5
6
7
8
VCC
8-Pin Dual In-Line or SO
82B715
LX
SU00290
PINNING
PIN
SYMBOL
FUNCTION
1
N.C.
2
L
X
Buffered Bus, LDA or LCL
3
S
X
I
2
C Bus, SDA or SCL
4
GND
Negative Supply
5
N.C.
6
S
Y
I
2
C Bus, SCL or SDA
7
L
Y
Buffered Bus, LCL or LDA
8
V
CC
Positive Supply
QUICK REFERENCE DATA
LIMITS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
V
CC
Supply voltage
4.5
12
V
I
CC
Quiescent current
16
mA
I
line
Output sink capability
30
mA
V
in
Input voltage range
0
V
CC
V
V
out
Output voltage range
0
V
CC
V
Z
in
/Z
out
Impedance transformation
8
10
13
T
amb
Temperature range
40
+85
C
ORDERING INFORMATION
DESCRIPTION
ORDER CODE
DRAWING NUMBER
8-pin plastic dual In-line package
P82B715P N
SOT97-1
8-pin plastic small outline package
P82B715T D
SOT96-1
NOTE:
1. For applications requiring, 3V operation and additional buffer performance, see P82B96 Data Sheet.
Philips Semiconductors
Preliminary specification
82B715
I
2
C bus extender
1998 Jan 09
3
BUFFER
BUFFER
82B715
VCC
LDA
LCL
GND
SCL
SDA
SU00291
Figure 1. Block Diagram: 82B715
Philips Semiconductors
Preliminary specification
82B715
I
2
C bus extender
1998 Jan 09
4
FUNCTIONAL DESCRIPTION
The 82B715 bipolar integrated circuit contains two identical buffer
circuits which enable I
2
C and similar bus systems to be extended
over long distances without degradation of system performance or
requiring the use of special cables.
The buffer has an effective current gain of ten from I
2
C bus to
Buffered bus. Whatever current is flowing out of the I
2
C bus side,
ten times that current will be flowing into the Buffered bus side (see
Figure 2).
As a consequence of this amplification the system is able to drive
capacitive loads up to ten times the standard limit on the Buffered
bus side. This current based buffering approach preserves the
bi-directional, open-collector/open-drain characteristic of the I
2
C
SDA/SCL lines.
To minimize interference and ensure stability, current rise and fall
rates are internally controlled.
APPLICATION NOTES
By using two (or more) 82B715 ICs, a sub-system can be built which
retains the interface characteristics of an I
2
C device so that it may
be included in, or optionally added to, any I
2
C or related system.
The sub-system features a low impedance or "Buffered" bus,
capable of driving large wiring capacities (see Figure 3).
I
2
C Systems
As with the standard I
2
C system, pull-up resistors are required to
aprovide the logic HIGH levels on the Buffered bus. (Standard
open-collector configuration of the I
2
C bus). The size and number of
these pull-up resistors depends on the system.
If the buffer is to be permanently connected into the system, the
circuit should be configured with only one pull-up resistor on the
Buffered bus and none on the I
2
C bus.
Alternatively a buffer may be connected to an existing I
2
C system. In
this case the Buffered bus pull-up will act in parallel with the I
2
C bus
pull-up.
CURRENT
SENSE
VCC
10 (IB)
BUFFERED BUS
LX
I2C BUS
SX
IB
GND
SU00292
Figure 2. Equivalent Circuit: One Half 82B715
1/2
1/2
SDA
SCL
STANDARD
I2C
INTERFACE
BUFFERED
INTERFACE
VCC
VCC
LONG
CABLE
1/2
1/2
BUFFERED
INTERFACE
LDA
82B715
82B715
LCL
SDA
SCL
STANDARD
I2C
INTERFACE
I2C
DEVICE
SU00293
Figure 3. Minimum Sub-System with 82B715
Philips Semiconductors
Preliminary specification
82B715
I
2
C bus extender
1998 Jan 09
5
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134).
Voltages with respect to pin GND (DIL-8 pin 4).
LIMITS
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
V
CC
to GND
Supply voltage range V
CC
0.3
+12
V
V
bus
Voltage range I
2
C Bus, SCL or SDA
0
V
CC
V
V
buff
Voltage range Buffered Bus
0
V
CC
V
I
DC current (any pin)
60
mA
P
tot
Power dissipation
300
mW
T
stg
Storage temperature range
55
+125
C
T
amb
Operating ambient temperature range
40
+85
C
CHARACTERISTICS
At T
amb
= +25
C and V
CC
= 5 Volts, unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Power Supply
V
CC
Supply voltage (operating)
4.5
--
12
V
I
CC
Supply current
--
16
--
mA
I
CC
Supply current at V
CC
= 12V
--
22
--
mA
I
CC
Supply current, both I
2
C inputs LOW,
both buffered outputs sinking 30mA.
--
28
--
mA
Drive Currents
I
Sx
, I
Sy
Output sink on I
2
C bus
V
Sx
, V
Sy
LOW = 0.4V
V
Lx
, V
Ly
LOW on Buffered bus = 0.3V
3
--
--
mA
I
Lx
, I
Ly
Output sink on Buffered bus
V
Lx
, V
Ly
LOW = 0.4V
V
Sx
, V
Sy
LOW on I
2
C bus = 0.3V
30
--
--
mA
Input Currents
I
Sx
, I
Sy
Input current from I
2
C bus when
I
Lx
, I
Ly
sink on Buffered bus = 30mA
--
--
3
mA
I
Lx
, I
Ly
Input current from Buffered bus when
I
Sx
, I
Sy
sink on I
2
C bus = 3mA
--
--
3
mA
I
Lx
, I
Ly
Leakage current on Buffered bus
V
Lx
, V
Ly
= V
CC
, and V
Sx
, V
Sy
= V
CC
--
--
200
A
Impedance Transformation
Z
in
/Z
out
Input/Output impedance
8
10
13
Pull-Up Resistance Calculation
In calculating the pull-up resistance values, the gain of the buffer
introduces scaling factors which must be applied to the system
components. Viewing the system from the Buffered bus, all I
2
C bus
capacitances have effectively 10 times their I
2
C bus value.
In practical systems the pull-up resistance is determined by the rise
time limit for I
2
C systems. As an approximation this limit will be
satisfied if the time constant (product of the net resistance and net
capacitance) of the total system is set to 1 microsecond.
The total time constant may either be set by considering each bus
node individually (i.e., the I
2
C nodes, and the Buffered bus node)
and choosing pull-up resistors to give time constants of 1
microsecond for each node; or by combining the capacitances into
an equivalent capacitive loading on the Buffered bus, and
calculating the Buffered bus pull-up resistor required by this
equivalent capacitance.
For each separate bus the pull-up resistor may be calculated as
follows:
R
+
1
m
sec
C
device
)
C
wiring
Where: C
device
= sum of device capacitances connected to each
bus,
and C
wiring
= total wiring and stray capacitance on each bus.
If these capacitances are not known then a good approximation is to
assume that each device presents 10pF of load capacitance and
10pF of wiring capacitance.
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