Philips Semiconductors
Product data
P89C660/P89C662/P89C664/
P89C668
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM
2
2002 Oct 28
853-2392 29118
DESCRIPTION
The P89C660/662/664/668 device contains a non-volatile
16KB/32KB/64KB Flash program memory that is both parallel
programmable and serial In-System and In-Application
Programmable. In-System Programming (ISP) allows the user to
download new code while the microcontroller sits in the application.
In-Application Programming (IAP) means that the microcontroller
fetches new program code and reprograms itself while in the
system. This allows for remote programming over a modem link.
A default serial loader (boot loader) program in ROM allows serial
In-System Programming of the Flash memory via the UART without
the need for a loader in the Flash code. For In-Application
Programming, the user program erases and reprograms the Flash
memory by use of standard routines contained in ROM.
This device executes one instruction in 6 clock cycles, hence
providing twice the speed of a conventional 80C51. An OTP
configuration bit gives the user the option to select conventional
12-clock timing.
This device is a Single-Chip 8-Bit Microcontroller manufactured in
advanced CMOS process and is a derivative of the 80C51
microcontroller family. The instruction set is 100% executing and
timing compatible with the 80C51 instruction set.
The device also has four 8-bit I/O ports, three 16-bit timer/event
counters, a multi-source, four-priority-level, nested interrupt
structure, an enhanced UART and on-chip oscillator and timing
circuits.
The added features of the P89C660/662/664/668 makes it a
powerful microcontroller for applications that require pulse width
modulation, high-speed I/O and up/down counting capabilities such
as motor control.
FEATURES
80C51 Central Processing Unit
On-chip Flash program memory with In-System Programming
(ISP) and In-Application Programming (IAP) capability
Boot ROM contains low level Flash programming routines for
downloading via the UART
Can be programmed by the end-user application (IAP)
Parallel programming with 87C51 compatible hardware interface
to programmer
Six clocks per machine cycle operation (standard)
12 clocks per machine cycle operation (optional)
Speed up to 20 MHz with 6 clock cycles per machine cycle
(40 MHz equivalent performance); up to 33 MHz with 12 clocks
per machine cycle
Fully static operation
RAM externally expandable to 64 kbytes
Four interrupt priority levels
Eight interrupt sources
Four 8-bit I/O ports
Full-duplex enhanced UART
Framing error detection
Automatic address recognition
Power control modes
Clock can be stopped and resumed
Idle mode
Power-Down mode
Programmable clock out
Second DPTR register
Asynchronous port reset
Low EMI (inhibit ALE)
I
2
C serial interface
Programmable Counter Array (PCA)
PWM
Capture/compare
Well-suited for IPMI applications
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