P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core
1 kB 3 V Flash with 128-byte RAM

Rev. 04 -- 21 November 2003

Product data

General description

The P89LPC901/902/903 are single-chip microcontrollers in low-cost 8-pin packages,
based on a high performance processor architecture that executes instructions in two
to four clocks, six times the rate of standard 80C51 devices. Many system-level
functions have been incorporated into the P89LPC901/902/903 in order to reduce
component count, board space, and system cost.

Features

2.1 Principal features

1 kB byte-erasable Flash code memory organized into 256-byte sectors and
16-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile
data storage.

128-byte RAM data memory.

Two 16-bit counter/timers. (P89LPC901 Timer 0 may be configured to toggle a
port output upon timer overflow or to become a PWM output.)

23-bit system timer that can also be used as a Real-Time clock.

Two analog comparators (P89LPC902 and P89LPC903, single analog
comparator on P89LPC901).

Enhanced UART with fractional baudrate generator, break detect, framing error
detection, automatic address detection and versatile interrupt capabilities
(P89LPC903).

High-accuracy internal RC oscillator option allows operation without external
oscillator components. The RC oscillator option is selectable and fine tunable.

2.4 V to 3.6 V V

operating range with 5 V tolerant I/O pins (may be pulled up or

driven to 5.5 V). Industry-standard pinout with V

, V

, and reset at locations 1,

8, and 4.

Up to six I/O pins when using internal oscillator and reset options.

8-pin SO-8 package.

2.2 Additional features

A high performance 80C51 CPU provides instruction cycle times of 167 ns to
333 ns for all instructions except multiply and divide when executing at 12 MHz.
This is six times the performance of the standard 80C51 running at the same
clock frequency. A lower clock frequency for the same performance results in
power savings and reduced EMI.

In-Application Programming (IAP-Lite) and byte erase allows code memory to be
used for non-volatile data storage.

Philips Semiconductors

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 04 -- 21 November 2003

2 of 55

9397 750 12293

Serial Flash In-Circuit Programming (ICP) allows simple production coding with
commercial EPROM programmers. Flash security bits prevent reading of sensitive
application programs.

Watchdog timer with separate on-chip oscillator, requiring no external
components. The watchdog prescaler is selectable from 8 values.

Low voltage reset (Brownout detect) allows a graceful system shutdown when
power fails. May optionally be configured as an interrupt.

Idle and two different Power-down reduced power modes. Improved wake-up from
Power-down mode (a low interrupt input starts execution). Typical Power-down
current is 1

A (total Power-down with voltage comparators disabled).

Active-LOW reset. On-chip power-on reset allows operation without external reset
components. A reset counter and reset glitch suppression circuitry prevent
spurious and incomplete resets. A software reset function is also available.

Configurable on-chip oscillator with frequency range options selected by user
programmed Flash configuration bits. Oscillator options support frequencies from
20 kHz to the maximum operating frequency of 12 MHz (P89LPC901).

Watchdog timer with separate on-chip oscillator, requiring no external
components. The watchdog prescaler is selectable from 8 values.

Programmable port output configuration options: quasi-bidirectional, open drain,
push-pull, input-only.

Port `input pattern match' detect. Port 0 may generate an interrupt when the value
of the pins match or do not match a programmable pattern.

LED drive capability (20 mA) on all port pins. A maximum limit is specified for the
entire chip.

Controlled slew rate port outputs to reduce EMI. Outputs have approximately
10 ns minimum ramp times.

Only power and ground connections are required to operate the
P89LPC901/902/903 when internal reset option is selected.

Four interrupt priority levels.

Two (P89LPC901), three (P89LPC903), or five (P89LPC902) keypad interrupt
inputs.

Second data pointer.

Schmitt trigger port inputs.

Emulation support.

Philips Semiconductors

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 04 -- 21 November 2003

7 of 55

9397 750 12293

Pinning information

5.1 Pinning

Fig 4.

P89LPC901 pinning (SO8).

handbook, halfpage

002aaa438

P89LPC901FD

VSS

P0.4/CIN1A/KBI4

P0.5/CMPREF/KBI5

P1.2/T0

VDD

XTAL1/P3.1

CLKOUT/XTAL2/P3.0

RST/P1.5

Fig 5.

P89LPC901 pinning (DIP8).

handbook, halfpage

002aaa469

P89LPC901FN

VDD

XTAL1/P3.1

CLKOUT/XTAL2/P3.0

RST/P1.5

VSS

P0.4/CIN1A/KBI4

P0.5/CMPREF/KBI5

P1.2/T0

Fig 6.

P89LPC902 pinning (SO8).

handbook, halfpage

002aaa439

P89LPC902FD

VSS

P0.4/CIN1A/KBI4

P0.5/CMPREF/KBI5

P0.6/CMP1/KBI6

VDD

P0.2/CIN2A/KBI2

P0.0/CMP2/KBI0

RST/P1.5

Fig 7.

P89LPC902 pinning (DIP8).

handbook, halfpage

002aaa470

P89LPC902FN

VDD

P0.2/CIN2A/KBI2

P0.0/CMP2/KBI0

RST/P1.5

VSS

P0.4/CIN1A/KBI4

P0.5/CMPREF/KBI5

P0.6/CMP1/KBI6

Philips Semiconductors

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 04 -- 21 November 2003

8 of 55

9397 750 12293

5.2 Pin description

Fig 8.

P89LPC903 pinning (SO8).

handbook, halfpage

002aaa440

P89LPC903FD

VSS

P0.4/CIN1A/KBI4

P0.5/CMPREF/KBI5

P1.0/TxD

VDD

P0.2/CIN2A/KBI2

P1.1/RxD

RST/P1.5

Table 3:

P89LPC901 pin description

Symbol

Pin

Type

Description

P0.0 - P0.6

6, 7

I/O

Port 0: Port 0 is an I/O port with a user-configurable output type. During reset Port 0
latches are configured in the input only mode with the internal pull-up disabled. The
operation of Port 0 pins as inputs and outputs depends upon the port configuration
selected. Each port pin is configured independently. Refer to

Section 8.12.1 "Port

configurations"

and

Table 13 "DC electrical characteristics"

for details.

The Keypad Interrupt feature operates with Port 0 pins.

All pins have Schmitt triggered inputs.

Port 0 also provides various special functions as described below:

I/O

P0.4 -- Port 0 bit 4.

CIN1A -- Comparator 1 positive input.

KBI4 -- Keyboard input 4.

I/O

P0.5 -- Port 0 bit 5.

CMPREF -- Comparator reference (negative) input.

KBI5 -- Keyboard input 5.

P1.0 - P1.5

4, 5

Port 1: Port 1 is an I/O port with a user-configurable output type. During reset Port 1
latches are configured in the input only mode with the internal pull-up disabled. The
operation of the configurable Port 1 pins as inputs and outputs depends upon the
port configuration selected. Each of the configurable port pins are programmed
independently. Refer to

Section 8.12.1 "Port configurations"

and

Table 13 "DC

electrical characteristics"

for details. P1.5 is input only.

All pins have Schmitt triggered inputs.

Port 1 also provides various special functions as described below:

I/O

P1.2 -- Port 1 bit 2.

T0 -- Timer/counter 0 external count input or overflow output.

P1.5 -- Port 1 bit 5 (input only).

RST -- External Reset input during Power-on or if selected via UCFG1. When
functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O
ports and peripherals to take on their default states, and the processor begins
execution at address 0. Also used during a power-on sequence to force In-System
Programming mode.

Philips Semiconductors

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 04 -- 21 November 2003

9 of 55

9397 750 12293

P3.0 - P3.1

2, 3

I/O

Port 3: Port 3 is an I/O port with a user-configurable output types. During reset Port 3
latches are configured in the input only mode with the internal pull-up disabled. The
operation of port 3 pins as inputs and outputs depends upon the port configuration
selected. Each port pin is configured independently. Refer to

Section 8.12.1 "Port

configurations"

and

Table 13 "DC electrical characteristics"

for details.

All pins have Schmitt triggered inputs.

Port 3 also provides various special functions as described below:

I/O

P3.0 -- Port 3 bit 0.

XTAL2 -- Output from the oscillator amplifier (when a crystal oscillator option is
selected via the FLASH configuration).

CLKOUT -- CPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6). It
can be used if the CPU clock is the internal RC oscillator, Watchdog oscillator or
external clock input, except when XTAL1/XTAL2 are used to generate clock source
for the real time clock/system timer.

I/O

P3.1 -- Port 3 bit 1.

XTAL1 -- Input to the oscillator circuit and internal clock generator circuits (when
selected via the FLASH configuration). It can be a port pin if internal RC oscillator or
Watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not
used to generate the clock for the real time clock/system timer.

Ground: 0 V reference.

Power Supply: This is the power supply voltage for normal operation as well as Idle
and Power-down modes.

Table 3:

P89LPC901 pin description

...continued

Symbol

Pin

Type

Description

Philips Semiconductors

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 04 -- 21 November 2003

10 of 55

9397 750 12293

Table 4:

P89LPC902 pin description

Symbol

Pin

Type

Description

P0.0 - P0.6

2, 3, 5, 6,
7

I/O

Section 8.12.1 "Port

configurations"

and

Table 13 "DC electrical characteristics"

for details.

The Keypad Interrupt feature operates with Port 0 pins.

All pins have Schmitt triggered inputs.

Port 0 also provides various special functions as described below:

I/O

P0.0 -- Port 0 bit 0.

CMP2 -- Comparator 2 output.

KBI0 -- Keyboard input 0.

I/O

P0.2 -- Port 0 bit 2.

CIN2A -- Comparator 2 positive input.

KBI2 -- Keyboard input 2.

I/O

P0.4 -- Port 0 bit 4.

CIN1A -- Comparator 1 positive input.

KBI4 -- Keyboard input 4.

I/O

P0.5 -- Port 0 bit 5.

CMPREF -- Comparator reference (negative) input.

KBI5 -- Keyboard input 5.

I/O

P0.6 -- Port 0 bit 6.

CMP1 -- Comparator 1 output.

KBI6 -- Keyboard input 6.

P1.0 - P1.5

Section 8.12.1 "Port configurations"

and

Table 13 "DC

electrical characteristics"

for details. P1.5 is input only.

All pins have Schmitt triggered inputs.

Port 1 also provides various special functions as described below:

P1.5 -- Port 1 bit 5 (input only).

Ground: 0 V reference.

Power Supply: This is the power supply voltage for normal operation as well as Idle
and Power-down modes.

Philips Semiconductors

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 04 -- 21 November 2003

11 of 55

9397 750 12293

Table 5:

P89LPC903 pin description

Symbol

Pin

Type

Description

P0.0 - P0.6

2, 6, 7

I/O

Section 8.12.1 "Port

configurations"

and

Table 13 "DC electrical characteristics"

for details.

The Keypad Interrupt feature operates with Port 0 pins.

All pins have Schmitt triggered inputs.

Port 0 also provides various special functions as described below:

I/O

P0.2 -- Port 0 bit 2.

CIN2A -- Comparator 2 positive input.

KBI2 -- Keyboard input 2.

I/O

P0.4 -- Port 0 bit 4.

CIN1A -- Comparator 1 positive input.

KBI4 -- Keyboard input 4.

I/O

P0.5 -- Port 0 bit 5.

CMPREF -- Comparator reference (negative) input.

KBI5 -- Keyboard input 5.

P1.0 - P1.5

3, 4, 5

Section 8.12.1 "Port configurations"

and

Table 13 "DC

electrical characteristics"

for details. P1.5 is input only.

All pins have Schmitt triggered inputs.

Port 1 also provides various special functions as described below:

I/O

P1.0 -- Port 1 bit 0.

TxD -- Serial port transmitter data.

I/O

P1.1 -- Port 1 bit 1.

RxD -- Serial port receiver data.

P1.5 -- Port 1 bit 5 (input only).

Ground: 0 V reference.

Power Supply: This is the power supply voltage for normal operation as well as Idle
and Power-down modes.

Philips Semiconductors

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 04 -- 21 November 2003

14 of 55

9397 750 12293

Special function registers

Remark: Special Function Registers (SFRs) accesses are restricted in the following
ways:

User must not attempt to access any SFR locations not defined.

Accesses to any defined SFR locations must be strictly for the functions for the
SFRs.

SFR bits labeled `-', `0' or `1' can only be written and read as follows:

`-' Unless otherwise specified, must be written with `0', but can return any value

when read (even if it was written with `0'). It is a reserved bit and may be used in
future derivatives.

`0' must be written with `0', and will return a `0' when read.

`1' must be written with `1', and will return a `1' when read.

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

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P89LPC901/902/903

8-bit micr

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Table 7:

P89LPC901 Special function registers

* indicates SFRs that are bit addressable.

Name

Description

SFR
addr.

Bit functions and addresses

Reset value

MSB

LSB

Hex

Binary

Bit address

ACC*

Accumulator

E0H

00000000

AUXR1

Auxiliary function register

A2H

CLKLP

ENT0

SRST

DPS

[1]

000000x0

Bit address

B register

F0H

00000000

CMP1

Comparator 1 control register

ACH

CE1

CN1

CO1

CMF1

[1]

xx000000

DIVM

CPU clock divide-by-M
control

95H

00000000

DPTR

Data pointer (2 bytes)

DPH

Data pointer HIGH

83H

00000000

DPL

Data pointer LOW

82H

00000000

FMADRH

Program Flash address HIGH

E7H

00000000

FMADRL

Program Flash address LOW

E6H

00000000

FMCON

Program Flash Control
(Read)

E4H

BUSY

HVA

HVE

01110000

Program Flash Control
(Write)

FMCMD.

FMDATA

Program Flash data

E5H

00000000

IEN0*

Interrupt enable 0

A8H

EWDRT

EBO

ET1

ET0

00000000

Bit address

IEN1*

Interrupt enable 1

E8H

EKBI

[1]

00x00000

Bit address

IP0*

Interrupt priority 0

B8H

PWDRT

PBO

PT1

PT0

[1]

x0000000

IP0H

Interrupt priority 0 HIGH

B7H

PWDRT

PBOH

PT1H

PT0H

[1]

x0000000

Bit address

IP1*

Interrupt priority 1

F8H

PKBI

[1]

00x00000

IP1H

Interrupt priority 1 HIGH

F7H

PCH

PKBIH

[1]

00x00000

KBCON

Keypad control register

94H

PATN
_SEL

KBIF

[1]

xxxxxx00

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KBMASK

Keypad interrupt mask
register

86H

00000000

KBPATN

Keypad pattern register

93H

11111111

Bit address

P0*

Port 0

80H

CMPREF

/KB5

CIN1A

/KB4

[1]

Bit address

P1*

Port 1

90H

RST

[1]

Bit address

P3*

Port 3

B0H

XTAL1

XTAL2

[1]

P0M1

Port 0 output mode 1

84H

(P0M1.5) (P0M1.4)

11111111

P0M2

Port 0 output mode 2

85H

(P0M2.5) (P0M2.4)

00000000

P1M1

Port 1 output mode 1

91H

(P1M1.5)

(P1M1.2)

[1]

11111111

P1M2

Port 1 output mode 2

92H

(P1M2.5)

(P1M2.2)

[1]

00000000

P3M1

Port 3 output mode 1

B1H

(P3M1.1) (P3M1.0) 03

[1]

xxxxxx11

P3M2

Port 3 output mode 2

B2H

(P3M2.1) (P3M2.0) 00

[1]

xxxxxx00

PCON

Power control register

87H

BOPD

BOI

GF1

GF0

PMOD1

PMOD0

00000000

PCONA

Power control register A

B5H

RTCPD

VCPD

[1]

00000000

PCONB

reserved for Power Control
Register B

B6H

[1]

xxxxxxxx

Bit address

PSW*

Program status word

D0H

RS1

RS0

00000000

PT0AD

Port 0 digital input disable

F6H

PT0AD.5

PT0AD.4

xx00000x

RSTSRC

Reset source register

DFH

BOF

POF

R_WD

R_SF

R_EX

[3]

RTCCON

Real-time clock control

D1H

RTCF

RTCS1

RTCS0

ERTC

RTCEN

[1]

[6]

011xxx00

RTCH

Real-time clock register HIGH

D2H

[6]

00000000

RTCL

Real-time clock register LOW

D3H

[6]

00000000

Stack pointer

81H

00000111

TAMOD

Timer 0 auxiliary mode

8FH

T0M2

xxx0xxx0

Table 7:

P89LPC901 Special function registers

...continued

* indicates SFRs that are bit addressable.

Name

Description

SFR
addr.

Bit functions and addresses

Reset value

MSB

LSB

Hex

Binary

Philips Semiconductor

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[1]

All ports are in input only (high impedance) state after power-up.

[2]

BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is `0'. If any are written while BRGEN = 1, the result is unpredictable.

Unimplemented bits in SFRs (labeled '-') are X (unknown) at all times. Unless otherwise specified, ones should not be written to these bits since they may be used for other
purposes in future derivatives. The reset values shown for these bits are `0's although they are unknown when read.

[3]

The RSTSRC register reflects the cause of the P89LPC901/902/903 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset
value is xx110000.

[4]

After reset, the value is 111001x1, i.e., PRE2-PRE0 are all `1', WDRUN = 1 and WDCLK = 1. WDTOF bit is `1' after Watchdog reset and is `0' after power-on reset. Other resets will
not affect WDTOF.

[5]

On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6]

The only reset source that affects these SFRs is power-on reset.

Bit address

TCON*

Timer 0 and 1 control

88H

TF1

TR1

TF0

TR0

00000000

TH0

Timer 0 HIGH

8CH

00000000

TH1

Timer 1 HIGH

8DH

00000000

TL0

Timer 0 LOW

8AH

00000000

TL1

Timer 1 LOW

8BH

00000000

TMOD

Timer 0 and 1 mode

89H

T1M1

T1M0

T0M1

T0M0

00000000

TRIM

Internal oscillator trim register

96H

TRIM.5

TRIM.4

TRIM.3

TRIM.2

TRIM.1

TRIM.0

[5] [6]

WDCON

Watchdog control register

A7H

PRE2

PRE1

PRE0

WDRUN

WDTOF

WDCLK

[4] [6]

WDL

Watchdog load

C1H

11111111

WFEED1

Watchdog feed 1

C2H

WFEED2

Watchdog feed 2

C3H

Table 7:

P89LPC901 Special function registers

...continued

* indicates SFRs that are bit addressable.

Name

Description

SFR
addr.

Bit functions and addresses

Reset value

MSB

LSB

Hex

Binary

Philips Semiconductor

P89LPC901/902/903

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Table 8:

P89LPC902 Special function registers

* indicates SFRs that are bit addressable.

Name

Description

SFR
addr.

Bit functions and addresses

Reset value

MSB

LSB

Hex

Binary

Bit address

ACC*

Accumulator

E0H

00000000

AUXR1

Auxiliary function register

A2H

SRST

DPS

[1]

000000x0

Bit address

B register

F0H

00000000

CMP1

Comparator 1 control register

ACH

CE1

CN1

OE1

CO1

CMF1

[1]

xx000000

CMP2

Comparator 2 control register

ADH

CE2

CN2

OE2

CO2

CMF2

[1]

xx000000

DIVM

CPU clock divide-by-M
control

95H

00000000

DPTR

Data pointer (2 bytes)

DPH

Data pointer HIGH

83H

00000000

DPL

Data pointer LOW

82H

00000000

FMADRH

Program Flash address HIGH

E7H

00000000

FMADRL

Program Flash address LOW

E6H

00000000

FMCON

Program Flash Control
(Read)

E4H

BUSY

HVA

HVE

01110000

Program Flash Control
(Write)

FMCMD.

FMDATA

Program Flash data

E5H

00000000

IEN0*

Interrupt enable 0

A8H

EWDRT

EBO

ET1

ET0

00000000

Bit address

IEN1*

Interrupt enable 1

E8H

EKBI

[1]

00x00000

Bit address

IP0*

Interrupt priority 0

B8H

PWDRT

PBO

PT1

PT0

[1]

x0000000

IP0H

Interrupt priority 0 HIGH

B7H

PWDRT

PBOH

PT1H

PT0H

[1]

x0000000

Bit address

IP1*

Interrupt priority 1

F8H

PKBI

[1]

00x00000

IP1H

Interrupt priority 1 HIGH

F7H

PCH

PKBIH

[1]

00x00000

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KBCON

Keypad control register

94H

PATN
_SEL

KBIF

[1]

xxxxxx00

KBMASK

Keypad interrupt mask
register

86H

00000000

KBPATN

Keypad pattern register

93H

11111111

Bit address

P0*

Port 0

80H

CMP1

/KB6

CMPREF

/KB5

CIN1A

/KB4

KB2

KB0

[1]

Bit address

P1*

Port 1

90H

RST

Bit address

P0M1

Port 0 output mode 1

84H

(P0M1.6) (P0M1.5) (P0M1.4)

(P0M1.2)

(P0M1.0) FF

11111111

P0M2

Port 0 output mode 2

85H

(P0M2.6) (P0M2.5) (P0M2.4)

(P0M2.2)

(P0M2.0) 00

00000000

P1M1

Port 1 output mode 1

91H

(P1M1.5)

[1]

11111111

P1M2

Port 1 output mode 2

92H

(P1M2.5)

[1]

00000000

PCON

Power control register

87H

BOPD

BOI

GF1

GF0

PMOD1

PMOD0

00000000

PCONA

Power control register A

B5H

RTCPD

VCPD

[1]

00000000

PCONB

reserved for Power Control
Register B

B6H

[1]

xxxxxxxx

Bit address

PSW*

Program status word

D0H

RS1

RS0

00000000

PT0AD

Port 0 digital input disable

F6H

PT0AD.5

PT0AD.4

PT0AD.2

xx00000x

RSTSRC

Reset source register

DFH

BOF

POF

R_WD

R_SF

R_EX

[3]

RTCCON

Real-time clock control

D1H

RTCF

RTCS1

RTCS0

ERTC

RTCEN

[1]

[6]

011xxx00

RTCH

Real-time clock register HIGH

D2H

[6]

00000000

RTCL

Real-time clock register LOW

D3H

[6]

00000000

Stack pointer

81H

00000111

Table 8:

P89LPC902 Special function registers

...continued

* indicates SFRs that are bit addressable.

Name

Description

SFR
addr.

Bit functions and addresses

Reset value

MSB

LSB

Hex

Binary

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[1]

All ports are in input only (high impedance) state after power-up.

[2]

BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is `0'. If any are written while BRGEN = 1, the result is unpredictable.

[3]

The RSTSRC register reflects the cause of the P89LPC901/902/903 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset
value is xx110000.

[4]

After reset, the value is 111001x1, i.e., PRE2-PRE0 are all `1', WDRUN = 1 and WDCLK = 1. WDTOF bit is `1' after Watchdog reset and is `0' after power-on reset. Other resets will
not affect WDTOF.

[5]

On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6]

The only reset source that affects these SFRs is power-on reset.

Bit address

TCON*

Timer 0 and 1 control

88H

TF1

TR1

TF0

TR0

00000000

TH0

Timer 0 HIGH

8CH

00000000

TH1

Timer 1 HIGH

8DH

00000000

TL0

Timer 0 LOW

8AH

00000000

TL1

Timer 1 LOW

8BH

00000000

TMOD

Timer 0 and 1 mode

89H

T1M1

T1M0

T0M1

T0M0

00000000

TRIM

Internal oscillator trim register

96H

TRIM.5

TRIM.4

TRIM.3

TRIM.2

TRIM.1

TRIM.0

[5] [6]

WDCON

Watchdog control register

A7H

PRE2

PRE1

PRE0

WDRUN

WDTOF

WDCLK

[4] [6]

WDL

Watchdog load

C1H

11111111

WFEED1

Watchdog feed 1

C2H

WFEED2

Watchdog feed 2

C3H

Table 8:

P89LPC902 Special function registers

...continued

* indicates SFRs that are bit addressable.

Name

Description

SFR
addr.

Bit functions and addresses

Reset value

MSB

LSB

Hex

Binary

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Table 9:

P89LPC903 Special function registers

* indicates SFRs that are bit addressable.

Name

Description

SFR
addr.

Bit functions and addresses

Reset value

MSB

LSB

Hex

Binary

Bit address

ACC*

Accumulator

E0H

00000000

AUXR1

Auxiliary function register

A2H

EBRR

SRST

DPS

[1]

000000x0

Bit address

B register

F0H

00000000

BRGR0

[2]

Baud rate generator rate
LOW

BEH

00000000

BRGR1

[2]

Baud rate generator rate
HIGH

BFH

00000000

BRGCON

Baud rate generator control

BDH

SBRGS

BRGEN

[6]

xxxxxx00

CMP1

Comparator 1 control register

ACH

CE1

CN1

CO1

CMF1

[1]

xx000000

CMP2

Comparator 2 control register

ADH

CE2

CN2

CO2

CMF2

[1]

xx000000

DIVM

CPU clock divide-by-M
control

95H

00000000

DPTR

Data pointer (2 bytes)

DPH

Data pointer HIGH

83H

00000000

DPL

Data pointer LOW

82H

00000000

FMADRH

Program Flash address HIGH

E7H

00000000

FMADRL

Program Flash address LOW

E6H

00000000

FMCON

Program Flash Control
(Read)

E4H

BUSY

HVA

HVE

01110000

Program Flash Control
(Write)

FMCMD.

FMDATA

Program Flash data

E5H

00000000

IEN0*

Interrupt enable 0

A8H

EWDRT

EBO

ES/ESR

ET1

ET0

00000000

Bit address

IEN1*

Interrupt enable 1

E8H

EST

EKBI

[1]

00x00000

Bit address

IP0*

Interrupt priority 0

B8H

PWDRT

PBO

PS/PSR

PT1

PT0

[1]

x0000000

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IP0H

Interrupt priority 0 HIGH

B7H

PWDRT

PBOH

PSH

/PSRH

PT1H

PT0H

[1]

x0000000

Bit address

IP1*

Interrupt priority 1

F8H

PST

PKBI

[1]

00x00000

IP1H

Interrupt priority 1 HIGH

F7H

PSTH

PCH

PKBIH

[1]

00x00000

KBCON

Keypad control register

94H

PATN
_SEL

KBIF

[1]

xxxxxx00

KBMASK

Keypad interrupt mask
register

86H

00000000

KBPATN

Keypad pattern register

93H

11111111

Bit address

P0*

Port 0

80H

CMPREF

/KB5

CIN1A

/KB4

KB2

[1]

Bit address

P1*

Port 1

90H

RST

RxD

TxD

P0M1

Port 0 output mode 1

84H

(P0M1.5) (P0M1.4)

(P0M1.2)

11111111

P0M2

Port 0 output mode 2

85H

(P0M2.5) (P0M2.4)

(P0M2.2)

00000000

P1M1

Port 1 output mode 1

91H

(P1M1.5)

(P1M1.1) (P1M1.0) FF

[1]

11111111

P1M2

Port 1 output mode 2

92H

(P1M2.5)

(P1M2.1) (P1M2.0) 00

[1]

00000000

PCON

Power control register

87H

SMOD1

SMOD0

BOPD

BOI

GF1

GF0

PMOD1

PMOD0

00000000

PCONA

Power control register A

B5H

RTCPD

VCPD

SPD

[1]

00000000

PCONB

reserved for Power Control
Register B

B6H

[1]

xxxxxxxx

Bit address

PSW*

Program status word

D0H

RS1

RS0

00000000

PT0AD

Port 0 digital input disable

F6H

PT0AD.5

PT0AD.4

PT0AD.2

xx00000x

RSTSRC

Reset source register

DFH

BOF

POF

R_BK

R_WD

R_SF

R_EX

[3]

RTCCON

Real-time clock control

D1H

RTCF

RTCS1

RTCS0

ERTC

RTCEN

[1]

[6]

011xxx00

RTCH

Real-time clock register HIGH

D2H

[6]

00000000

Table 9:

P89LPC903 Special function registers

...continued

* indicates SFRs that are bit addressable.

Name

Description

SFR
addr.

Bit functions and addresses

Reset value

MSB

LSB

Hex

Binary

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[1]

All ports are in input only (high impedance) state after power-up.

[2]

BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is `0'. If any are written while BRGEN = 1, the result is unpredictable.

[3]

The RSTSRC register reflects the cause of the P89LPC901/902/903 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset
value is xx110000.

[4]

After reset, the value is 111001x1, i.e., PRE2-PRE0 are all `1', WDRUN = 1 and WDCLK = 1. WDTOF bit is `1' after Watchdog reset and is `0' after power-on reset. Other resets will
not affect WDTOF.

[5]

On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6]

The only reset source that affects these SFRs is power-on reset.

RTCL

Real-time clock register LOW

D3H

[6]

00000000

SADDR

Serial port address register

A9H

00000000

SADEN

Serial port address enable

B9H

00000000

SBUF

Serial port data buffer register

99H

xxxxxxxx

Bit address

SCON*

Serial port control

98H

SM0/FE

SM1

SM2

REN

TB8

RB8

00000000

SSTAT

Serial port extended status
register

BAH

DBMOD

INTLO

CIDIS

DBISEL

STINT

00000000

Stack pointer

81H

00000111

Bit address

TCON*

Timer 0 and 1 control

88H

TF1

TR1

TF0

TR0

00000000

TH0

Timer 0 HIGH

8CH

00000000

TH1

Timer 1 HIGH

8DH

00000000

TL0

Timer 0 LOW

8AH

00000000

TL1

Timer 1 LOW

8BH

00000000

TMOD

Timer 0 and 1 mode

89H

T1M1

T1M0

T0M1

T0M0

00000000

TRIM

Internal oscillator trim register

96H

TRIM.5

TRIM.4

TRIM.3

TRIM.2

TRIM.1

TRIM.0

[5] [6]

WDCON

Watchdog control register

A7H

PRE2

PRE1

PRE0

WDRUN

WDTOF

WDCLK

[4] [6]

WDL

Watchdog load

C1H

11111111

WFEED1

Watchdog feed 1

C2H

WFEED2

Watchdog feed 2

C3H

Table 9:

P89LPC903 Special function registers

...continued

* indicates SFRs that are bit addressable.

Name

Description

SFR
addr.

Bit functions and addresses

Reset value

MSB

LSB

Hex

Binary

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Functional description

Remark: Please refer to the

P89LPC901/902/903 User's Manual for a more detailed

functional description.

8.1 Enhanced CPU

The P89LPC901/902/903 uses an enhanced 80C51 CPU which runs at 6 times the
speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles,
and most instructions execute in one or two machine cycles.

8.2 Clocks

8.2.1

Clock definitions

The P89LPC901/902/903 device has several internal clocks as defined below:

OSCCLK -- Input to the DIVM clock divider. OSCCLK is selected from one of the
clock sources (see Figures

, and

) and can also be optionally divided to a

slower frequency (see

Section 8.7 "CPU CLOCK (CCLK) modification: DIVM

Note: f

OSC

is defined as the OSCCLK frequency.

CCLK -- CPU clock; output of the clock divider. There are two CCLK cycles per
machine cycle, and most instructions are executed in one to two machine cycles (two
or four CCLK cycles).

RCCLK -- The internal 7.373 MHz RC oscillator output.

PCLK -- Clock for the various peripheral devices and is CCLK/2

8.2.2

CPU clock (OSCCLK)

The P89LPC901/902/903 provides several user-selectable oscillator options in
generating the CPU clock. This allows optimization for a range of needs from high
precision to lowest possible cost. These options are configured when the FLASH is
programmed and include an on-chip Watchdog oscillator and an on-chip RC
oscillator.

The P89LPC901, in addition, includes an option for an oscillator using an external
crystal or an external clock source. The crystal oscillator can be optimized for low,
medium, or high frequency crystals covering a range from 20 kHz to 12 MHz.

8.2.3

Low speed oscillator option (P89LPC901)

This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic
resonators are also supported in this configuration.

8.2.4

Medium speed oscillator option (P89LPC901)

This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic
resonators are also supported in this configuration.

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8.2.5

High speed oscillator option (P89LPC901)

This option supports an external crystal in the range of 4 MHz to 12 MHz. Ceramic
resonators are also supported in this configuration. If CCLK is 8 MHz or slower, the
CLKLP SFR bit (AUXR1.7) can be set to `1' to reduce power consumption. On reset,
CLKLP is `0' allowing highest performance access. This bit can then be set in
software if CCLK is running at 8 MHz or slower.

8.2.6

Clock output (P89LPC901)

The P89LPC901 supports a user selectable clock output function on the
XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if
another clock source has been selected (on-chip RC oscillator, Watchdog oscillator,
external clock input on X1) and if the Real-Time clock is not using the crystal
oscillator as its clock source. This allows external devices to synchronize to the
P89LPC901. This output is enabled by the ENCLK bit in the TRIM register. The
frequency of this clock output is

that of the CCLK. If the clock output is not needed

in Idle mode, it may be turned off prior to entering Idle, saving additional power.

8.3 On-chip RC oscillator option

The P89LPC901/902/903 has a 6-bit TRIM register that can be used to tune the
frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory
pre-programmed value to adjust the oscillator frequency to 7.373 MHz,

2.5%.

End-user applications can write to the Trim register to adjust the on-chip RC oscillator
to other frequencies. If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can
be set to `1' to reduce power consumption. On reset, CLKLP is `0' allowing highest
performance access. This bit can then be set in software if CCLK is running at 8 MHz
or slower.

8.4 Watchdog oscillator option

The Watchdog has a separate oscillator which has a frequency of 400 kHz. This
oscillator can be used to save power when a high clock frequency is not needed.

8.5 External clock input option (P89LPC901)

In this configuration, the processor clock is derived from an external source driving
the XTAL1/P3.1 pin. The rate may be from 0 Hz up to 12 MHz. The XTAL2/P3.0 pin
may be used as a standard port pin or a clock output.

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Fig 12. Block diagram of oscillator control (P89LPC901).

Fig 13. Block diagram of oscillator control (P89LPC902).

Fig 14. Block diagram of oscillator control (P89LPC903).

002aaa447

RTC

CPU

WDT

DIVM

CCLK

OSCCLK

PCLK

TIMERS 0 & 1

High freq.

Med. freq.

Low freq.

XTAL1

XTAL2

OSCILLATOR

WATCHDOG

OSCILLATOR

(7.3728 MHz)

(400 kHz)

002aaa448

RTC

CPU

WDT

DIVM

CCLK

OSCCLK

PCLK

TIMERS 0 & 1

OSCILLATOR

WATCHDOG

OSCILLATOR

(7.3728 MHz)

(400 kHz)

002aaa449

RTC

CPU

WDT

DIVM

CCLK

OSCCLK

PCLK

TIMERS 0 & 1

OSCILLATOR

WATCHDOG

OSCILLATOR

(7.3728 MHz)

(400 kHz)

BAUD RATE

GENERATOR

UART

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8.6 CPU CLock (CCLK) wake-up delay

The P89LPC901/902/903 has an internal wake-up timer that delays the clock until it
stabilizes depending to the clock source used. If the clock source is any of the three
crystal selections (P89LPC901) the delay is 992 OSCCLK cycles plus 60 to 100

8.7 CPU CLOCK (CCLK) modification: DIVM register

The OSCCLK frequency can be divided down up to 510 times by configuring a
dividing register, DIVM, to generate CCLK. This feature makes it possible to
temporarily run the CPU at a lower rate, reducing power consumption. By dividing the
clock, the CPU can retain the ability to respond to events that would not exit Idle
mode by executing its normal program at a lower rate. This can also allow bypassing
the oscillator start-up time in cases where Power-down mode would otherwise be
used. The value of DIVM may be changed by the program at any time without
interrupting code execution.

8.8 Low power select

The P89LPC901 is designed to run at 12 MHz (CCLK) maximum. However, if CCLK
is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to `1' to lower the power
consumption further. On any reset, CLKLP is `0' allowing highest performance
access. This bit can then be set in software if CCLK is running at 8 MHz or slower.

8.9 Memory organization

The various P89LPC901/902/903 memory spaces are as follows:

DATA

128 bytes of internal data memory space (00h:7Fh) accessed via direct or indirect
addressing, using instruction other than MOVX and MOVC. All or part of the Stack
may be in this area.

SFR

Special Function Registers. Selected CPU registers and peripheral control and
status registers, accessible only via direct addressing.

CODE

64 kB of Code memory space, accessed as part of program execution and via the
MOVC instruction. The P89LPC901/902/903 has 1 kB of on-chip Code memory.

8.10 Data RAM arrangement

The 128 bytes of on-chip RAM is organized as follows:

8.11 Interrupts

The P89LPC901/902/903 uses a four priority level interrupt structure. This allows
great flexibility in controlling the handling of the many interrupt sources.

Table 10:

On-chip data memory usages

Type

Data RAM

Size (Bytes)

DATA

Memory that can be addressed directly and indirectly 128

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The P89LPC901 supports 6 interrupt sources: timers 0 and 1, brownout detect,
Watchdog/real-time clock, keyboard, and the comparator.

The P89LPC902 supports 6 interrupt sources: timers 0 and 1, brownout detect,
Watchdog/real-time clock, keyboard, and comparators 1 and 2.

The P89LPC903 supports 9 interrupt sources: timers 0 and 1, serial port Tx, serial
port Rx, combined serial port Rx/Tx, brownout detect, Watchdog/real-time clock,
keyboard, and comparators 1 and 2.

Each interrupt source can be individually enabled or disabled by setting or clearing a
bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a
global disable bit, EA, which disables all interrupts.

Each interrupt source can be individually programmed to one of four priority levels by
setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An
interrupt service routine in progress can be interrupted by a higher priority interrupt,
but not by another interrupt of the same or lower priority. The highest priority interrupt
service cannot be interrupted by any other interrupt source. If two requests of
different priority levels are pending at the start of an instruction, the request of higher
priority level is serviced.

If requests of the same priority level are pending at the start of an instruction, an
internal polling sequence determines which request is serviced. This is called the
arbitration ranking. Note that the arbitration ranking is only used to resolve pending
requests of the same priority level.

8.11.1

External interrupt inputs

The P89LPC901/902/903 has a Keypad Interrupt function. This can be used as an
external interrupt input.

If enabled when the P89LPC901/902/903 is put into Power-down or Idle mode, the
interrupt will cause the processor to wake-up and resume operation. Refer to

Section

8.14 "Power reduction modes"

for details.

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8.12 I/O ports

The P89LPC901 has between 3 and 6 I/O pins: P0.4, P0.5, P1.2, P1.5, P3.0, and
P3.1 The exact number of I/O pins available depends on the clock and reset options
chosen, as shown in

Table 11

The P89LPC902 and P89LPC903 devices have either 5 or 6 I/O pins depending on
the reset pin option chosen.

8.12.1

Port configurations

All but one I/O port pin on the P89LPC901/902/903 may be configured by software to
one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51
port outputs), push-pull, open drain, and input-only. Two configuration registers for
each port select the output type for each port pin.

P1.5 (RST) can only be an input and cannot be configured.

Fig 17. Interrupt sources, interrupt enables, and power-down wake-up sources (P89LPC903).

002aaa452

BOPD

EBO

KBIF

EKBI

INTERRUPT
TO CPU

WAKE-UP
(IF IN POWER-DOWN)

EWDRT

CMF

EA (IE0.7)

RTCF

ERTC

(RTCCON.1)

WDOVF

TF1

ET1

TI & RI/RI

ES/ESR

EST

TF0

ET0

Table 11:

Number of I/O pins available

Clock source

Reset option

Number of I/O pins
(8-pin package)

On-chip oscillator or Watchdog oscillator

No external reset (except during power-up)

External RST pin supported

External clock input

No external reset (except during power-up)

External RST pin supported

Low/medium/high speed oscillator
(external crystal or resonator)

No external reset (except during power-up)

External RST pin supported

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8.12.2

Quasi-bidirectional output configuration

Quasi-bidirectional output type can be used as both an input and output without the
need to reconfigure the port. This is possible because when the port outputs a logic
HIGH, it is weakly driven, allowing an external device to pull the pin LOW. When the
pin is driven LOW, it is driven strongly and able to sink a fairly large current. These
features are somewhat similar to an open-drain output except that there are three
pull-up transistors in the quasi-bidirectional output that serve different purposes.

The P89LPC901/902/903 is a 3 V device, however, the pins are 5 V-tolerant (except
for XTAL1 and XTAL2). In quasi-bidirectional mode, if a user applies 5 V on the pin,
there will be a current flowing from the pin to V

, causing extra power consumption.

Therefore, applying 5 V in quasi-bidirectional mode is discouraged.

A quasi-bidirectional port pin has a Schmitt-triggered input that also has a glitch
suppression circuit.

8.12.3

Open-drain output configuration

The open-drain output configuration turns off all pull-ups and only drives the
pull-down transistor of the port driver when the port latch contains a logic `0'. To be
used as a logic output, a port configured in this manner must have an external
pull-up, typically a resistor tied to V

An open-drain port pin has a Schmitt-triggered input that also has a glitch
suppression circuit.

8.12.4

Input-only configuration

The input-only port configuration has no output drivers. It is a Schmitt-triggered input
that also has a glitch suppression circuit.

8.12.5

Push-pull output configuration

The push-pull output configuration has the same pull-down structure as both the
open-drain and the quasi-bidirectional output modes, but provides a continuous
strong pull-up when the port latch contains a logic `1'. The push-pull mode may be
used when more source current is needed from a port output. A push-pull port pin
has a Schmitt-triggered input that also has a glitch suppression circuit.

8.12.6

Port 0 analog functions

The P89LPC901/902/903 incorporates an Analog Comparator. In order to give the
best analog function performance and to minimize power consumption, pins that are
being used for analog functions must have the digital outputs and digital inputs
disabled.

Digital outputs are disabled by putting the port output into the Input-Only (high
impedance) mode as described in

Section 8.12.4 "Input-only configuration"

Digital inputs on Port 0 may be disabled through the use of the PT0AD register. On
any reset, the PT0AD bits default to `0's to enable digital functions.

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8.12.7

Additional port features

After power-up, all pins are in Input-Only mode. Please note that this is different
from the LPC76x series of devices.

After power-up all I/O pins, except P1.5, may be configured by software.

Pin P1.5 is input only.

Every output on the P89LPC901/902/903 has been designed to sink typical LED
drive current. However, there is a maximum total output current for all ports which
must not be exceeded. Please refer to

Table 13 "DC electrical characteristics"

for

detailed specifications.

All ports pins that can function as an output have slew rate controlled outputs to limit
noise generated by quickly switching output signals. The slew rate is factory-set to
approximately 10 ns rise and fall times.

8.13 Power monitoring functions

The P89LPC901/902/903 incorporates power monitoring functions designed to
prevent incorrect operation during initial power-up and power loss or reduction during
operation. This is accomplished with two hardware functions: Power-on Detect and
Brownout detect.

8.13.1

Brownout detection

The Brownout detect function determines if the power supply voltage drops below a
certain level. The default operation is for a Brownout detection to cause a processor
reset, however, it may alternatively be configured to generate an interrupt.

Brownout detection may be enabled or disabled in software.

If Brownout detection is enabled, the operating voltage range for V

is 2.7 V to 3.6 V,

and the brownout condition occurs when V

falls below the brownout trip voltage,

(see

Table 13 "DC electrical characteristics"

), and is negated when V

rises

above V

. If brownout detection is disabled, the operating voltage range for V

2.4 V to 3.6 V. If the P89LPC901/902/903 device is to operate with a power supply
that can be below 2.7 V, BOE should be left in the unprogrammed state so that the
device can operate at 2.4 V, otherwise continuous brownout reset may prevent the
device from operating.

For correct activation of Brownout detect, the V

rise and fall times must be

observed. Please see

Table 13 "DC electrical characteristics"

for specifications.

8.13.2

Power-on detection

The Power-on Detect has a function similar to the Brownout detect, but is designed to
work as power comes up initially, before the power supply voltage reaches a level
where Brownout detect can work. The POF flag in the RSTSRC register is set to
indicate an initial power-up condition. The POF flag will remain set until cleared by
software.

8.14 Power reduction modes

The P89LPC901/902/903 supports three different power reduction modes. These
modes are Idle mode, Power-down mode, and total Power-down mode.

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8.14.1

Idle mode

Idle mode leaves peripherals running in order to allow them to activate the processor
when an interrupt is generated. Any enabled interrupt source or reset may terminate
Idle mode.

8.14.2

Power-down mode

The Power-down mode stops the oscillator in order to minimize power consumption.
The P89LPC901/902/903 exits Power-down mode via any reset, or certain interrupts.
In Power-down mode, the power supply voltage may be reduced to the RAM
keep-alive voltage V

RAM

. This retains the RAM contents at the point where

Power-down mode was entered. SFR contents are not guaranteed after V

has

been lowered to V

RAM

, therefore it is highly recommended to wake up the processor

via reset in this case. V

must be raised to within the operating range before the

Power-down mode is exited.

Some chip functions continue to operate and draw power during Power-down mode,
increasing the total power used during Power-down. These include: Brownout detect,
Watchdog Timer, Comparators (note that Comparators can be powered-down
separately), and Real-Time Clock (RTC)/System Timer. The internal RC oscillator is
disabled unless both the RC oscillator has been selected as the system clock and the
RTC is enabled.

8.14.3

Total Power-down mode

This is the same as Power-down mode except that the brownout detection circuitry
and the voltage comparators are also disabled to conserve additional power. The
internal RC oscillator is disabled unless both the RC oscillator has been selected as
the system clock and the RTC is enabled. If the internal RC oscillator is used to clock
the RTC during Power-down, there will be high power consumption. Please use an
external low frequency clock to achieve low power with the Real-Time Clock running
during Power-down.

8.15 Reset

The P1.5/RST pin can function as either an active-LOW reset input or as a digital
input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to `1', enables the
external reset input function on P1.5. When cleared, P1.5 may be used as an input
pin.

Remark: During a power-up sequence, the RPE selection is overridden and this pin
will always function as a reset input. An external circuit connected to this pin
should not hold this pin LOW during a power-on sequence as this will keep the
device in reset. After power-up this input will function either as an external reset
input or as a digital input as defined by the RPE bit. Only a power-up reset will
temporarily override the selection defined by RPE bit. Other sources of reset will not
override the RPE bit.

Remark: During a power cycle, V

must fall below V

POR

(see

Table 13 "DC electrical

characteristics"

) before power is reapplied, in order to ensure a power-on reset.

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Reset can be triggered from the following sources:

External reset pin (during power-up or if user configured via UCFG1)

Power-on detect

Brownout detect

Watchdog Timer

Software reset

UART break character detect reset (P80LPC903).

For every reset source, there is a flag in the Reset Register, RSTSRC. The user can
read this register to determine the most recent reset source. These flag bits can be
cleared in software by writing a `0' to the corresponding bit. More than one flag bit
may be set:

During a power-on reset, both POF and BOF are set but the other flag bits are
cleared.

For any other reset, previously set flag bits that have not been cleared will remain
set.

8.16 Timers/counters 0 and 1

The P89LPC901/902/903 has two general purpose timers which are similar to the
standard 80C51 Timer 0 and Timer 1. These timers have four operating modes
(modes 0, 1, 2, and 3). Modes 0, 1, and 2 are the same for both Timers. Mode 3 is
different.

8.16.1

Mode 0

Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit
Counter with a divide-by-32 prescaler. In this mode, the Timer register is configured
as a 13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.

8.16.2

Mode 1

Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.

8.16.3

Mode 2

Mode 2 configures the Timer register as an 8-bit Counter with automatic reload.
Mode 2 operation is the same for Timer 0 and Timer 1.

8.16.4

Mode 3

When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit
counters and is provided for applications that require an extra 8-bit timer. When
Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator.

8.16.5

Mode 6 (P89LPC901)

In this mode, the corresponding timer can be changed to a PWM with a full period of
256 timer clocks.

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8.16.6

Timer overflow toggle output (P89LPC901)

Timers 0 and 1 can be configured to automatically toggle a port output whenever a
timer overflow occurs. The same device pins that are used for the T0 and T1 count
inputs are also used for the timer toggle outputs. The port outputs will be a logic 1
prior to the first timer overflow when this mode is turned on.

8.17 Real-Time clock/system timer

The P89LPC901/902/903 has a simple Real-Time clock that allows a user to continue
running an accurate timer while the rest of the device is powered-down. The
Real-Time clock can be a wake-up or an interrupt source. The Real-Time clock is a
23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down
counter. When it reaches all `0's, the counter will be reloaded again and the RTCF
flag will be set. The clock source for this counter can be either the CPU clock (CCLK)
or the XTAL oscillator, provided that the XTAL oscillator is not being used as the CPU
clock. If the XTAL oscillator is used as the CPU clock, then the RTC will use CCLK as
its clock source. Only power-on reset will reset the Real-Time clock and its
associated SFRs to the default state.

8.18 UART (P89LPC903)

The P89LPC903 has an enhanced UART that is compatible with the conventional
80C51 UART except that Timer 2 overflow cannot be used as a baud rate source.
The P89LPC903 does include an independent Baud Rate Generator. The baud rate
can be selected from the oscillator (divided by a constant), Timer 1 overflow, or the
independent Baud Rate Generator. In addition to the baud rate generation,
enhancements over the standard 80C51 UART include Framing Error detection,
automatic address recognition, selectable double buffering and several interrupt
options. The UART can be operated in 4 modes: shift register, 8-bit UART, 9-bit
UART, and CPU clock/32 or CPU clock/16.

8.18.1

Mode 0

Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are
transmitted or received, LSB first. The baud rate is fixed at

of the CPU clock

frequency.

8.18.2

Mode 1

10 bits are transmitted (through TxD) or received (through RxD): a start bit
(logical `0'), 8 data bits (LSB first), and a stop bit (logical `1'). When data is received,
the stop bit is stored in RB8 in Special Function Register SCON. The baud rate is
variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator
(described in

Section 8.18.5 "Baud rate generator and selection"

8.18.3

Mode 2

11 bits are transmitted (through TxD) or received (through RxD): start bit (logical `0'),
8 data bits (LSB first), a programmable 9

data bit, and a stop bit (logical `1'). When

data is transmitted, the 9

data bit (TB8 in SCON) can be assigned the value of `0' or

`1'. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When
data is received, the 9

data bit goes into RB8 in Special Function Register SCON,

while the stop bit is not saved. The baud rate is programmable to either

the CPU clock frequency, as determined by the SMOD1 bit in PCON.

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8.18.4

Mode 3

11 bits are transmitted (through TxD) or received (through RxD): a start bit
(logical `0'), 8 data bits (LSB first), a programmable 9

data bit, and a stop bit

(logical `1'). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate.
The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or
the Baud Rate Generator (described in section

Section 8.18.5 "Baud rate generator

and selection"

8.18.5

Baud rate generator and selection

The P89LPC903 enhanced UART has an independent Baud Rate Generator. The
baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0
SFRs which together form a 16-bit baud rate divisor value that works in a similar
manner as Timer 1. If the baud rate generator is used, Timer 1 can be used for other
timing functions.

The UART can use either Timer 1 or the baud rate generator output (see

Figure 18

Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The
independent Baud Rate Generator uses CCLK.

8.18.6

Framing error

Framing error is reported in the status register (SSTAT). In addition, if SMOD0
(PCON.6) is `1', framing errors can be made available in SCON.7, respectively. If
SMOD0 is `0', SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6)
are set up when SMOD0 is `0'.

8.18.7

Break detect

Break detect is reported in the status register (SSTAT). A break is detected when
11 consecutive bits are sensed LOW. The break detect can be used to reset the
device.

8.18.8

Double buffering

The UART has a transmit double buffer that allows buffering of the next character to
be written to SBUF while the first character is being transmitted. Double buffering
allows transmission of a string of characters with only one stop bit between any two
characters, as long as the next character is written between the start bit and the stop
bit of the previous character.

Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = `0'), the UART
is compatible with the conventional 80C51 UART. If enabled, the UART allows writing
to SnBUF while the previous data is being shifted out. Double buffering is only
allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be
disabled (DBMOD = `0').

Fig 18. Baud rate sources for UART (Modes 1, 3).

Baud Rate Modes 1 and 3

SBRGS = 1

SBRGS = 0

SMOD1 = 0

SMOD1 = 1

Timer 1 Overflow

(PCLK-based)

Baud Rate Generator

(CCLK-based)

002aaa419

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8.18.9

Transmit interrupts with double buffering enabled (Modes 1, 2 and 3)

Unlike the conventional UART, in double buffering mode, the Tx interrupt is generated
when the double buffer is ready to receive new data.

8.18.10

The 9

bit (bit 8) in double buffering (Modes 1, 2 and 3)

If double buffering is disabled TB8 can be written before or after SBUF is written, as
long as TB8 is updated some time before that bit is shifted out. TB8 must not be
changed until the bit is shifted out, as indicated by the Tx interrupt.

If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8
will be double-buffered together with SBUF data.

8.19 Analog comparators

One analog comparator is provided on the P89LPC901. Two analog comparators are
provided on the P89LPC902 and P89LPC903 devices. Comparator operation is such
that the output is a logical one (which may be read in a register) when the positive
input is greater than the negative input (selectable from a pin or an internal reference
voltage). Otherwise the output is a zero. The comparator may be configured to cause
an interrupt when the output value changes.

The connections to the comparator are shown in

Figure 19

. Note: Not all possible

comparator configurations are available on all three devices. Please refer to the Logic
diagrams in

Section 6 "Logic symbols" on page 12

. The comparator functions to

= 2.4 V.

When the comparator is first enabled, the comparator output and interrupt flag are not
guaranteed to be stable for 10 microseconds. The comparator interrupt should not be
enabled during that time, and the comparator interrupt flag must be cleared before
the interrupt is enabled in order to prevent an immediate interrupt service.

When a comparator is disabled the comparator's output, COx, goes HIGH. If the
comparator output was LOW and then is disabled, the resulting transition of the
comparator output from a LOW to HIGH state will set the comparator flag, CMFx.
This will cause an interrupt if the comparator interrupt is enabled. The user should
therefore disable the comparator interrupt prior to disabling the comparator.
Additionally, the user should clear the comparator flag, CMFx, after disabling the
comparator.

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8.20 Internal reference voltage

An internal reference voltage generator may supply a default reference when a single
comparator input pin is used. The value of the internal reference voltage, referred to
as V

REF

, is 1.23 V

10%.

8.21 Comparator interrupt

Each comparator has an interrupt flag contained in its configuration register. This flag
is set whenever the comparator output changes state. The flag may be polled by
software or may be used to generate an interrupt.

8.22 Comparator and power reduction modes

The comparators may remain enabled when Power-down or Idle mode is activated,
but the comparators are disabled automatically in Total Power-down mode.

If the comparator interrupt is enabled (except in Total Power-down mode), a change
of the comparator output state will generate an interrupt and wake up the processor. If
the comparator output to a pin is enabled, the pin should be configured in the
push-pull mode in order to obtain fast switching times while in Power-down mode.
The reason is that with the oscillator stopped, the temporary strong pull-up that
normally occurs during switching on a quasi-bidirectional port pin does not take
place.

The comparator consumes power in Power-down and Idle modes, as well as in the
normal operating mode. This fact should be taken into account when system power
consumption is an issue. To minimize power consumption, the user can disable the
comparator via PCONA.5 or put the device in Total Power-down mode.

Fig 19. Comparator input and output connections.

Comparator 1

CN1

(P0.4) CIN1A

(P0.5) CMPREF

VREF

OE1

Change Detect

CO1

CMF1

Interrupt

002aaa453

CMP1 (P0.6)

Change Detect

CMF2

Comparator 2

OE2

CO2

CMP2 (P0.0)

CN2

(P0.2) CIN2A

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8.23 Keypad interrupt (KBI)

The Keypad Interrupt function is intended primarily to allow a single interrupt to be
generated when Port 0 is equal to or not equal to a certain pattern. This function can
be used for bus address recognition or keypad recognition. The user can configure
the port via SFRs for different tasks.

The Keypad Interrupt Mask Register (KBMASK) is used to define which input pins
connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN)
is used to define a pattern that is compared to the value of Port 0. The Keypad
Interrupt Flag (KBIF) in the Keypad Interrupt Control Register (KBCON) is set when
the condition is matched while the Keypad Interrupt function is active. An interrupt will
be generated if enabled. The PATN_SEL bit in the Keypad Interrupt Control Register
(KBCON) is used to define equal or not-equal for the comparison.

In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x
series, the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then
any key connected to Port 0 which is enabled by the KBMASK register will cause the
hardware to set KBIF and generate an interrupt if it has been enabled. The interrupt
may be used to wake up the CPU from Idle or Power-down modes. This feature is
particularly useful in handheld, battery powered systems that need to carefully
manage power consumption yet also need to be convenient to use.

In order to set the flag and cause an interrupt, the pattern on Port 0 must be held
longer than 6 CCLKs.

8.24 Watchdog timer

The Watchdog timer causes a system reset when it underflows as a result of a failure
to feed the timer prior to the timer reaching its terminal count. It consists of a
programmable 12-bit prescaler, and an 8-bit down counter. The down counter is
decremented by a tap taken from the prescaler. The clock source for the prescaler is
either the PCLK or the nominal 400 kHz Watchdog oscillator. The Watchdog timer
can only be reset by a power-on reset. When the Watchdog feature is disabled, it can
be used as an interval timer and may generate an interrupt.

Figure 20

shows the

Watchdog timer in Watchdog mode. Feeding the watchdog requires a two-byte
sequence. If PCLK is selected as the Watchdog clock and the CPU is powered-down,
the watchdog is disabled. The Watchdog timer has a time-out period that ranges from
a few

s to a few seconds. Please refer to the

P89LPC901/902/903 User's Manual for

more details.

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8.25 Additional features

8.25.1

Software reset

The SRST bit in AUXR1 gives software the opportunity to reset the processor
completely, as if an external reset or Watchdog reset had occurred. Care should be
taken when writing to AUXR1 to avoid accidental software resets.

8.25.2

Dual data pointers

The dual Data Pointers (DPTR) provides two different Data Pointers to specify the
address used with certain instructions. The DPS bit in the AUXR1 register selects
one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic `0' so
that the DPS bit may be toggled (thereby switching Data Pointers) simply by
incrementing the AUXR1 register, without the possibility of inadvertently altering other
bits in the register.

8.26 Flash program memory

8.26.1

General description

The P89LPC901/902/903 Flash memory provides in-circuit electrical erasure and
programming. The Flash can be erased, read, and written as bytes. The Sector and
Page Erase functions can erase any Flash sector (256 bytes) or page (16 bytes). The
Chip Erase operation will erase the entire program memory. In-Circuit Programming
using standard commercial programmers is available. In addition, In-Application
Programming (IAP) and byte erase allows code memory to be used for non-volatile
data storage. On-chip erase and write timing generation contribute to a user-friendly
programming interface. The P89LPC901/902/903 Flash reliably stores memory
contents even after more than 100,000 erase and program cycles. The cell is

(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a

feed sequence.

Fig 20. Watchdog timer in Watchdog mode (WDTE = `1').

PRE2

PRE1

PRE0

WDRUN

WDTOF

WDCLK

WDCON (A7H)

CONTROL REGISTER

PRESCALER

002aaa423

SHADOW
REGISTER
FOR WDCON

8-BIT DOWN

COUNTER

WDL (C1H)

Watchdog

oscillator

PCLK

MOV WFEED1, #0A5H
MOV WFEED2, #05AH

RESET
see note (1)

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designed to optimize the erase and programming mechanisms. The
P89LPC901/902/903 uses V

as the supply voltage to perform the Program/Erase

algorithms.

8.26.2

Features

Programming and erase over the full operating voltage range.

Byte-erase allowing code memory to be used for data storage.

Read/Programming/Erase using ICP.

Any flash program/erase operation in 2 ms.

Programming with industry-standard commercial programmers.

Programmable security for the code in the Flash for each sector.

More than 100,000 minimum erase/program cycles for each byte.

10-year minimum data retention.

8.26.3

Flash organization

The P89LPC901/902/903 program memory consists of four 256 byte sectors. Each
sector can be further divided into 16-byte pages. In addition to sector erase, page
erase, and byte erase, a 16-byte page register is included which allows from 1 to 16
bytes of a given page to be programmed at the same time, substantially reducing
overall programming time. In addition, erasing and reprogramming of
user-programmable configuration bytes including UCFG1, the Boot Status Bit, and
the Boot Vector is supported.

8.26.4

Flash programming and erasing

Different methods of erasing or programming of the Flash are available. The Flash
may be programmed or erased in the end-user application (IAP) under control of the
application's firmware. Another option is to use the In-Circuit Programming (ICP)
mechanism. This ICP system provides for programming through a serial clock- serial
data interface. Third, the Flash may be programmed or erased using a commercially
available EPROM programmer which supports this device. This device does not
provide for direct verification of code memory contents. Instead this device provides a
32-bit CRC result on either a sector or the entire 1 KB of user code space.

8.26.5

In-circuit programming (ICP)

In-Circuit Programming is performed without removing the microcontroller from the
system. The In-Circuit Programming facility consists of internal hardware resources
to facilitate remote programming of the P89LPC901/902/903 through a two-wire
serial interface. The Philips In-Circuit Programming facility has made in-circuit
programming in an embedded application, using commercially available
programmers, possible with a minimum of additional expense in components and
circuit board area. The ICP function uses five pins. Only a small connector needs to
be available to interface your application to a commercial programmer in order to use
this feature. Additional details may be found in the

P89LPC901/902/903 User's

Manual.

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8.26.6

In-application programming

In-Application Programming is performed in the application under the control of the
microcontroller's firmware. The IAP facility consists of internal hardware resources to
facilitate programming and erasing. The Philips In-Application Programming has
made in-application programming in an embedded application possible without
additional components. This is accomplished through the use of four SFRs consisting
of a control/status register, a data register, and two address registers. Additional
details may be found in the

P89LPC901/902/903 User's Manual.

8.26.7

Using flash as data storage

The Flash code memory array of this device supports individual byte erasing and
programming. Any byte in the code memory array may be read using the MOVC
instruction, provided that the sector containing the byte has not been secured (a
MOVC instruction is not allowed to read code memory contents of a secured sector).
Thus any byte in a non-secured sector may be used for non-volatile data storage.

8.26.8

User configuration bytes

Some user-configurable features of the P89LPC901/902/903 must be defined at
power-up and therefore cannot be set by the program after start of execution. These
features are configured through the use of the Flash byte UCFG1. Please see the
P89LPC901/902/903 User's Manual for additional details.

8.26.9

User sector security bytes

There are four User Sector Security Bytes, each corresponding to one sector. Please
see the

P89LPC901/902/903 User's Manual for additional details.

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Limiting values

[1]

Stresses above those listed under

Table 12 "Limiting values"

may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any conditions other than those described in

Table 13 "DC electrical characteristics"

and

Table 14 "AC characteristics"

section of this specification are not implied.

[2]

This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

[3]

Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V

unless otherwise

noted.

Table 12:

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

amb(bias)

operating bias ambient temperature

+125

stg

storage temperature range

+150

xtal

voltage on XTAL1, XTAL2 pin to V

as applicable

+ 0.5

voltage on any other pin to V

0.5

+5.5

OH(I/O)

HIGH-level output current per I/O pin

OL(I/O)

LOW-level output current per I/O pin

I/O(tot)(max)

maximum total I/O current

120

tot(pack)

total power dissipation per package

based on package heat
transfer, not device power
consumption

1.5

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10. Static characteristics

Table 13:

DC electrical characteristics

= 2.4 V to 3.6 V unless otherwise specified.

amb

C to +85

C for industrial, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

[1]

Max

Unit

power supply current,
operating (P89LPC901)

3.6 V; 12 MHz

[7]

power supply current, Idle
mode (P89LPC901)

3.6 V; 12 MHz

[7]

power supply current,
operating (P89LPC902,
P89LPC903)

3.6 V; 7.373 MHz

[8]

<t.b.d.>

power supply current, Idle
mode (P89LPC902,
P89LPC903)

3.6 V; 7.373 MHz

[8]

<t.b.d.>

Power supply current,
Power-down mode, voltage
comparators powered-down

3.6 V

[7][8]

<t.b.d.>

PD1

Power supply current, Total
Power-down mode

3.6 V

[7][8]

DDR

rise time

mV/

DDF

fall time

mV/

POR

Power-on reset detect voltage

0.2

RAM

RAM keep-alive voltage

1.5

th(HL)

negative-going threshold
voltage (Schmitt input)

0.22V

0.4V

th(LH)

positive-going threshold
voltage (Schmitt input)

0.6V

0.7V

hys

hysteresis voltage

0.2V

LOW-level output voltage; all
ports, all modes except Hi-Z

= 20 mA

0.6

1.0

= 10 mA

0.3

0.5

= 3.2 mA

0.2

0.3

HIGH-level output voltage, all
ports

8 mA;

push-pull mode

TBD

3.2 mA;

push-pull mode

0.7

0.4

quasi-bidirectional mode

0.3

0.2

input/output pin capacitance

[6]

logical 0 input current,
all ports

= 0.4 V

[5]

input leakage current, all ports V

= V

or V

[4]

logical 1-to-0 transition
current, all ports

= 2.0 V at

= 3.6 V

[2][3]

450

RST

internal reset pull-up resistor

Philips Semiconductors

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 04 -- 21 November 2003

45 of 55

9397 750 12293

[1]

Typical ratings are not guaranteed. The values listed are at room temperature, 3 V.

[2]

Ports in quasi-bidirectional mode with weak pull-up (applies to all port pins with pull-ups)

[3]

Port pins source a transition current when used in quasi-bidirectional mode and externally driven from `1' to `0'. This current is highest
when V

is approximately 2 V.

[4]

Measured with port in high-impedance mode.

[5]

Measured with port in quasi-bidirectional mode.

[6]

Pin capacitance is characterized but not tested.

[7]

The I

, I

specifications are measured using an external clock with the following functions disabled: comparators, brownout detect,

and Watchdog timer (P89LPC901).

[8]

The I

, I

specifications are measured with the following functions disabled: comparators, brownout detect, and Watchdog timer

(P89LPC902, P89LPC903).

brownout trip voltage with
BOV = `1', BOPD = `0'

2.4 V < V

< 3.6 V

2.40

2.70

REF

bandgap reference voltage

1.11

1.23

1.34

(VREF)

bandgap temperature
coefficient

ppm/

Table 13:

DC electrical characteristics

...continued

= 2.4 V to 3.6 V unless otherwise specified.

amb

C to +85

C for industrial, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

[1]

Max

Unit

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8-bit microcontrollers with two-clock 80C51 core

Product data

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11. Dynamic characteristics

[1]

Parameters are valid over operating temperature range unless otherwise specified.

[2]

Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.

Table 14:

AC characteristics

amb

C to +85

C for industrial, unless otherwise specified.

[1]

Symbol

Parameter

Conditions

Variable clock

OSC

= 12 MHz

Unit

Min

Max

Min

Max

RCOSC

internal RC oscillator frequency
(nominal f = 7.3728 MHz) trimmed
to

1% at T

amb

= 25

7.189

7.557

7.189

7.557

MHz

WDOSC

internal Watchdog oscillator
frequency (nominal f = 400 kHz)

280

480

280

480

kHz

Crystal oscillator (P89LPC901)

OSC

oscillator frequency

MHz

CLCL

clock cycle

see

Figure 22

CLKP

CLKLP active frequency

MHz

Glitch filter

glitch rejection, P1.5/RST pin

signal acceptance, P1.5/RST pin

125

glitch rejection, any pin except
P1.5/RST

signal acceptance, any pin except
P1.5/RST

External clock (P89LPC901)

CHCX

HIGH time

see

Figure 22

CLCL

CLCX

LOW time

see

Figure 22

CLCL

CHCX

CLCH

rise time

see

Figure 22

CHCL

fall time

see

Figure 22

Shift register (UART mode 0 - P89LPC903)

XLXL

serial port clock cycle time

see

Figure 21

16 t

CLCL

1333

QVXH

output data set-up to clock rising
edge

see

Figure 21

13 t

CLCL

1083

XHQX

output data hold after clock rising
edge

see

Figure 21

CLCL

+ 20

103

XHDX

input data hold after clock rising
edge

see

Figure 21

DVXH

input data valid to clock rising edge see

Figure 21

150

Philips Semiconductors

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Product data

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12. Comparator electrical characteristics

[1]

This parameter is characterized, but not tested in production.

Fig 21. Shift register mode timing.

Valid

tXLXL

002aaa425

Set TI

Set RI

tXHQX

tQVXH

tXHDV

tXHDX

Clock

Output Data

Write to SBUF

Input Data

Clear RI

Fig 22. External clock timing.

tCHCL

tCLCX

tCHCX

tCLCH

002aaa416

0.2 VDD + 0.9

0.2 VDD - 0.1 V

VDD - 0.5 V

0.45 V

Table 15:

Comparator electrical characteristics

= 2.4 V to 3.6 V, unless otherwise specified.

amb

C to +85

C for industrial, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

offset voltage comparator inputs

common mode range comparator inputs

0.3

CMRR

common mode rejection ratio

[1]

response time

250

500

comparator enable to output valid

input leakage current, comparator

0 < V

< V

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P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Product data

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13. Package outline

Fig 23. SOT96-1

UNIT

max.

(1)

(2)

(1)

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

inches

1.75

0.25
0.10

1.45
1.25

0.25

0.49
0.36

0.25
0.19

5.0
4.8

4.0
3.8

1.27

6.2
5.8

1.05

0.7
0.6

0.7
0.3

8
0

0.25

0.1

0.25

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

1.0
0.4

SOT96-1

detail X

(A )

pin 1 index

076E03

MS-012

0.069

0.010
0.004

0.057
0.049

0.01

0.019
0.014

0.0100
0.0075

0.20
0.19

0.16
0.15

0.05

0.244
0.228

0.028
0.024

0.028
0.012

0.01

0.041

0.004

0.039
0.016

2.5

5 mm

scale

SO8: plastic small outline package; 8 leads; body width 3.9 mm

SOT96-1

99-12-27
03-02-18

Philips Semiconductors

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Product data

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49 of 55

9397 750 12293

Fig 24. SOT97-1

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

SOT97-1

99-12-27
03-02-13

UNIT

max.

(1)

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

min.

max.

1.73
1.14

0.53
0.38

0.36
0.23

9.8
9.2

6.48
6.20

3.60
3.05

0.254

2.54

7.62

8.25
7.80

10.0

8.3

1.15

4.2

0.51

3.2

inches

0.068
0.045

0.021
0.015

0.014
0.009

1.07
0.89

0.042
0.035

0.39
0.36

0.26
0.24

0.14
0.12

0.01

0.1

0.3

0.32
0.31

0.39
0.33

0.045

0.17

0.02

0.13

050G01

MO-001

SC-504-8

(e )

seating plane

10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

pin 1 index

DIP8: plastic dual in-line package; 8 leads (300 mil)

SOT97-1

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8-bit microcontrollers with two-clock 80C51 core

Product data

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14. Soldering

14.1 Introduction

This text gives a very brief insight to a complex technology. A more in-depth account
of soldering ICs can be found in our

Data Handbook IC26; Integrated Circuit

Packages (document order number 9398 652 90011).

There is no soldering method that is ideal for all IC packages. Wave soldering is often
preferred when through-hole and surface mount components are mixed on one
printed-circuit board. Wave soldering can still be used for certain surface mount ICs,
but it is not suitable for fine pitch SMDs. In these situations reflow soldering is
recommended. Driven by legislation and environmental forces the worldwide use of
lead-free solder pastes is increasing.

14.2 Through-hole mount packages

14.2.1

Soldering by dipping or by solder wave

Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250

C or

265

C, depending on solder material applied, SnPb or Pb-free respectively.

The total contact time of successive solder waves must not exceed 5 seconds.

The device may be mounted up to the seating plane, but the temperature of the
plastic body must not exceed the specified maximum storage temperature (T

stg(max)

If the printed-circuit board has been pre-heated, forced cooling may be necessary
immediately after soldering to keep the temperature within the permissible limit.

14.2.2

Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the
seating plane or not more than 2 mm above it. If the temperature of the soldering iron
bit is less than 300

C it may remain in contact for up to 10 seconds. If the bit

temperature is between 300 and 400

C, contact may be up to 5 seconds.

14.3 Surface mount packages

14.3.1

Reflow soldering

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling
or pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending on heating method.

Typical reflow peak temperatures range from 215 to 270

C depending on solder

paste material. The top-surface temperature of the packages should preferably be
kept:

below 225

C (SnPb process) or below 245

C (Pb-free process)

for all the BGA and SSOP-T packages

Philips Semiconductors

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Product data

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for packages with a thickness

2.5 mm

for packages with a thickness < 2.5 mm and a volume

350 mm

so called

thick/large packages.

below 240

C (SnPb process) or below 260

C (Pb-free process) for packages with

a thickness < 2.5 mm and a volume < 350 mm

so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all
times.

14.3.2

Wave soldering

Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging
and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was specifically
developed.

If wave soldering is used the following conditions must be observed for optimal
results:

Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.

For packages with leads on two sides and a pitch (e):

larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

For packages with leads on four sides, the footprint must be placed at a 45

angle

to the transport direction of the printed-circuit board. The footprint must
incorporate solder thieves downstream and at the side corners.

During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250

C or

265

C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated flux will eliminate the need for removal of corrosive residues in
most applications.

14.3.3

Manual soldering

Fix the component by first soldering two diagonally-opposite end leads. Use a low
voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time
must be limited to 10 seconds at up to 300

When using a dedicated tool, all other leads can be soldered in one operation within
2 to 5 seconds between 270 and 320

Philips Semiconductors

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 04 -- 21 November 2003

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14.4 Package related soldering information

[1]

For more detailed information on the BGA packages refer to the

(LF)BGA Application Note

(AN01026); order a copy from your Philips Semiconductors sales office.

[2]

All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal
or external package cracks may occur due to vaporization of the moisture in them (the so called
popcorn effect). For details, refer to the Drypack information in the

Data Handbook IC26; Integrated

Circuit Packages; Section: Packing Methods.

[3]

For SDIP packages, the longitudinal axis must be parallel to the transport direction of the
printed-circuit board.

[4]

Hot bar soldering or manual soldering is suitable for PMFP packages.

[5]

These transparent plastic packages are extremely sensitive to reflow soldering conditions and must
on no account be processed through more than one soldering cycle or subjected to infrared reflow
soldering with peak temperature exceeding 217

C measured in the atmosphere of the reflow

oven. The package body peak temperature must be kept as low as possible.

[6]

These packages are not suitable for wave soldering. On versions with the heatsink on the bottom
side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with
the heatsink on the top side, the solder might be deposited on the heatsink surface.

[7]

If wave soldering is considered, then the package must be placed at a 45

angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[8]

Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it
is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[9]

Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

Table 16:

Suitability of IC packages for wave, reflow and dipping soldering methods

Mounting

Package

[1]

Soldering method

Wave

Reflow

[2]

Dipping

Through-hole
mount

DBS, DIP, HDIP, RDBS,
SDIP, SIL

suitable

[3]

suitable

Through-hole-
surface mount

PMFP

[4]

not suitable

Surface mount

BGA, LBGA, LFBGA,
SQFP, SSOP-T

[5]

TFBGA, VFBGA

not suitable

suitable

DHVQFN, HBCC, HBGA,
HLQFP, HSQFP, HSOP,
HTQFP, HTSSOP,
HVQFN, HVSON, SMS

not suitable

[6]

suitable

PLCC

[7]

, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended

[7][8]

suitable

SSOP, TSSOP, VSO,
VSSOP

not recommended

[9]

suitable

Philips Semiconductors

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8-bit microcontrollers with two-clock 80C51 core

Product data

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15. Revision history

Table 17:

Revision history

Rev Date

CPCN

Description

20031121

Product data (9397 750 12293); ECN 853-2434 01-A14555 of 18 November 2003

Modifications:

Changed CIN to CIN1A throughout document.

Changed CMP to CMP1 throughout document.

Figure 1 "P89LPC901 block diagram." on page 4

; adjusted drawing.

Figure 2 "P89LPC902 block diagram." on page 5

; adjusted drawing.

Figure 3 "P89LPC903 block diagram." on page 6

; adjusted drawing.

Table 5 "P89LPC903 pin description" on page 11

; changed CIN to CIN1A.

Table 8 "P89LPC902 Special function registers" on page 18

; removed ENCLK

Table 9 "P89LPC903 Special function registers" on page 21

; removed ENCLK

Figure 19 "Comparator input and output connections." on page 38

; adjusted drawing.

Table 13 "DC electrical characteristics" on page 44

; changed I

value from 1.5 V to

2.0 V.

20030929

Product data (9397 750 12031); ECN 853-2434 30348 of 11 September 2003

20030731

Product data (9397 750 11801); ECN 853-2434 30152 of 28 July 2003

20030602

Preliminary data (9397 750 11494)

9397 750 12293

Philips Semiconductors

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 04 -- 21 November 2003

54 of 55

Contact information

For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.

Fax: +31 40 27 24825

16. Data sheet status

[1]

Please consult the most recently issued data sheet before initiating or completing a design.

[2]

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

17. Definitions

Short-form specification -- The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.

Application information -- Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.

18. Disclaimers

Life support -- These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status `Production'),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.

Level

Data sheet status

[1]

Product status

[2][3]

Definition

Objective data

Development

This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.

Preliminary data

Qualification

This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).

All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.

The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.

Date of release: 21 November 2003

Document order number: 9397 750 12293

Contents

Philips Semiconductors

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.1

Principal features . . . . . . . . . . . . . . . . . . . . . . . 1

2.2

Additional features . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information . . . . . . . . . . . . . . . . . . . . . 3

3.1

Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pinning information . . . . . . . . . . . . . . . . . . . . . . 7

5.1

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

5.2

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8

Logic symbols . . . . . . . . . . . . . . . . . . . . . . . . . 12

Special function registers . . . . . . . . . . . . . . . . 14

Functional description . . . . . . . . . . . . . . . . . . 24

8.1

Enhanced CPU . . . . . . . . . . . . . . . . . . . . . . . . 24

8.2

Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8.3

On-chip RC oscillator option . . . . . . . . . . . . . . 25

8.4

Watchdog oscillator option . . . . . . . . . . . . . . . 25

8.5

External clock input option (P89LPC901) . . . . 25

8.6

CPU CLock (CCLK) wake-up delay . . . . . . . . 27

8.7

CPU CLOCK (CCLK) modification: DIVM
register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.8

Low power select . . . . . . . . . . . . . . . . . . . . . . 27

8.9

Memory organization . . . . . . . . . . . . . . . . . . . 27

8.10

Data RAM arrangement . . . . . . . . . . . . . . . . . 27

8.11

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.12

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.13

Power monitoring functions. . . . . . . . . . . . . . . 32

8.14

Power reduction modes . . . . . . . . . . . . . . . . . 32

8.15

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8.16

Timers/counters 0 and 1 . . . . . . . . . . . . . . . . . 34

8.17

Real-Time clock/system timer. . . . . . . . . . . . . 35

8.18

UART (P89LPC903) . . . . . . . . . . . . . . . . . . . . 35

8.19

Analog comparators . . . . . . . . . . . . . . . . . . . . 37

8.20

Internal reference voltage . . . . . . . . . . . . . . . . 38

8.21

Comparator interrupt. . . . . . . . . . . . . . . . . . . . 38

8.22

Comparator and power reduction modes . . . . 38

8.23

Keypad interrupt (KBI) . . . . . . . . . . . . . . . . . . 39

8.24

Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 39

8.25

Additional features . . . . . . . . . . . . . . . . . . . . . 40

8.26

Flash program memory. . . . . . . . . . . . . . . . . . 40

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 43

Static characteristics. . . . . . . . . . . . . . . . . . . . 44

Dynamic characteristics . . . . . . . . . . . . . . . . . 46

Comparator electrical characteristics . . . . . . 47

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 48

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

14.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 50

14.2

Through-hole mount packages . . . . . . . . . . . 50

14.3

Surface mount packages . . . . . . . . . . . . . . . . 50

14.4

Package related soldering information . . . . . . 52

Revision history . . . . . . . . . . . . . . . . . . . . . . . 53

Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 54

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: P89LPC901

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: P89LPC901