Philips Semiconductors

Product specification

80C31/80C51/87C51

CMOS single-chip 8-bit microcontrollers

1996 Aug 16

8530169 17187

DESCRIPTION

The Philips 80C31/80C51/87C51 is a high-performance
microcontroller fabricated with Philips high-density CMOS
technology. The CMOS 8XC51 is functionally compatible with the
NMOS 8031/8051 microcontrollers. The Philips CMOS technology
combines the high speed and density characteristics of HMOS with
the low power attributes of CMOS. Philips epitaxial substrate
minimizes latch-up sensitivity.

The 8XC51 contains a 4k

8 ROM (80C51) EPROM (87C51), a 128

8 RAM, 32 I/O lines, two 16-bit counter/timers, a five-source,

two-priority level nested interrupt structure, a serial I/O port for either
multi-processor communications, I/O expansion or full duplex UART,
and on-chip oscillator and clock circuits.

In addition, the device has two software selectable modes of power
reduction--idle mode and power-down mode. The idle mode freezes
the CPU while allowing the RAM, timers, serial port, and interrupt
system to continue functioning. The power-down mode saves the
RAM contents but freezes the oscillator, causing all other chip
functions to be inoperative.

FEATURES

8031/8051 compatible

8 ROM (80C51)

8 EPROM (87C51)

ROMless (80C31)

128

8 RAM

Two 16-bit counter/timers

Full duplex serial channel

Boolean processor

Memory addressing capability

64k ROM and 64k RAM

Power control modes:

Idle mode

Power-down mode

CMOS and TTL compatible

Five speed ranges at V

= 5V

12MHz

16MHz

24MHz

33MHz

Five package styles

Extended temperature ranges

OTP package available

PIN CONFIGURATIONS

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

RST

RxD/P3.0

TxD/P3.1

INT0/P3.2

INT1/P3.3

T0/P3.4

T1/P3.5

P1.7

WR/P3.6

RD/P3.7

XTAL2

XTAL1

VSS

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

P2.6/A14

P2.7/A15

PSEN

ALE/PROG

EA/VPP

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

VCC

CERAMIC

AND

PLASTIC

DUAL

IN-LINE

PACKAGE

CERAMIC

AND

PLASTIC

LEAD

CHIP

CARRIER

PLASTIC

QUAD

FLAT

PACK

SU00001

SEE PAGE 3 FOR QFP AND LCC PIN FUNCTIONS.

Philips Semiconductors

Product specification

80C31/80C51/87C51

CMOS single-chip 8-bit microcontrollers

1996 Aug 16

CERAMIC AND PLASTIC LEADED CHIP CARRIER
PIN FUNCTIONS

LCC

Pin

Function

NC*

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

RST

P3.0/RxD

NC*

P3.1/TxD

P3.2/INT0

P3.3/INT1

Pin

Function

P3.4/T0

P3.5/T1

P3.6/WR

P3.7/RD

XTAL2

XTAL1

NC*

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

P2.6/A14

Pin

Function

P2.7/A15

PSEN

ALE/PROG

NC*

EA/VPP

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

SU00002

* DO NOT CONNECT

PLASTIC QUAD FLAT PACK
PIN FUNCTIONS

Pin

Function

P1.5

P1.6

P1.7

RST

P3.0/RxD

NC*

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

P3.6/WR

P3.7/RD

XTAL2

XTAL1

Pin

Function

NC*

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

P2.6/A14

P2.7/A15

PSEN

ALE/PROG

NC*

EA/V

P0.7/AD7

Pin

Function

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

NC*

P1.0

P1.1

P1.2

P.13

P1.4

PQFP

SU00003

* DO NOT CONNECT

LOGIC SYMBOL

POR

ADDRESS AND

DATA BUS

ADDRESS BUS

SECONDAR

FUNCTIONS

RxD

TxD

INT0

INT1

T0
T1

RST

EA/VPP

PSEN

ALE/PROG

VSS

VCC

XTAL1

XTAL2

SU00004

Philips Semiconductors

Product specification

80C31/80C51/87C51

CMOS single-chip 8-bit microcontrollers

1996 Aug 16

ORDERING INFORMATION

PHILIPS NORTH AMERICA

EPROM

DRAWING

NUMBER

ROMless

ROM

DRAWING

NUMBER

TEMPERATURE RANGE

AND PACKAGE

Freq

MHz

SC87C51CCF40

0590B

0 to +70, Ceramic Dual In-line Package, UV

3.5 to 12

SC87C51CCK44

1472A

0 to +70, Ceramic Leaded Chip Carrier, UV

3.5 to 12

SC87C51CCN40

SOT129-1

SC80C31BCCN40

SC80C51BCCN40

SOT129-1

0 to +70, Plastic Dual In-line Package, OTP

3.5 to 12

SC87C51CCA44

SOT187-2

SC80C31BCCA44

SC80C51BCCA44

SOT187-2

0 to +70, Plastic Leaded Chip Carrier, OTP

3.5 to 12

SC87C51CCB44

SOT307-2

SC80C31BCCB44

SC80C51BCCB44

SOT307-2

0 to +70, Plastic Quad Flat Pack, OTP

3.5 to 12

SC87C51ACF40

0590B

40 to +85, Ceramic Dual In-line Package, UV

3.5 to 12

SC87C51ACN40

SOT129-1

SC80C31BACN40

SC80C51BACN40

SOT129-1

40 to +85, Plastic Dual In-line Package, OTP

3.5 to 12

SC87C51ACA44

SOT187-2

SC80C31BACA44

SC80C51BACA44

SOT187-2

40 to +85, Plastic Leaded Chip Carrier, OTP

3.5 to 12

SC87C51ACB44

SOT307-2

SC80C31BACB44

SC80C51BACB44

SOT307-2

40 to +85, Plastic Quad Flat Pack, OTP

3.5 to 12

SC87C51CGF40

0590B

0 to +70, Ceramic Dual In-line Package, UV

3.5 to 16

SC87C51CGK44

1472A

0 to +70, Ceramic Leaded Chip Carrier, UV

3.5 to 16

SC87C51CGN40

SOT129-1

SC80C31BCGN40

SC80C51BCGN40

SOT129-1

0 to +70, Plastic Dual In-line Package, OTP

3.5 to 16

SC87C51CGA44

SOT187-2

SC80C31BCGA44

SC80C51BCGA44

SOT187-2

0 to +70, Plastic Leaded Chip Carrier, OTP

3.5 to 16

SC87C51CGB44

SOT307-2

SC80C31BCGB44

SC80C51BCGB44

SOT307-2

0 to +70, Plastic Quad Flat Pack, OTP

3.5 to 16

SC87C51AGF40

0590B

40 to +85, Ceramic Dual In-line Package, UV

3.5 to 16

SC87C51AGN40

SOT129-1

SC80C31BAGN40

SC80C51BAGN40

SOT129-1

40 to +85, Plastic Dual In-line Package, OTP

3.5 to 16

SC87C51AGA44

SOT187-2

SC80C31BAGA44

SC80C51BAGA44

SOT187-2

40 to +85, Plastic Leaded Chip Carrier, OTP

3.5 to 16

SC87C51AGB44

SOT307-2

SC80C31BAGB44

SC80C51BAGB44

SOT307-2

40 to +85, Plastic Quad Flat Pack, OTP

3.5 to 16

SC87C51CPF40

0590B

0 to +70, Ceramic Dual In-line Package, UV

3.5 to 24

SC87C51CPK44

1472A

0 to +70, Ceramic Leaded Chip Carrier, UV

3.5 to 24

SC87C51CPN40

SOT129-1

SC80C31BCPN40

SC80C51BCPN40

SOT129-1

0 to +70, Plastic Dual In-line Package, OTP

3.5 to 24

SC87C51CPA44

SOT187-2

SC80C31BCPA44

SC80C51BCPA44

SOT187-2

0 to +70, Plastic Leaded Chip Carrier, OTP

3.5 to 24

SC87C51APF40

0590B

40 to +85, Ceramic Dual In-line Package, UV

SC87C51APN40

SOT129-1

SC80C31BAPN40

SC80C51BAPN40

SOT129-1

40 to +85, Plastic Dual In-line Package, OTP

3.5 to 24

SC87C51APA44

SOT187-2

SC80C31BAPA44

SC80C51BAPA44

SOT187-2

40 to +85, Plastic Leaded Chip Carrier, OTP

3.5 to 24

SC87C51CYF40

0590B

0 to +70, Ceramic Dual In-line Package, UV

3.5 to 33

SC87C51CYK44

1472A

0 to +70, Ceramic Leaded Chip Carrier, UV

3.5 to 33

SC87C51CYN40

SOT129-1

SC80C31BCYN40

SC80C51BCYN40

SOT129-1

0 to +70, Plastic Dual In-line Package, OTP

3.5 to 33

SC87C51CYA44

SOT187-2

SC80C31BCYA44

SC80C51BCYA44

SOT187-2

0 to +70, Plastic Leaded Chip Carrier, OTP

3.5 to 33

1. OTP = One Time Programmable EPROM. UV = UV Erasable EPROM
2. SOT311 replaced by SOT307-2.

Philips Semiconductors

Product specification

80C31/80C51/87C51

CMOS single-chip 8-bit microcontrollers

1996 Aug 16

ORDERING INFORMATION (Continued)

PHILIPS

ROMless

(ORDER NUMBER)

ROMless

(MARKING NUMBER)

ROM

DRAWING

NUMBER

TEMPERATURE RANGE

AND PACKAGE

Freq

MHz

PCB80C31-2 N

PCB80C31BH2-12P

PCB80C51BH-2P

SOT129-1

0 to +70, Plastic Dual In-line Package, OTP

0.5 to 12

PCB80C31-2 A

PCB80C31BH2-12WP

PCB80C51BH-2WP

SOT187-2

0 to +70, Plastic Leaded Chip Carrier, OTP

0.5 to 12

PCB80C31BH2-12H

PCB80C51BH-2H

SOT307-2

0 to +70, Plastic Quad Flat Pack, OTP

0.5 to 12

PCB80C31-3 N

PCB80C31BH3-16P

PCB80C51BH-3P

SOT129-1

0 to +70, Plastic Dual In-line Package, OTP

1.2 to 16

PCB80C31-3 A

PCB80C31BH3-16WP

PCB80C51BH-3WP

SOT187-2

0 to +70, Plastic Leaded Chip Carrier, OTP

1.2 to 16

PCB80C31BH3-16H

PCB80C51BH-3H

SOT307-2

0 to +70, Plastic Quad Flat Pack, OTP

1.2 to 16

PCF80C31-3 N

PCF80C31BH3-16P

PCF80C51BH-3P

SOT129-1

40 to +85, Plastic Dual In-line Package, OTP

1.2 to 16

PCF80C31-3 A

PCF80C31BH3-16WP

PCF80C51BH-3WP

SOT187-2

40 to +85, Plastic Leaded Chip Carrier, OTP

1.2 to 16

PCF80C31BH3-16H

PCF80C51BH-3H

SOT307-2

40 to +85, Plastic Quad Flat Pack, OTP

1.2 to 16

PCA80C31BH3-16P

PCA80C51BH-3P

SOT129-1

40 to +125, Plastic Dual In-line Package

1.2 to 16

PCA80C31BH3-16WP

PCA80C51BH-3WP

SOT187-2

40 to +125, Plastic Leaded Chip Carrier

1.2 to 16

PCB80C31-4 N

PCB80C31BH4-24P

PCB80C51BH-4P

SOT129-1

0 to +70, Plastic Dual In-line Package, OTP

1.2 to 24

PCB80C31-4 A

PCB80C31BH4-24WP

PCB80C51BH-4WP

SOT187-2

0 to +70, Plastic Leaded Chip Carrier, OTP

1.2 to 24

PCB80C31BH4-24H

PCB80C51BH-4H

SOT307-2

0 to +70, Plastic Quad Flat Pack, OTP

1.2 to 24

PCF80C31-4 N

PCF80C31BH4-24P

PCF80C51BH-4P

SOT129-1

40 to +85, Plastic Dual In-line Package, OTP

1.2 to 24

PCF80C31-4 A

PCF80C31BH4-24WP

PCF80C51BH-4WP

SOT187-2

40 to +85, Plastic Leaded Chip Carrier, OTP

1.2 to 24

PCF80C31BH4-24H

PCF80C51BH-4H

SOT307-2

40 to +85, Plastic Leaded Chip Carrier, OTP

1.2 to 24

PCB80C31-5 N

PCB80C31BH5-30P

PCB80C51BH-5P

SOT129-1

0 to +70, Plastic Dual In-line Package

1.2 to 33

PCB80C31-5 A

PCB80C31BH5-30WP

PCB80C51BH-5WP

SOT187-2

0 to +70, Plastic Leaded Chip Carrier

1.2 to 33

PCB80C31-5 B

PCB80C31BH5-30H

PCB80C51BH-5H

SOT307-2

0 to +70, Plastic Quad Flat Pack

1.2 to 33

Philips Semiconductors

Product specification

80C31/80C51/87C51

CMOS single-chip 8-bit microcontrollers

1996 Aug 16

PIN DESCRIPTION

PIN NO.

MNEMONIC

DIP

LCC

QFP

TYPE

NAME AND FUNCTION

Ground: 0V reference.

Power Supply: This is the power supply voltage for normal, idle, and power-down
operation.

P0.00.7

3932

4336

3730

I/O

Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to
them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory. In
this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the
code bytes during program verification in the 87C51. External pull-ups are required during
program verification.

P1.0P1.7

40-44,

I/O

Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 1 pins that are externally pulled low will source current because of the internal
pull-ups. (See DC Electrical Characteristics: I

). Port 1 also receives the low-order address

byte during program memory verification.

P2.0P2.7

2128

2431

1825

I/O

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 2 pins that are externally being pulled low will source current because of the
internal pull-ups. (See DC Electrical Characteristics: I

). Port 2 emits the high-order

address byte during fetches from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it
uses strong internal pull-ups when emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function
register.

P3.0P3.7

1017

11,

1319

713

I/O

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 3 pins that are externally being pulled low will source current because of the
pull-ups. (See DC Electrical Characteristics: I

). Port 3 also serves the special features of

the 80C51 family, as listed below:

RxD (P3.0): Serial input port

TxD (P3.1): Serial output port

INT0 (P3.2): External interrupt

INT1 (P3.3): External interrupt

T0 (P3.4): Timer 0 external input

T1 (P3.5): Timer 1 external input

WR (P3.6): External data memory write strobe

RD (P3.7): External data memory read strobe

RST

Reset: A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to V

permits a power-on reset using only an external

capacitor to V

ALE/PROG

I/O

Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the
address during an access to external memory. In normal operation, ALE is emitted at a
constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking.
Note that one ALE pulse is skipped during each access to external data memory. This pin is
also the program pulse input (PROG) during EPROM programming.

PSEN

Program Store Enable: The read strobe to external program memory. When the device is
executing code from the external program memory, PSEN is activated twice each machine
cycle, except that two PSEN activations are skipped during each access to external data
memory. PSEN is not activated during fetches from internal program memory.

EA/V

External Access Enable/Programming Supply Voltage: EA must be externally held low
to enable the device to fetch code from external program memory locations 0000H to
0FFFH. If EA is held high, the device executes from internal program memory unless the
program counter contains an address greater than 0FFFH. This pin also receives the
12.75V programming supply voltage (V

) during EPROM programming.

XTAL1

Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.

XTAL2

Crystal 2: Output from the inverting oscillator amplifier.

Philips Semiconductors

Product specification

80C31/80C51/87C51

CMOS single-chip 8-bit microcontrollers

1996 Aug 16

Table 1.

80C52/80C54/80C58 Special Function Registers

SYMBOL

DESCRIPTION

DIRECT

ADDRESS

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
MSB

LSB

RESET
VALUE

ACC*

Accumulator

E0H

00H

AUXR#

Auxiliary

8EH

xxxxxxx0B

AUXR1#

Auxiliary 1 (Note 2)

A2H

WUPD

DPS

xxxx00x0B

B register

F0H

00H

DPTR:

Data Pointer (2 bytes)

DPH

Data Pointer High

83H

00H

DPL

Data Pointer Low

82H

00H

IE*

Interrupt Enable

A8H

ET2

ET1

EX1

ET0

EX0

00H

IP*

Interrupt Priority

B8H

PT2

PT1

PX1

PT0

PX0

x0000000B

IPH#

Interrupt Priority High

B7H

PT2H

PSH

PT1H

PX1H

PT0H

PX0H

x0000000B

P0*

Port 0

80H

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

FFH

P1*

Port 1

90H

T2EX

FFH

P2*

Port 2

A0H

AD15

AD14

AD13

AD12

AD11

AD10

AD9

AD8

FFH

P3*

Port 3

B0H

INT1

INT0

TxD

RxD

FFH

PCON#

Power Control

87H

SMOD1

SMOD0

GF1

GF0

IDL

00xx0000B

PSW*

Program Status Word

D0H

RS1

RS0

00H

SADDR#

Slave Address

A9H

00H

SADEN#

Slave Address Mask

B9H

00H

SBUF

Serial Data Buffer

99H

xxxxxxxxB

SCON*

Serial Control

98H

SM0/FE

SM1

SM2

REN

TB8

RB8

00H

Stack Pointer

81H

07H

TCON*

Timer Control

88H

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

00H

T2MOD#

Timer 2 Mode Control

C9H

T2OE

DCEN

xxxxxx00B

TH0

Timer High 0

8CH

00H

TH1

Timer High 1

8DH

00H

TL0

Timer Low 0

8AH

00H

TL1

Timer Low 1

8BH

00H

TMOD

Timer Mode

89H

GATE

C/T

GATE

C/T

00H

SFRs are bit addressable.

SFRs are modified from or added to the 80C51 SFRs.

Reserved bits.

1. Reset value depends on reset source.
2. Available only on SC80C51.

Philips Semiconductors

Product specification

80C31/80C51/87C51

CMOS single-chip 8-bit microcontrollers

1996 Aug 16

OSCILLATOR CHARACTERISTICS

XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator, as shown in the logic symbol.

To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.

RESET

A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-up reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles.

IDLE MODE

In idle mode, the CPU puts itself to sleep while all of the on-chip
peripherals stay active. The instruction to invoke the idle mode is the
last instruction executed in the normal operating mode before the
idle mode is activated. The CPU contents, the on-chip RAM, and all
of the special function registers remain intact during this mode. The
idle mode can be terminated either by any enabled interrupt (at
which time the process is picked up at the interrupt service routine
and continued), or by a hardware reset which starts the processor in
the same manner as a power-on reset.

POWER-DOWN MODE

In the power-down mode, the oscillator is stopped and the
instruction to invoke power-down is the last instruction executed.
Only the contents of the on-chip RAM are preserved. A hardware
reset is the only way to terminate the power-down mode. the control
bits for the reduced power modes are in the special function register
PCON.

Table 2 shows the state of I/O ports during low current operating
modes.

Table 2. External Pin Status During Idle and Power-Down Modes

MODE

PROGRAM MEMORY

ALE

PSEN

PORT 0

PORT 1

PORT 2

PORT 3

Idle

Internal

Data

Idle

External

Float

Data

Address

Data

Power-down

Internal

Data

Power-down

External

Float

Data

ROM CODE SUBMISSION

When submitting ROM code for the 80C51, the following must be specified:
1. 4k byte user ROM data

2. 64 byte ROM encryption key (SC80C51 only)

3. ROM security bits (SC80C51 only).

ADDRESS

CONTENT

BIT(S)

COMMENT

0000H to 0FFFH

DATA

7:0

User ROM Data

1000H to 101FH

KEY

7:0

ROM Encryption Key

1020H

SEC

ROM Security Bit 1

1020H

SEC

ROM Security Bit 2

Security Bit 1: When programmed, this bit has two effects on masked ROM parts:
1. External MOVC is disabled, and
2. EA# is latched on Reset.

Security Bit 2: When programmed, this bit inhibits Verify User ROM.

Philips Semiconductors

Product specification

80C31/80C51/87C51

CMOS single-chip 8-bit microcontrollers

1996 Aug 16

Electrical Deviations from Commercial Specifications for Extended Temperature Range (87C51)
DC and AC parameters not included here are the same as in the commercial temperature range table.

DC ELECTRICAL CHARACTERISTICS

amb

= 40

C to +85

C, V

= 5V

10%, V

= 0V (Philips North America SC87C51);

For SC87C51 (33MHz only), T

amb

= 0

C to +70

C, V

= 5V

amb

= 40

C to +85

C, V

= 5V

10%, V

= 0V (PCB80C31/51 and PCF80C31/51 Philips Parts Only)

TEST

LIMITS

SYMBOL

PARAMETER

CONDITIONS

MIN

MAX

UNIT

Input low voltage, except EA (Philips North America)

0.5

0.2V

0.15

Input low voltage, except EA (Philips)

0.5

0.2V

0.25

IL1

Input low voltage to EA

0.5

0.2V

0.45

Input high voltage, except XTAL1, RST

0.2V

+0.5

IH1

Input high voltage to XTAL1, RST

0.7V

+0.1

+0.5

Logical 0 input current, ports 1, 2, 3

= 0.45V

Logical 1-to-0 transition current, ports 1, 2, 3

= 2.0V

750

Power supply current:

= 4.55.5V

Active mode

@ 16MHz (Philips PCB80C31/51, PCF80C31/51)

Active mode @ 12MHz (Philips North America SC87C51)

Idle mode

@ 16MHz (Philips PCB80C31/51, PCF80C31/51)

6.5

Idle mode @ 12MHz (Philips North America SC87C51)

Power-down mode

(Philips PCB80C31/51, PCF80C31/51)

Power-down mode (Philips North America SC87C51)

NOTES:
1. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t

= t

= 10ns; V

= V

+ 0.5V;

= V

0.5V; XTAL2 not connected; EA = RST = Port 0 = V

2. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t

= t

= 10ns; V

= V

+ 0.5V;

= V

0.5V; XTAL2 not connected; EA = Port 0 = V

; RST = V

SS.

3. The power-down current is measured with all output pins disconnected, XTAL2 not connected, EA = Port 0 = V

; RST = V

SS.

ABSOLUTE MAXIMUM RATINGS

1, 2, 3

PARAMETER

RATING

UNIT

Operating temperature under bias

0 to +70 or 40 to +85

Storage temperature range

65 to +150

Voltage on EA/V

pin to V

0 to +13.0

Voltage on any other pin to V

0.5 to +6.5

Maximum I

per I/O pin

Power dissipation (based on package heat transfer limitations, not device power consumption)

1.5

NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.

3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V

unless otherwise

noted.

Philips Semiconductors

Product specification

80C31/80C51/87C51

CMOS single-chip 8-bit microcontrollers

1996 Aug 16

DC ELECTRICAL CHARACTERISTICS

amb

= 0

C to +70

C or 40

C to +85

C, V

= 5V

20%, V

= 0V (PCB80C31/51 and PCF80C31/51) (12, 16, and 24MHz versions)

amb

= 0

C to +70

C or 40

C to +85

C, V

= 5V

10%, V

= 0V (87C51 12, 16, and 24MHz versions) (PCB80C31/51 33MHz version);

For SC87C51 (33MHz only) T

amb

= 0

C to +70

C, V

= 5V

TEST

LIMITS

SYMBOL

PARAMETER

CONDITIONS

MIN

TYPICAL

MAX

UNIT

Input low voltage, except EA

0.5

0.2V

0.1

IL1

Input low voltage to EA

0.2V

0.3

Input high voltage, except XTAL1, RST

0.2V

+0.9

+0.5

IH1

Input high voltage, XTAL1, RST

0.7V

+0.5

Output low voltage, ports 1, 2, 3

= 1.6mA

0.45

OL1

Output low voltage, port 0, ALE, PSEN

= 3.2mA

0.45

Output high voltage, ports 1, 2, 3, ALE, PSEN

= 60

= 25

= 10

2.4

0.75V

0.9V

V
V
V

OH1

Output high voltage (port 0 in external bus mode)

= 800

= 300

= 80

2.4

0.75V

0.9V

V
V
V

Logical 0 input current, ports 1, 2, 3

= 0.45V

Logical 1-to-0 transition current, ports 1, 2, 3

See note 4

650

Input leakage current, port 0

= V

or V

Power supply current:

Active mode @ 12MHz

(Philips)

Active mode @ 12MHz

(Philips North America)

Idle mode @ 12MHz

(Philips)

Idle mode @ 12MHz (Philips North America)

Power-down mode

(Philips and

Philips North America)

See note 6

11.5

1.3

18
19

4.4

mA
mA
mA
mA

RST

Internal reset pull-down resistor

(Philips North America)

300

(Philips)

150

Pin capacitance

NOTES:
1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V

s of ALE and ports 1 and 3. The noise is due

to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I

can exceed these conditions provided that no

single output sinks more than 5mA and no more than two outputs exceed the test conditions.

3. Capacitive loading on ports 0 and 2 may cause the V

on ALE and PSEN to momentarily fall below the 0.9V

specification when the

address bits are stabilizing.

4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its

maximum value when V

is approximately 2V.

5. I

CCMAX

at other frequencies (for Philips North America parts) is given by: Active mode: I

CCMAX

= 1.43 X FREQ + 1.90;

Idle mode: I

CCMAX

= 0.14 X FREQ +2.31, where FREQ is the external oscillator frequency in MHz. I

CCMAX

is given in mA. See Figure 8.

6. See Figures 9 through 12 for I

test conditions.

7. For Philips North America parts when T

amb

= 40

C to +85

C or Philips parts when T

amb

= 40

C to +125

C, see DC Electrical

Characteristics table on previous page.

8. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t

= t

= 10ns; V

= V

+ 0.5V;

= V

0.5V; XTAL2 not connected; EA = RST = Port 0 = V

9. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t

= t

= 10ns; V

= V

+ 0.5V;

= V

0.5V; XTAL2 not connected; EA = Port 0 = V

; RST = V

SS.

10. The power-down current is measured with all output pins disconnected, XTAL2 not connected, EA = Port 0 = V

; RST = V

SS.

11. Under steady state (non-transient) conditions, I

must be externally limited as follows:

Maximum I

per port pin:

15mA

Maximum I

per 8-bit port:

26mA

Maximum I

total for all outputs:

67mA

If I

exceeds the test condition, V

may exceed the related specification. Pins are not guaranteed to sink current greater than the listed

test conditions.

12. Pin capacitance for the ceramic DIP package is 15pF maximum.

Philips Semiconductors

Product specification

80C31/80C51/87C51

CMOS single-chip 8-bit microcontrollers

1996 Aug 16

DC ELECTRICAL CHARACTERISTICS FOR PHILIPS NORTH AMERICA DEVICES (SC80C31 AND SC80C51)

amb

= 0

C to +70

C or 40

C to +85

C, V

= 5V

10%; V

= 0V

SYMBOL

PARAMETER

TEST

CONDITIONS

LIMITS

UNIT

SYMBOL

PARAMETER

TEST

CONDITIONS

MIN

TYP

MAX

UNIT

Input low voltage

4.5V < V

< 5.5V

0.5

0.2V

0.1

Input high voltage (ports 0, 1, 2, 3, EA)

0.2V

+0.9

+0.5

IH1

Input high voltage, XTAL1, RST

0.7V

+0.5

Output low voltage, ports 1, 2, 3

= 4.5V

= 1.6mA

0.4

OL1

Output low voltage, port 0, ALE, PSEN

8, 7

= 4.5V

= 3.2mA

0.4

Output high voltage, ports 1, 2, 3

= 4.5V

= 30

0.7

OH1

Output high voltage (port 0 in external bus mode),
ALE

, PSEN

= 4.5V

= 3.2mA

0.7

Logical 0 input current, ports 1, 2, 3

= 0.4V

Logical 1-to-0 transition current, ports 1, 2, 3

= 2.0V

See note 4

650

Input leakage current, port 0

0.45 < V

< V

0.3

Power supply current (see Figure 8):

Active mode @ 16MHz

Idle mode @ 16MHz

Power-down mode

See note 5

amb

= 0 to +70

amb

= 40 to +85

11.5

1.3

50
75

RST

Internal reset pull-down resistor

225

Pin capacitance

(except EA)

NOTES:
1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V

s of ALE and ports 1 and 3. The noise is due

can exceed these conditions provided that no

single output sinks more than 5mA and no more than two outputs exceed the test conditions.

3. Capacitive loading on ports 0 and 2 may cause the V

on ALE and PSEN to momentarily fall below the (V

0.7) specification when the

address bits are stabilizing.

4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its

maximum value when V

is approximately 2V.

5. See Figures 9 through 12 for I

test conditions.

Active Mode:

= 1.5

FREQ + 8.0;

Idle Mode:

= 0.14

FREQ +2.31; See Figure 8.

6. This value applies to T

amb

= 0

C to +70

C. For T

amb

= 40

C to +85

C, I

= 750

7. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
8. Under steady state (non-transient) conditions, I

must be externally limited as follows:

Maximum I

per port pin:

15mA (*NOTE: This is 85

C specification.)

Maximum I

per 8-bit port:

26mA

Maximum total I

for all outputs:

71mA

If I

exceeds the test condition, V

may exceed the related specification. Pins are not guaranteed to sink current greater than the listed

test conditions.

9. ALE is tested to V

OH1

, except when ALE is off then V

is the voltage specification.

10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF

(except EA it is 25pF).

Philips Semiconductors

Product specification

80C31/80C51/87C51

CMOS single-chip 8-bit microcontrollers

1996 Aug 16

AC ELECTRICAL CHARACTERISTICS FOR SC87C51 1233MHz PHILIPS NORTH AMERICA DEVICES

amb

= 0

C to +70

C or 40

C to +85

C, V

= 5V

10%, V

= 0V (SC87C51 12, 16 and 24MHz versions);

For SC87C51 (33MHz only) T

amb

= = 0

C to +70

C, V

= 5V

VARIABLE CLOCK

SYMBOL

FIGURE

PARAMETER

MIN

MAX

UNIT

1/t

CLCL

Oscillator frequency: Speed Versions

SC87C51

C
G
P
Y

3.5
3.5
3.5
3.5

12
16
24
33

MHz
MHz
MHz
MHz

LHLL

ALE pulse width

CLCL

AVLL

Address valid to ALE low

CLCL

LLAX

Address hold after ALE low

CLCL

LLIV

ALE low to valid instruction in

CLCL

LLPL

ALE low to PSEN low

CLCL

PLPH

PSEN pulse width

CLCL

PLIV

PSEN low to valid instruction in

CLCL

PXIX

Input instruction hold after PSEN

PXIZ

Input instruction float after PSEN

CLCL

AVIV

Address to valid instruction in

CLCL

PLAZ

PSEN low to address float

Data Memory

RLRH

2, 3

RD pulse width

CLCL

100

WLWH

2, 3

WR pulse width

CLCL

100

RLDV

2, 3

RD low to valid data in

CLCL

RHDX

2, 3

Data hold after RD

RHDZ

2, 3

Data float after RD

CLCL

LLDV

2, 3

ALE low to valid data in

CLCL

150

AVDV

2, 3

Address to valid data in

CLCL

165

LLWL

2, 3

ALE low to RD or WR low

CLCL

+50

AVWL

2, 3

Address valid to WR low or RD low

CLCL

QVWX

2, 3

Data valid to WR transition

CLCL

WHQX

2, 3

Data hold after WR

CLCL

RLAZ

2, 3

RD low to address float

WHLH

2, 3

RD or WR high to ALE high

CLCL

+25

External Clock

CHCX

High time

CLCX

Low time

CLCH

Rise time

CHCL

Fall time

NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. For all Philips North America speed versions only.
4. Interfacing the 87C51 to devices with float times up to 50ns is permitted. This limited bus contention will not cause damage to port 0 drivers.

Philips Semiconductors

Product specification

80C31/80C51/87C51

CMOS single-chip 8-bit microcontrollers

1996 Aug 16

AC ELECTRICAL CHARACTERISTICS FOR PHILIPS DEVICES

amb

= 0

C to +70

C, V

= 5V

20%, V

= 0V (PCB80C31/51, PCF80C31/51)

1, 2, 4, 5

VARIABLE CLOCK

SYMBOL

FIGURE

PARAMETER

MIN

MAX

UNIT

1/t

CLCL

Oscillator frequency: Speed Versions

PCB8031/51

PCA/PCB/PCF80C31/51

PCB/PCF80C31/51

PCB/FB80C31/51

0.5
1.2
1.2
1.2

12
16
24
33

MHz
MHz
MHz
MHz

LHLL

ALE pulse width

CLCL

AVLL

Address valid to ALE low

CLCL

LLAX

Address hold after ALE low

CLCL

LLIV

ALE low to valid instruction in

CLCL

LLPL

ALE low to PSEN low

CLCL

PLPH

PSEN pulse width

CLCL

PLIV

PSEN low to valid instruction in

CLCL

PXIX

Input instruction hold after PSEN

PXIZ

Input instruction float after PSEN

CLCL

AVIV

Address to valid instruction in

CLCL

PLAZ

PSEN low to address float

Data Memory

RLRH

2, 3

RD pulse width

CLCL

100

WLWH

2, 3

WR pulse width

CLCL

100

RLDV

2, 3

RD low to valid data in

CLCL

RHDX

2, 3

Data hold after RD

RHDZ

2, 3

Data float after RD

CLCL

LLDV

2, 3

ALE low to valid data in

CLCL

150

AVDV

2, 3

Address to valid data in

CLCL

165

LLWL

2, 3

ALE low to RD or WR low

CLCL

+50

AVWL

2, 3

Address valid to WR low or RD low

CLCL

QVWX

2, 3

Data valid to WR transition

CLCL

WHQX

2, 3

Data hold after WR

CLCL

RLAZ

2, 3

RD low to address float

WHLH

2, 3

RD or WR high to ALE high

CLCL

+25

External Clock

CHCX

High time

CLCX

Low time

CLCH

Rise time

CHCL

Fall time

NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. For all Philips speed versions only.
4. Interfacing the 80C31/51 to devices with float times up to 30ns is permitted. This limited bus contention will not cause damage to port 0

drivers.

5. V

= 5V

10% for 33MHz.

Philips Semiconductors

Product specification

80C31/80C51/87C51

CMOS single-chip 8-bit microcontrollers

1996 Aug 16

AC ELECTRICAL CHARACTERISTICS FOR PHILIPS NORTH AMERICA DEVICES (SC80C31 AND SC80C51)

amb

= 0

C to +70

C or 40

C to +85

C, V

= 5V

10%, V

= 0V

1, 2, 3

16MHz CLOCK

VARIABLE CLOCK

SYMBOL

FIGURE

PARAMETER

MIN

MAX

MIN

MAX

UNIT

1/t

CLCL

Oscillator frequency

Speed versions : C, G

3.5

MHz

LHLL

ALE pulse width

CLCL

AVLL

Address valid to ALE low

CLCL

LLAX

Address hold after ALE low

CLCL

LLIV

ALE low to valid instruction in

150

CLCL

100

LLPL

ALE low to PSEN low

CLCL

PLPH

PSEN pulse width

142

CLCL

PLIV

PSEN low to valid instruction in

CLCL

105

PXIX

Input instruction hold after PSEN

PXIZ

Input instruction float after PSEN

CLCL

AVIV

Address to valid instruction in

207

CLCL

105

PLAZ

PSEN low to address float

Data Memory

RLRH

2, 3

RD pulse width

275

CLCL

100

WLWH

2, 3

WR pulse width

275

CLCL

100

RLDV

2, 3

RD low to valid data in

147

CLCL

165

RHDX

2, 3

Data hold after RD

RHDZ

2, 3

Data float after RD

CLCL

LLDV

2, 3

ALE low to valid data in

350

CLCL

150

AVDV

2, 3

Address to valid data in

397

CLCL

165

LLWL

2, 3

ALE low to RD or WR low

137

239

CLCL

+50

AVWL

2, 3

Address valid to WR low or RD low

122

CLCL

130

QVWX

2, 3

Data valid to WR transition

CLCL

WHQX

2, 3

Data hold after WR

CLCL

QVWH

Data valid to WR high

287

CLCL

150

RLAZ

2, 3

RD low to address float

WHLH

2, 3

RD or WR high to ALE high

103

CLCL

+40

External Clock

CHCX

High time

CLCL

CLCX

Low time

CLCL

CHCX

CLCH

Rise time

CHCL

Fall time

Shift Register

XLXL

Serial port clock cycle time

750

12t

CLCL

QVXH

Output data setup to clock rising edge

492

10t

CLCL

133

XHQX

Output data hold after clock rising edge

CLCL

117

XHDX

Input data hold after clock rising edge

XHDV

Clock rising edge to input data valid

492

10t

CLCL

133

NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the 80C31/51 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0

drivers.

4. See application note AN457 for external memory interfacing.

Philips Semiconductors

Product specification

80C31/80C51/87C51

CMOS single-chip 8-bit microcontrollers

1996 Aug 16

AC ELECTRICAL CHARACTERISTICS FOR PHILIPS NORTH AMERICA DEVICES (SC80C31 AND SC80C51)

amb

= 0

C to +70

C or 40

C to +85

C, V

= 5V

10%, V

= 0V

1, 2, 3

24MHz CLOCK

VARIABLE CLOCK

33MHz CLOCK

SYMBOL

FIGURE

PARAMETER

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

1/t

CLCL

Oscillator frequency

Speed versions : P (24MHz)

: Y (33MHz)

3.5

MHz

LHLL

ALE pulse width

CLCL

AVLL

Address valid to ALE low

CLCL

LLAX

Address hold after ALE low

CLCL

LLIV

ALE low to valid instruction in

102

CLCL

LLPL

ALE low to PSEN low

CLCL

PLPH

PSEN pulse width

CLCL

PLIV

PSEN low to valid instruction in

CLCL

PXIX

Input instruction hold after PSEN

PXIZ

Input instruction float after PSEN

CLCL

AVIV

Address to valid instruction in

128

CLCL

PLAZ

PSEN low to address float

Data Memory

RLRH

2, 3

RD pulse width

150

CLCL

100

WLWH

2, 3

WR pulse width

150

CLCL

100

RLDV

2, 3

RD low to valid data in

118

CLCL

RHDX

2, 3

Data hold after RD

RHDZ

2, 3

Data float after RD

CLCL

LLDV

2, 3

ALE low to valid data in

183

CLCL

150

AVDV

2, 3

Address to valid data in

210

CLCL

165

105

LLWL

2, 3

ALE low to RD or WR low

175

CLCL

+50

140

AVWL

2, 3

Address valid to WR low or RD low

CLCL

QVWX

2, 3

Data valid to WR transition

CLCL

WHQX

2, 3

Data hold after WR

CLCL

QVWH

Data valid to WR high

162

CLCL

130

RLAZ

2, 3

RD low to address float

WHLH

2, 3

RD or WR high to ALE high

CLCL

+25

External Clock

CHCX

High time

CLCL

CLCX

Low time

CLCL

CHCX

CLCH

Rise time

CHCL

Fall time

Shift Register

XLXL

Serial port clock cycle time

505

12t

CLCL

360

QVXH

Output data setup to clock rising edge

283

10t

CLCL

133

167

XHQX

Output data hold after clock rising edge

CLCL

XHDX

Input data hold after clock rising edge

XHDV

Clock rising edge to input data valid

283

10t

CLCL

133

167

NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the SC80C31/51 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0

drivers.

4. Variable clock is specified for oscillator frequencies greater than 16MHz to 33MHz. For frequencies equal or less than 16MHz, see 16MHz

"AC Electrial Characteristics", page 15.

Philips Semiconductors

Product specification

80C31/80C51/87C51

CMOS single-chip 8-bit microcontrollers

1996 Aug 16

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has five characters. The first character is always
`t' (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal. The
designations are:
A Address
C Clock
D Input data
H Logic level high
I Instruction (program memory contents)
L Logic level low, or ALE

P PSEN
Q Output data
R RD signal
t Time
V Valid
W WR signal
X No longer a valid logic level
Z Float
Examples: t

AVLL

= Time for address valid to ALE low.

LLPL

= Time for ALE low to PSEN low.

PXIZ

ALE

PSEN

PORT 0

PORT 2

A0A15

A8A15

A0A7

AVLL

PXIX

LLAX

INSTR IN

LHLL

PLPH

LLIV

PLAZ

LLPL

AVIV

SU00006

PLIV

Figure 1. External Program Memory Read Cycle

LLAX

ALE

PSEN

PORT 0

PORT 2

A0A7

FROM RI OR DPL

DATA IN

A0A7 FROM PCL

INSTR IN

P2.0P2.7 OR A8A15 FROM DPH

A0A15 FROM PCH

WHLH

LLDV

LLWL

RLRH

RLAZ

AVLL

RHDX

RHDZ

AVWL

AVDV

RLDV

SU00007

Figure 2. External Data Memory Read Cycle

Philips Semiconductors

Product specification

80C31/80C51/87C51

CMOS single-chip 8-bit microcontrollers

1996 Aug 16

EPROM CHARACTERISTICS

The 87C51 is programmed by using a modified Quick-Pulse
Programming

algorithm. It differs from older methods in the value

used for V

(programming supply voltage) and in the width and

number of the ALE/PROG pulses.

The 87C51 contains two signature bytes that can be read and used
by an EPROM programming system to identify the device. The
signature bytes identify the device as an 87C51 manufactured by
Philips Corporation.

Table 3 shows the logic levels for reading the signature bytes, and
for programming the program memory, the encryption table, and the
security bits. The circuit configuration and waveforms for quick-pulse
programming are shown in Figures 13 and 14. Figure 15 shows the
circuit configuration for normal program memory verification.

Quick-Pulse Programming

The setup for microcontroller quick-pulse programming is shown in
Figure 13. Note that the 87C51 is running with a 4 to 6MHz
oscillator. The reason the oscillator needs to be running is that the
device is executing internal address and program data transfers.

The address of the EPROM location to be programmed is applied to
ports 1 and 2, as shown in Figure 13. The code byte to be
programmed into that location is applied to port 0. RST, PSEN and
pins of ports 2 and 3 specified in Table 3 are held at the `Program
Code Data' levels indicated in Table 3. The ALE/PROG is pulsed
low 25 times as shown in Figure 14.

To program the encryption table, repeat the 25 pulse programming
sequence for addresses 0 through 1FH, using the `Pgm Encryption
Table' levels. Do not forget that after the encryption table is
programmed, verification cycles will produce only encrypted data.

To program the security bits, repeat the 25 pulse programming
sequence using the `Pgm Security Bit' levels. After one security bit is
programmed, further programming of the code memory and
encryption table is disabled. However, the other security bit can still
be programmed.

Note that the EA/V

pin must not be allowed to go above the

maximum specified V

level for any amount of time. Even a narrow

glitch above that voltage can cause permanent damage to the
device. The V

source should be well regulated and free of glitches

and overshoot.

Program Verification

If security bit 2 has not been programmed, the on-chip program
memory can be read out for program verification. The address of the
program memory locations to be read is applied to ports 1 and 2 as
shown in Figure 15. The other pins are held at the `Verify Code Data'
levels indicated in Table 3. The contents of the address location will
be emitted on port 0. External pull-ups are required on port 0 for this
operation.

If the encryption table has been programmed, the data presented at
port 0 will be the exclusive NOR of the program byte with one of the
encryption bytes. The user will have to know the encryption table
contents in order to correctly decode the verification data. The
encryption table itself cannot be read out.

Reading the Signature Bytes
The signature bytes are read by the same procedure as a normal
verification of locations 030H and 031H, except that P3.6 and P3.7
need to be pulled to a logic low. The values are:
(030H) = 15H indicates manufactured by Philips
(031H) = 92H indicates 87C51

Program/Verify Algorithms

Any algorithm in agreement with the conditions listed in Table 3, and
which satisfies the timing specifications, is suitable.

Erasure Characteristics

Erasure of the EPROM begins to occur when the chip is exposed to
light with wavelengths shorter than approximately 4,000 angstroms.
Since sunlight and fluorescent lighting have wavelengths in this
range, exposure to these light sources over an extended time (about
1 week in sunlight, or 3 years in room level fluorescent lighting)
could cause inadvertent erasure. For this and secondary effects,
it is recommended that an opaque label be placed over the
window. For elevated temperature or environments where solvents
are being used, apply Kapton tape Fluorglas part number 23455, or
equivalent.

The recommended erasure procedure is exposure to ultraviolet light
(at 2537 angstroms) to an integrated dose of at least 15W-sec/cm

Exposing the EPROM to an ultraviolet lamp of 12,000

W/cm

rating

for 20 to 39 minutes, at a distance of about 1 inch, should be
sufficient.

Erasure leaves the array in an all 1s state.

Table 3. EPROM Programming Modes

MODE

RST

PSEN

ALE/PROG

EA/V

P2.7

P2.6

P3.7

P3.6

Read signature

Program code data

Verify code data

Pgm encryption table

Pgm security bit 1

Pgm security bit 2

NOTES:
1. `0' = Valid low for that pin, `1' = valid high for that pin.
2. V

= 12.75V +0.25V.

3. V

= 5V

10% during programming and verification.

4. *ALE/PROG receives 25 programming pulses while V

is held at 12.75V. Each programming pulse is low for 100

s (

s) and high for a

minimum of 10

Trademark phrase of Intel Corporation.

Philips Semiconductors

Product specification

80C31/80C51/87C51

CMOS single-chip 8-bit microcontrollers

1996 Aug 16

EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS

amb

= 21

C to +27

C, V

= 5V

10%, V

= 0V (See Figure 16)

SYMBOL

PARAMETER

MIN

MAX

UNIT

Programming supply voltage

12.5

13.0

Programming supply current

1/t

CLCL

Oscillator frequency

MHz

AVGL

Address setup to PROG low

48t

CLCL

GHAX

Address hold after PROG

48t

CLCL

DVGL

Data setup to PROG low

48t

CLCL

GHDX

Data hold after PROG

48t

CLCL

EHSH

P2.7 (ENABLE) high to V

48t

CLCL

SHGL

setup to PROG low

GHSL

hold after PROG

GLGH

PROG width

110

AVQV

Address to data valid

48t

CLCL

ELQZ

ENABLE low to data valid

48t

CLCL

EHQZ

Data float after ENABLE

48t

CLCL

GHGL

PROG high to PROG low

PROGRAMMING

VERIFICATION

ADDRESS

DATA IN

DATA OUT

LOGIC 1

LOGIC 0

AVQV

EHQZ

ELQV

SHGL

GHSL

GLGH

GHGL

AVGL

GHAX

DVGL

GHDX

P1.0P1.7
P2.0P2.4

PORT 0

ALE/PROG

EA/V

P2.7
ENABLE

SU00020

EHSH

NOTE:

FOR PROGRAMMING VERIFICATION SEE FIGURE 13.
FOR VERIFICATION CONDITIONS SEE FIGURE 15.

Figure 16. EPROM Programming and Verification

Philips Semiconductors

Product specification

80C31/80C51/87C51

CMOS single-chip 8-bit microcontrollers

1996 Aug 16

0590B

40-PIN (600 mils wide) CERAMIC DUAL IN-LINE (F) PACKAGE (WITH WINDOW (FA) PACKAGE)

NOTES:

Controlling dimension: Inches. Millimeters are

Dimension and tolerancing per

ANSI

Y14. 5M-1982.

"T", "D", and "E" are reference datums on the body

These dimensions measured with the leads

Pin numbers start with Pin #1 and continue

Denotes window location for EPROM products.

and include allowance for glass overrun and meniscus

on the seal line, and lid to base mismatch.

constrained to be perpendicular to plane

counterclockwise to Pin #40 when viewed

shown in parentheses.

from the top.

PIN # 1

0.225 (5.72) MAX.

0.010 (0.254)

0.023 (0.58)

0.015 (0.38)

0.165 (4.19)

0.125 (3.18)

0.070 (1.78)

0.050 (1.27)

SEA

TING

PLANE

0.620 (15.75)

0.590 (14.99)

(NOTE 4)

0.598 (15.19)

0.571 (14.50)

BSC

0.600 (15.24)

0.695 (17.65)

0.600 (15.24)

(NOTE 4)

0.015 (0.38)

0.010 (0.25)

0.175 (4.45)

0.145 (3.68)

0.055 (1.40)

0.020 (0.51)

0.100 (2.54) BSC

2.087 (53.01)

2.038 (51.77)

0.098 (2.49)

0.040 (1.02)

0.098 (2.49)

0.040 (1.02)

SEE NOTE 6

8530590B 06688

Philips Semiconductors

Product specification

80C31/80C51/87C51

CMOS single-chip 8-bit microcontrollers

1996 Aug 16

1472A

44-PIN CERQUAD J-BEND (K) PACKAGE

NOTES:

All dimensions and tolerances to conform

UV window is optional.

Dimensions do not include glass protrusion.

Glass protrusion to be 0.005 inches maximum

Controlling dimension millimeters.

All dimensions and tolerances include

lead trim of

fset and lead plating finish.

Backside solder relief is optional and

dimensions are for reference only

1.02 (0.040) X 45

16.89 (0.665)

16.00 (0.630)

17.65 (0.695)

17.40 (0.685)

CHAMFER

16.89 (0.665)

16.00 (0.630)

17.65 (0.695)

17.40 (0.685)

on each side.

ANSI

Y14.51982.

3 X 0.63 (0.025) R MIN.

3.05 (0.120)

2.29 (0.090)

4.83 (0.190)

3.94 (0.155)

SEA

TING

PLANE

0.38 (0.015)

0.51 (0.02) X 45

17.65 (0.656)

17.40 (0.685)

1.27 (0.050)

12.7 (0.500)

8.13 (0.320)

7.37 (0.290)

40X

4.83 (0.190)

3.94 (0.155)

SEA

TING

PLANE

0.15 (0.006) MIN.

0.25 (0.010) R MIN.

0.508 (0.020) R MIN.

0.25 (0.010)

0.15 (0.006)

+ 5

° °

0.076 (0.003) MIN.

DET

AIL

mm/(inch)

SEE DET

AIL

SEE DET

AIL

DET

AIL

TYP

ALL

SIDES

mm/(inch)

1.52 (0.060) REF

0.482 (0.019 + 0.002)

SEA

TING

PLANE

1.02 + 0.25 (0.040 + 0.010)

BASE PLANE

TYP

4 PLACES

0.73 + 0.08 (0.029 + 0.003)

1.27 (0.050)

TYP

NOMINAL

8.13 (0.320)

7.37 (0.290)

853-1472A 05854

Philips Semiconductors

Product specification

80C31/80C51/87C51

CMOS single-chip 8-bit microcontrollers

Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work
right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only.
Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381

DEFINITIONS

Data Sheet Identification

Product Status

Definition

Objective Specification

Preliminary Specification

Product Specification

Formative or in Design

Preproduction Product

Full Production

This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.

This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.

Philips Semiconductors and Philips Electronics North America Corporation register

eligible circuits under the Semiconductor Chip Protection Act.

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