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Электронный компонент: PCF8570

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DATA SHEET
Product specification
Supersedes data of 1997 Sep 02
File under Integrated Circuits, IC12
1999 Jan 06
INTEGRATED CIRCUITS
PCF8570
256
8-bit static low-voltage RAM
with I
2
C-bus interface
1999 Jan 06
2
Philips Semiconductors
Product specification
256
8-bit static low-voltage RAM with
I
2
C-bus interface
PCF8570
CONTENTS
1
FEATURES
2
APPLICATIONS
3
GENERAL DESCRIPTION
4
QUICK REFERENCE DATA
5
ORDERING INFORMATION
6
BLOCK DIAGRAM
7
PINNING
8
CHARACTERISTICS OF THE I
2
C-BUS
8.1
Bit transfer
8.2
Start and stop conditions
8.3
System configuration
8.4
Acknowledge
8.5
I
2
C-bus protocol
9
LIMITING VALUES
10
HANDLING
11
DC CHARACTERISTICS
12
AC CHARACTERISTICS
13
APPLICATION INFORMATION
13.1
Application example
13.2
Slave address
13.3
Power-saving mode
14
PACKAGE OUTLINES
15
SOLDERING
15.1
Introduction
15.2
Through-hole mount packages
15.2.1
Soldering by dipping or by solder wave
15.2.2
Manual soldering
15.3
Surface mount packages
15.3.1
Reflow soldering
15.3.2
Wave soldering
15.3.3
Manual soldering
15.4
Suitability of IC packages for wave, reflow and
dipping soldering methods
16
DEFINITIONS
17
LIFE SUPPORT APPLICATIONS
18
PURCHASE OF PHILIPS I
2
C COMPONENTS
1999 Jan 06
3
Philips Semiconductors
Product specification
256
8-bit static low-voltage RAM with
I
2
C-bus interface
PCF8570
1
FEATURES
Operating supply voltage 2.5 to 6.0 V
Low data retention voltage; minimum 1.0 V
Low standby current; maximum 15
A
Power-saving mode; typical 50 nA
Serial input/output bus (I
2
C-bus)
Address by 3 hardware address pins
Automatic word address incrementing
Available in DIP8 and SO8 packages.
2
APPLICATIONS
Telephony:
RAM expansion for stored numbers in repertory
dialling (e.g. PCD33xxA applications)
General purpose RAM for applications requiring
extremely low current and low-voltage RAM retention,
such as battery or capacitor-backed.
Radio, television and video cassette recorder:
channel presets
General purpose:
RAM expansion for the microcontroller families
PCD33xxA, PCF84CxxxA, P80CLxxx and most other
microcontrollers.
3
GENERAL DESCRIPTION
The PCF8570 is a low power static CMOS RAM,
organized as 256 words by 8-bits.
Addresses and data are transferred serially via a two-line
bidirectional bus (I
2
C-bus). The built-in word address
register is incremented automatically after each written or
read data byte. Three address pins, A0, A1 and A2 are
used to define the hardware address, allowing the use of
up to 8 devices connected to the bus without additional
hardware.
4
QUICK REFERENCE DATA
5
ORDERING INFORMATION
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DD
supply voltage
2.5
6.0
I
DD
supply current (standby)
f
SCL
= 0 Hz
-
15
A
I
DDR
supply current (power-saving mode)
T
amb
= 25
C
-
400
nA
T
amb
operating ambient temperature
-
40
+85
C
T
stg
storage temperature
-
65
+150
C
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
PCF8570P
DIP8
plastic dual in-line package; 8 leads (300 mil)
SOT97-1
PCF8570T
SO8
plastic small outline package; 8 leads; body width 7.5 mm
SOT176-1
1999 Jan 06
4
Philips Semiconductors
Product specification
256
8-bit static low-voltage RAM with
I
2
C-bus interface
PCF8570
6
BLOCK DIAGRAM
Fig.1 Block diagram.
handbook, full pagewidth
MLB928
WORD
ADDRESS
REGISTER
SHIFT
REGISTER
POWER
ON
RESET
INPUT
FILTER
ROW
SELECT
MEMORY
CELL
ARRAY
COLUMN
SELECT
MULTIPLEXER
R/W
CONTROL
I C BUS
CONTROL
2
6
5
SCL
SDA
3
A2
2
A1
1
A0
8
VDD
4
VSS
7
TEST
PCF8570
7
8
7
PINNING
SYMBOL
PIN
DESCRIPTION
A0
1
hardware address input 0
A1
2
hardware address input 1
A2
3
hardware address input 2
V
SS
4
negative supply
SDA
5
serial data input/output
SCL
6
serial clock input
TEST
7
Input for power-saving mode (see section
"Power-saving mode"). Also used as a test output
during manufacture. TEST should be tied to V
SS
during normal operation.
V
DD
8
positive supply
Fig.2 Pin configuration.
page
1
2
3
4
8
7
6
5
MLB929
PCF8570
SCL
SDA
A2
A1
A0
VDD
VSS
TEST
1999 Jan 06
5
Philips Semiconductors
Product specification
256
8-bit static low-voltage RAM with
I
2
C-bus interface
PCF8570
8
CHARACTERISTICS OF THE I
2
C-BUS
The I
2
C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL). Both
lines must be connected to a positive supply via a pull-up
resistor. Data transfer may be initiated only when the bus
is not busy.
8.1
Bit transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as a control signal.
Fig.3 Bit transfer.
MBA607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
8.2
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is
defined as the stop condition (P).
Fig.4 Definition of start and stop conditions.
MBA608
SDA
SCL
P
STOP condition
SDA
SCL
S
START condition
1999 Jan 06
6
Philips Semiconductors
Product specification
256
8-bit static low-voltage RAM with
I
2
C-bus interface
PCF8570
8.3
System configuration
A device generating a message is a `transmitter', a device receiving a message is the `receiver'. The device that controls
the message is the `master' and the devices which are controlled by the master are the `slaves'.
Fig.5 System configuration.
MBA605
MASTER
TRANSMITTER /
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER /
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER /
RECEIVER
SDA
SCL
8.4
Acknowledge
The number of data bytes transferred between the start
and stop conditions from transmitter to receiver is
unlimited. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH level
signal put on the bus by the transmitter during which time
the master generates an extra acknowledge related clock
pulse. A slave receiver which is addressed must generate
an acknowledge after the reception of each byte. Also a
master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the
slave transmitter.
The device that acknowledges must pull down the SDA
line during the acknowledge clock pulse, so that the SDA
line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration). A master receiver must
signal an end of data to the transmitter by not generating
an acknowledge on the last byte that has been clocked out
of the slave. In this event the transmitter must leave the
data line HIGH to enable the master to generate a stop
condition.
Fig.6 Acknowledgement on the I
2
C-bus.
handbook, full pagewidth
MBA606 - 1
START
condition
S
SCL FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
clock pulse for
acknowledgement
1
2
8
9
1999 Jan 06
7
Philips Semiconductors
Product specification
256
8-bit static low-voltage RAM with
I
2
C-bus interface
PCF8570
8.5
I
2
C-bus protocol
Before any data is transmitted on the I
2
C-bus, the device which should respond is addressed first. The addressing is
always carried out with the first byte transmitted after the start procedure. The I
2
C-bus configuration for the different
PCF8570 WRITE and READ cycles is shown in Figs 7, 8 and 9.
Fig.7 Master transmits to slave receiver (WRITE) mode.
handbook, full pagewidth
S
0 A
SLAVE ADDRESS
WORD ADDRESS
A
A
DATA
P
acknowledgement
from slave
acknowledgement
from slave
acknowledgement
from slave
R/W
auto increment
memory word address
MBD822
n bytes
Fig.8 Master reads after setting word address (WRITE word address; READ data).
handbook, full pagewidth
S
0 A
SLAVE ADDRESS
WORD ADDRESS
A
A
SLAVE ADDRESS
acknowledgement
from slave
acknowledgement
from slave
acknowledgement
from slave
R/W
acknowledgement
from master
A
DATA
auto increment
memory word address
MLB930
P
no acknowledgement
from master
1
DATA
auto increment
memory word address
last byte
R/W
S
1
n bytes
at this moment master -
transmitter becomes
master - receiver and
PCF8570 slave -
receiver becomes
slave - transmitter
1999 Jan 06
8
Philips Semiconductors
Product specification
256
8-bit static low-voltage RAM with
I
2
C-bus interface
PCF8570
9
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
10 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC12 under
"Handling MOS Devices".
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
V
DD
supply voltage (pin 8)
-
0.8
+8.0
V
V
I
input voltage (any input)
-
0.8
V
DD
+ 0.8
V
I
I
DC input current
-
10
mA
I
O
DC output current
-
10
mA
I
DD
positive supply current
-
50
mA
I
SS
negative supply current
-
50
mA
P
tot
total power dissipation per package
-
300
mW
P
O
power dissipation per output
-
50
mW
T
amb
operating ambient temperature
-
40
+85
C
T
stg
storage temperature
-
65
+150
C
Fig.9 Master reads slave immediately after first byte (READ mode).
andbook, full pagewidth
S
1 A
SLAVE ADDRESS
DATA
A
1
DATA
acknowledgement
from slave
acknowledgement
from slave
acknowledgement
from slave
R/W
auto increment
word address
MBD824
auto increment
word address
n bytes
last bytes
P
1999 Jan 06
9
Philips Semiconductors
Product specification
256
8-bit static low-voltage RAM with
I
2
C-bus interface
PCF8570
11 DC CHARACTERISTICS
V
DD
= 2.5 to 6.0 V; V
SS
= 0 V; T
amb
=
-
40 to +85
C; unless otherwise specified.
Notes
1. The Power-on reset circuit resets the I
2
C-bus logic when V
DD
< V
POR
. The status of the device after a Power-on reset
condition can be tested by sending the slave address and testing the acknowledge bit.
2. If the input voltages are a diode voltage above or below the supply voltage V
DD
or V
SS
an input current will flow; this
current must not exceed
0.5 mA.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
V
DD
supply voltage
2.5
-
6.0
V
I
DD
supply current
standby mode
V
I
= V
DD
or V
SS
;
f
SCL
= 0 Hz;
T
amb
=
-
25 to +70
C
-
-
5
A
operating mode
V
I
= V
DD
or V
SS
;
f
SCL
= 100 Hz
-
-
200
A
V
POR
Power-on reset voltage
note 1
1.5
1.9
2.3
V
Inputs, input/output SDA
V
IL
LOW level input voltage
note 2
-
0.8
-
0.3V
DD
V
V
IH
HIGH level input voltage
note 2
0.7V
DD
-
V
DD
+ 0.8 V
I
OL
LOW level output current
V
OL
= 0.4 V
3
-
-
mA
I
LI
input leakage current
V
I
= V
DD
or V
SS
-
1
-
+1
A
Inputs A0, A1, A2 and TEST
I
LI
input leakage current
V
I
= V
DD
or V
SS
-
250
-
+250
nA
Inputs SCL and SDA
C
i
input capacitance
V
I
= V
SS
-
-
7
pF
Low V
DD
data retention
V
DDR
supply voltage for data retention
1
-
6
V
I
DDR
supply current
V
DDR
= 1 V
-
-
5
A
V
DDR
= 1 V;
T
amb
=
-
25 to +70
C
-
-
2
A
Power-saving mode (see Figs 13 and 14)
I
DDR
supply current
TEST = V
DD
; T
amb
= 25
C
-
50
400
nA
t
HD2
recovery time
-
50
-
s
1999 Jan 06
10
Philips Semiconductors
Product specification
256
8-bit static low-voltage RAM with
I
2
C-bus interface
PCF8570
12 AC CHARACTERISTICS
All timing values are valid within the operating supply voltage and ambient temperature range and reference to V
IL
and
V
IH
with an input voltage swing of V
SS
to V
DD
.
Note
1. A detailed description of the I
2
C-bus specification, with applications, is given in brochure
"The I
2
C-bus and how to
use it". This brochure may be ordered using the code 9398 393 40011.
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
I
2
C-bus timing (see Fig.10; note 1)
f
SCL
SCL clock frequency
-
-
100
kHz
t
SP
tolerable spike width on bus
-
-
100
ns
t
BUF
bus free time
4.7
-
-
s
t
SU;STA
START condition set-up time
4.7
-
-
s
t
HD;STA
START condition hold time
4.0
-
-
s
t
LOW
SCL LOW time
4.7
-
-
s
t
HIGH
SCL HIGH time
4.0
-
-
s
t
r
SCL and SDA rise time
-
-
1.0
s
t
f
SCL and SDA fall time
-
-
0.3
s
t
SU;DAT
data set-up time
250
-
-
ns
t
HD;DAT
data hold time
0
-
-
ns
t
VD;DAT
SCL LOW-to-data out valid
-
-
3.4
s
t
SU;STO
STOP condition set-up time
4.0
-
-
s
Fig.10 I
2
C-bus timing diagram; rise and fall times refer to V
IL
and V
IH
.
handbook, full pagewidth
PROTOCOL
SCL
SDA
MBD820
BIT 0
LSB
(R/W)
t HD;STA
t
SU;DAT
t
HD;DAT
t
VD;DAT
t SU;STO
t
f
r
t
t
BUF
t
SU;STA
t
LOW
t HIGH
1 / f SCL
START
CONDITION
(S)
BIT 7
MSB
(A7)
BIT 6
(A6)
ACKNOWLEDGE
(A)
STOP
CONDITION
(P)
1999 Jan 06
11
Philips Semiconductors
Product specification
256
8-bit static low-voltage RAM with
I
2
C-bus interface
PCF8570
13 APPLICATION INFORMATION
13.1
Application example
Fig.11 Application diagram.
It is recommended that a 4.7
F/10 V solid aluminium capacitor (SAL) be connected between V
DD
and V
SS
.
handbook, full pagewidth
MLB931
SCL
SDA
VSS
A1
A0
A2
TEST
PCF8570
'1010'
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
VDD
SDA
SCL
R
R
V DD
(I C bus)
2
R: pull up resistor
R =
r
t
C BUS
VDD
SCL
SDA
VSS
A1
A0
A2
TEST
PCF8570
'1010'
VDD
VDD
SCL
SDA
VSS
A1
A0
A2
TEST
PCF8570
'1010'
V DD
1
VDD
1
VDD
1
VDD
1
0
0
0
0
0
up to 8 PCF8570C
1999 Jan 06
12
Philips Semiconductors
Product specification
256
8-bit static low-voltage RAM with
I
2
C-bus interface
PCF8570
13.2
Slave address
The PCF8570 has a fixed combination 1 0 1 0 as group 1, while group 2 is fully programmable (see Fig.12).
13.3
Power-saving mode
With the condition TEST = V
DD
or V
DDR
the PCF8570 goes into the power-saving mode and I
2
C-bus logic is reset.
Fig.12 Slave address.
handbook, halfpage
MLB892
1
0
1
0
A2
A1
A0 R/W
group 1
group 2
Fig.13 Timing for power-saving mode.
(1) Power-saving mode without 5 V supply voltage.
(2) Power-saving mode with 5 V supply voltage.
(3) t
SU
and t
HD1
4
s and t
HD2
50
s.
handbook, full pagewidth
MLB932
,,
,,
,,,
,,,
,,,
,,,
,,
,,
,,,
,,,
,,,
,,,
power saving
mode (1)
TEST = VDDR
power saving
mode (2)
TEST = VDD
operating mode
TEST
SCL
SDA
VDD
IDD
VDD
VDDR
0 V
VDD
VDDR
0 V
VDD
VDDR
0 V
VDD
VDDR
0 V
IDD
IDDS
t SU
t HD1
t SU
t HD2
(3)
(3)
(3)
(3)
1999 Jan 06
13
Philips Semiconductors
Product specification
256
8-bit static low-voltage RAM with
I
2
C-bus interface
PCF8570
Fig.14 Application example for power-saving mode.
It is recommended that a 4.7
F/10 V solid aluminium capacitor (SAL) be connected between V
DD
and V
SS
.
(1) In the operating mode TEST = 0 V; in the power-saving mode TEST = V
DDR
.
handbook, full pagewidth
MLB933
TEST
SCL
SDA
VSS
PCF8570
MICROCONTROLLER
4
VDD
VDDR
8
7
6
5
A0
A1
A2
1
2
3
1.2 V
(NiCd)
5 V
(1)
1999 Jan 06
14
Philips Semiconductors
Product specification
256
8-bit static low-voltage RAM with
I
2
C-bus interface
PCF8570
14 PACKAGE OUTLINES
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
SOT97-1
92-11-17
95-02-04
UNIT
A
max.
1
2
b
1
(1)
(1)
(1)
b
2
c
D
E
e
M
Z
H
L
mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
min.
A
max.
b
max.
w
M
E
e
1
1.73
1.14
0.53
0.38
0.36
0.23
9.8
9.2
6.48
6.20
3.60
3.05
0.254
2.54
7.62
8.25
7.80
10.0
8.3
1.15
4.2
0.51
3.2
inches
0.068
0.045
0.021
0.015
0.014
0.009
1.07
0.89
0.042
0.035
0.39
0.36
0.26
0.24
0.14
0.12
0.01
0.10
0.30
0.32
0.31
0.39
0.33
0.045
0.17
0.020
0.13
b
2
050G01
MO-001AN
M
H
c
(e )
1
M
E
A
L
seating plane
A
1
w
M
b
1
e
D
A
2
Z
8
1
5
4
b
E
0
5
10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
pin 1 index
DIP8: plastic dual in-line package; 8 leads (300 mil)
SOT97-1
1999 Jan 06
15
Philips Semiconductors
Product specification
256
8-bit static low-voltage RAM with
I
2
C-bus interface
PCF8570
UNIT
A
max.
A
1
A
2
A
3
b
p
c
D
(1)
E
(1)
Z
(1)
e
H
E
L
L
p
Q
y
w
v
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
inches
2.65
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
7.65
7.45
7.6
7.4
1.27
10.65
10.00
1.1
1.0
2.0
1.8
8
0
o
o
0.25
0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
1.1
0.45
SOT176-1
95-02-25
97-05-22
X
4
8
A
A
1
A
2
w
M
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v
M
A
5
1
(A )
3
A
y
0.25
0.10
0.012
0.004
0.096
0.089
0.019
0.014
0.013
0.009
0.30
0.29
0.30
0.29
0.050
1.45
0.057
0.25
0.01
0.419
0.394
0.043
0.039
0.079
0.071
0.01
0.004
0.043
0.018
0.01
0
5
10 mm
scale
pin 1 index
SO8: plastic small outline package; 8 leads; body width 7.5 mm
SOT176-1
1999 Jan 06
16
Philips Semiconductors
Product specification
256
8-bit static low-voltage RAM with
I
2
C-bus interface
PCF8570
15 SOLDERING
15.1
Introduction
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
"Data Handbook IC26; Integrated Circuit Packages"
(document order number 9398 652 90011).
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mount components are mixed on
one printed-circuit board. However, wave soldering is not
always suitable for surface mount ICs, or for printed-circuit
boards with high population densities. In these situations
reflow soldering is often used.
15.2
Through-hole mount packages
15.2.1
S
OLDERING BY DIPPING OR BY SOLDER WAVE
The maximum permissible temperature of the solder is
260
C; solder at this temperature must not be in contact
with the joints for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
stg(max)
). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
15.2.2
M
ANUAL SOLDERING
Apply the soldering iron (24 V or less) to the lead(s) of the
package, either below the seating plane or not more than
2 mm above it. If the temperature of the soldering iron bit
is less than 300
C it may remain in contact for up to
10 seconds. If the bit temperature is between
300 and 400
C, contact may be up to 5 seconds.
15.3
Surface mount packages
15.3.1
R
EFLOW SOLDERING
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical reflow peak temperatures range from
215 to 250
C. The top-surface temperature of the
packages should preferable be kept below 230
C.
15.3.2
W
AVE SOLDERING
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
For packages with leads on two sides and a pitch (e):
larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
For packages with leads on four sides, the footprint must
be placed at a 45
angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250
C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
15.3.3
M
ANUAL SOLDERING
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300
C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320
C.
1999 Jan 06
17
Philips Semiconductors
Product specification
256
8-bit static low-voltage RAM with
I
2
C-bus interface
PCF8570
15.4
Suitability of IC packages for wave, reflow and dipping soldering methods
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
"Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods".
2. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
3. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
4. If wave soldering is considered, then the package must be placed at a 45
angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
MOUNTING
PACKAGE
SOLDERING METHOD
WAVE
REFLOW
(1)
DIPPING
Through-hole mount DBS, DIP, HDIP, SDIP, SIL
suitable
(2)
-
suitable
Surface mount
BGA, SQFP
not suitable
suitable
-
HLQFP, HSQFP, HSOP, HTSSOP, SMS
not suitable
(3)
suitable
-
PLCC
(4)
, SO, SOJ
suitable
suitable
-
LQFP, QFP, TQFP
not recommended
(4)(5)
suitable
-
SSOP, TSSOP, VSO
not recommended
(6)
suitable
-
1999 Jan 06
18
Philips Semiconductors
Product specification
256
8-bit static low-voltage RAM with
I
2
C-bus interface
PCF8570
16 DEFINITIONS
17 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
18 PURCHASE OF PHILIPS I
2
C COMPONENTS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Purchase of Philips I
2
C components conveys a license under the Philips' I
2
C patent to use the
components in the I
2
C system provided the system conforms to the I
2
C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1999 Jan 06
19
Philips Semiconductors
Product specification
256
8-bit static low-voltage RAM with
I
2
C-bus interface
PCF8570
NOTES
Internet: http://www.semiconductors.philips.com
Philips Semiconductors a worldwide company
Philips Electronics N.V. 1999
SCA61
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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Printed in The Netherlands
415106/00/04/pp20
Date of release: 1999 Jan 06
Document order number:
9397 750 04971