Philips Semiconductors

Product specification

87C652/87C654

80C51 8-bit microcontroller
8K/16K, 256 OTP, I

1999 Jul 23

853-1689 22042

DESCRIPTION

The 87C652/87C654 single-chip 8-Bit
microcontroller is manufactured in an
advanced CMOS process and is a derivative
of the 80C51 microcontroller family. The
87C652/87C654 has the same instruction
set as the 80C51. Three versions of the
derivative exist:

80C652--ROMless
83C652/83C654--8 Kbyte, 16 Kbyte ROM
87C652/87C654--8 Kbyte, 16 Kbyte OTP

The ROMless and ROM are in separate
datasheets.

This device provides architectural
enhancements that make it applicable in a
variety of applications for general control
systems. The 87C654 contains a non-volatile
16k

8 EPROM and the 87C652 contains an

8k x 8 EPROM. Both have a volatile 256

read/write data memory, four 8-bit I/O ports,
two 16-bit timer/event counters (identical to
the timers of the 80C51), a multi-source,
two-priority-level, nested interrupt structure,
an I

C interface, UART and on-chip oscillator

and timing circuits. For systems that require
extra capability, the 87C652/87C654 can be
expanded using standard TTL compatible
memories and logic.

The device also functions as an arithmetic
processor having facilities for both binary and
BCD arithmetic plus bit-handling capabilities.
The instruction set consists of over 100
instructions: 49 one-byte, 45 two-byte and 17
three-byte. With a 16 MHz crystal, 58% of the
instructions are executed in 0.75

s and 40%

in 1.5

s. Multiply and divide instructions

require 3

FEATURES

80C51 central processing unit

16k

8 EPROM or 8k x 8 EPROM

expandable externally to 64k bytes

256

8 RAM, expandable externally to

64k bytes

Two standard 16-bit timer/counters

Four 8-bit I/O ports

C-bus serial I/O port with byte oriented

master and slave functions

Full-duplex UART facilities

Power control modes

Idle mode

Power-down mode

Extended temperature range

OTP package available

Two speed ranges

16 MHz

20 MHz

PIN CONFIGURATIONS

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

SCL/P1.6

RST

RxD/P3.0

TxD/P3.1

INT0/P3.2

INT1/P3.3

T0/P3.4

T1/P3.5

SDA/P1.7

WR/P3.6

RD/P3.7

XTAL2

XTAL1

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

P2.6/A14

P2.7/A15

PSEN

ALE/PROG

EA/V

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

PLASTIC

DUAL

IN-LINE

PACKAGE

SU00259

ORDERING INFORMATION

EPROM

TEMPERATURE RANGE

C AND PACKAGE

FREQ

Drawing

EPROM

TEMPERATURE RANGE C AND PACKAGE

MHz

Number

S87C654-4N40

0 to +70, Plastic Dual In-line Package

SOT129-1

S87C654-4A44

0 to +70, Plastic Leaded Chip Carrier

SOT187-2

S87C6544B44

0 to +70, Plastic Quad Flat Pack

SOT307-2

S87C654-5N40

40 to +85, Plastic Dual In-line Package

SOT129-1

S87C654-5A44

40 to +85, Plastic Leaded Chip Carrier

SOT187-2

S87C654-5B44

40 to +85, Plastic Quad Flat Pack

SOT307-2

S87C6547N40

0 to +70, Plastic Dual In-line Package

SOT129-1

S87C6547A44

0 to +70, Plastic Leaded Chip Carrier

SOT187-2

S87C652-4N40

0 to +70, Plastic Dual In-line Package

SOT129-1

S87C652-4A44

0 to +70, Plastic Leaded Chip Carrier

SOT187-2

S87C652-4B44

0 to +70, Plastic Quad Flat Pack

SOT307-2

S87C652-5A44

40 to +85, Plastic Leaded Chip Carrier

SOT187-2

NOTES:
1. For ROM see 83C654 data sheet and 83C652/80C652 data sheet

Philips Semiconductors

Product specification

87C652/87C654

80C51 8-bit microcontroller
8K/16K, 256 OTP, I

1999 Jul 23

PLASTIC LEADED CHIP
CARRIER PIN FUNCTIONS

LCC

Pin

Function

NC*

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6/SCL

P1.7/SDA

RST

P3.0/RxD

NC*

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

P3.6/WR

P3.7/RD

XTAL2

XTAL1

Pin

Function

NC*

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

P2.6/A14

P2.7/A15

PSEN

ALE/PROG

NC*

EA/V

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

SU00260

* NO INTERNAL CONNECTION

PLASTIC QUAD FLAT PACK
PIN FUNCTIONS

Pin

Function

P1.5

P1.6/SCL

P1.7/SDA

RST

P3.0/RxD

NC*

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

P3.6/WR

P3.7/RD

XTAL2

XTAL1

NC*

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

Pin

Function

P2.5/A13

P2.6/A14

P2.7/A15

PSEN

ALE/PROG

NC*

EA/V

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

NC*

P1.0

P1.1

P1.2

P.13

P1.4

PQFP

SU00261

* NO INTERNAL CONNECTION

Philips Semiconductors

Product specification

87C652/87C654

80C51 8-bit microcontroller
8K/16K, 256 OTP, I

1999 Jul 23

PIN DESCRIPTIONS

PIN NUMBER

MNEMONIC

DIP

LCC

QFP

TYPE

NAME AND FUNCTION

Ground: 0 V reference.

Power Supply: This is the power supply voltage for normal, idle, and power-down operation.

P0.00.7

3932

4336

3730

I/O

Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them
float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order
address and data bus during accesses to external program and data memory. In this
application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code
bytes during program verification in the 87C654. External pull-ups are required during
program verification.

P1.0P1.7

4044,

I/O

Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7
which are open drain. Port 1 pins that have 1s written to them are pulled high by the internal
pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will
source current because of the internal pull-ups. (See DC Electrical Characteristics: I

Port 1 also receives the low-order address byte during program memory verification.
Alternate functions include:

P1.6

I/O

SCL: I

C-bus serial port clock line.

P1.7

I/O

SDA: I

C-bus serial port data line.

P2.0P2.7

2128

2431

1825

I/O

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 2 pins that are externally being pulled low will source current because of the internal
pull-ups. (See DC Electrical Characteristics: I

). Port 2 emits the high-order address byte

during fetches from external program memory and during accesses to external data memory
that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal
pull-ups when emitting 1s. During accesses to external data memory that use 8-bit
addresses (MOV @Ri), port 2 emits the contents of the P2 special function register.

P3.0P3.7

1017

11,

1319

713

I/O

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 3 pins that are externally being pulled low will source current because of the pull-ups.
(See DC Electrical Characteristics: I

). Port 3 also serves the special features of the 80C51

family, as listed below:

RxD (P3.0): Serial input port

TxD (P3.1): Serial output port

INT0 (P3.2): External interrupt

INT1 (P3.3): External interrupt

T0 (P3.4): Timer 0 external input

T1 (P3.5): Timer 1 external input

WR (P3.6): External data memory write strobe

RD (P3.7): External data memory read strobe

RST

Reset: A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to V

permits a power-on reset using only an external

capacitor to V

ALE/PROG

I/O

Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the
address during an access to external memory. In normal operation, ALE is emitted at a
constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking.
Note that one ALE pulse is skipped during each access to external data memory. This pin is
also the program pulse input (PROG) during EPROM programming.

PSEN

Program Store Enable: The read strobe to external program memory. When the 87C654 is
executing code from the external program memory, PSEN is activated twice each machine
cycle, except that two PSEN activations are skipped during each access to external data
memory. PSEN is not activated during fetches from internal program memory.

EA/V

External Access Enable/Programming Supply Voltage: EA must be externally held low to
enable the device to fetch code from external program memory locations 0000H and 1FFFH
for 87C652 and 3FFFH for 87C654. If EA is held high, the device executes from internal
program memory unless the program counter contains an address greater than 3FFFH. This
pin also receives the 12.75 V programming supply voltage (V

) during EPROM programming.

XTAL1

Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.

XTAL2

Crystal 2: Output from the inverting oscillator amplifier.

NOTE:
To avoid "latch-up" effect at power-on, the voltage on any pin at any time must not be higher than V

+ 0.5 V or V

0.5 V, respectively.

Philips Semiconductors

Product specification

87C652/87C654

80C51 8-bit microcontroller
8K/16K, 256 OTP, I

1999 Jul 23

Table 1.

8XC652/654 Special Function Registers

SYMBOL

DESCRIPTION

DIRECT

ADDRESS

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
MSB

LSB

RESET
VALUE

ACC*

Accumulator

E0H

00H

B register

F0H

00H

DPTR:

DPH
DPL

Data pointer
(2 bytes)
Data pointer high
Data pointer low

83H
82H

00H
00H

IE*#

Interrupt enable

A8H

ES1

ES0

ET1

EX1

ET0

EX0

0x000000B

IP*#

Interrupt priority

B8H

PS1

PS0

PT1

PX1

PT0

PX0

xx000000B

P0*

Port 0

80H

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

FFH

P1*#

Port 1

90H

SDA

SCL

FFH

P2*

Port 2

A0H

A15

A14

A13

A12

A11

A10

FFH

P3*

Port 3

B0H

INT1

INT0

TXD

RXD

FFH

PCON#

Power control

87H

SMOD

GF1

GF0

IDL

0xxx0000B

S0CON*#

Serial 0 port control

98H

SM0

SM1

SM2

REN

TB8

RB8

00H

S0BUF#

Serial 0 data buffer

99H

xxxxxxxxB

PSW*

Program status word

D0H

RS1

RS0

00H

S1DAT#

Serial 1 data

DAH

00H

Stack pointer

81H

07H

S1ADR#

Serial 1 address

DBH

SLAVE ADDRESS

00H

S1STA#

Serial 1 status

D9H

SC4

SC3

SC2

SC1

SC0

F8H

S1CON*#

Serial 1 control

D8H

CR2

ENS1

STA

STO

CR1

CR0

00000000B

TCON*

Timer control

88H

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

00H

TH1

Timer high 1

8DH

00H

TH0

Timer high 0

8CH

00H

TL1

Timer low 1

8BH

00H

TL0

Timer low 0

8AH

00H

TMOD

Timer mode

89H

GATE

C/T

GATE

C/T

00H

SFRs are bit addressable.

SFRs are modified from or added to the 80C51 SFRs.

Philips Semiconductors

Product specification

87C652/87C654

80C51 8-bit microcontroller
8K/16K, 256 OTP, I

1999 Jul 23

OSCILLATOR
CHARACTERISTICS

XTAL1 and XTAL2 are the input and output,
respectively, of an inverting amplifier. The
pins can be configured for use as an on-chip
oscillator, as shown in the Logic Symbol.

To drive the device from an external clock
source, XTAL1 should be driven while XTAL2
is left unconnected. There are no
requirements on the duty cycle of the
external clock signal, because the input to
the internal clock circuitry is through a
divide-by-two flip-flop. However, minimum
and maximum high and low times specified in
the data sheet must be observed.

Reset

A reset is accomplished by holding the RST
pin high for at least two machine cycles (24
oscillator periods), while the oscillator is
running. To insure a good power-on reset, the
RST pin must be high long enough to allow
the oscillator time to start up (normally a few

milliseconds) plus two machine cycles. At
power-on, the voltage on V

and RST must

come up at the same time for a proper
start-up.

Idle Mode

In the idle mode, the CPU puts itself to sleep
while all of the on-chip peripherals stay
active. The instruction to invoke the idle
mode is the last instruction executed in the
normal operating mode before the idle mode
is activated. The CPU contents, the on-chip
RAM, and all of the special function registers
remain intact during this mode. The idle
mode can be terminated either by any
enabled interrupt (at which time the process
is picked up at the interrupt service routine
and continued), or by a hardware reset which
starts the processor in the same manner as a
power-on reset.

Power-Down Mode

In the power-down mode, the oscillator is
stopped and the instruction to invoke

power-down is the last instruction executed.
Only the contents of the on-chip RAM are
preserved. A hardware reset is the only way
to terminate the power-down mode. The
control bits for the reduced power modes are
in the special function register PCON. Table 2
shows the state of the I/O ports during low
current operating modes.

C SERIAL

COMMUNICATION--SIO1

The I

C serial port is identical to the I

serial port on the 8XC552. The operation of
this subsystem is described in detail in the
8XC552 section of this manual.

Note that in both the 8XC652/4 and the
8XC552 the I

C pins are alternate functions

to port pins P1.6 and P1.7. Because of this,
P1.6 and P1.7 on these parts do not have a
pull-up structure as found on the 80C51.
Therefore P1.6 and P1.7 have open drain
outputs on the 8XC652/4.

Table 2. External Pin Status During Idle and Power-Down Mode

MODE

PROGRAM

MEMORY

ALE

PSEN

PORT 0

PORT 1

PORT 2

PORT 3

Idle

Internal

Data

Idle

External

Float

Data

Address

Data

Power-down

Internal

Data

Power-down

External

Float

Data

Serial Control Register (S1CON) See Table 3

S1CON (D8H)

CR2

ENS1

STA

STO

CR1

CR0

Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation.

Table 3. Serial Clock Rates

BIT FREQUENCY (kHz) AT f

OSC

CR2

CR1

CR0

6 MHZ

12 MHz

16 MHz

20 MHz

OSC

DIVIDED BY

62.5

256

224

31.25

62.5

83.3

104

192

100

125

160

6.25

12.5

960

100

133

166

120

100

200

267

334

0.25 < 62.5

0 to 255

0.5 < 62.5

0 to 254

0.65 < 55.6

0 to 253

0.81 < 69.4

0 to 253

(256 (reload value Timer 1))

(Reload value range: 0 254 in mode 2)

NOTE:
1. These frequencies exceed the upper limit of 100kHz of the I

C-bus specification and cannot be used in an I

C-bus application.

Philips Semiconductors

Product specification

87C652/87C654

80C51 8-bit microcontroller
8K/16K, 256 OTP, I

1999 Jul 23

ABSOLUTE MAXIMUM RATINGS

1, 2, 3

PARAMETER

RATING

UNIT

Storage temperature range

65 to +150

Voltage on EA/V

to V

0.5 to + 13

Voltage on any other pin to V

0.5 to + 6.5

Input, output current on any single pin

Power dissipation (based on package heat transfer
limitations, not device power consumption)

NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at
these or any conditions other than those described in the AC and DC Electrical
Characteristics section of this specification is not implied.

2. This product includes circuitry specifically designed for the protection of its internal devices

from the damaging effects of excessive static charge. Nonetheless, it is suggested that
conventional precautions be taken to avoid applying greater than the rated maxima.

3. Parameters are valid over operating temperature range unless otherwise specified. All

voltages are with respect to V

unless otherwise noted.

DEVICE SPECIFICATIONS

SUPPLY VOLTAGE

(V)

FREQUENCY

(MHz)

TEMPERATURE

RANGE

TYPE

MIN.

MAX.

MIN.

MAX.

(

S87C652-4 and

S87C654-4

4.5

5.5

3.5

0 to +70

S87C652-5 and

S87C654-5

4.5

5.5

3.5

40 to +85

S87C6547

4.5

5.5

3.5

0 to +70

Philips Semiconductors

Product specification

87C652/87C654

80C51 8-bit microcontroller
8K/16K, 256 OTP, I

1999 Jul 23

DC ELECTRICAL CHARACTERISTICS

= 0 V

TEST

LIMITS

SYMBOL

PARAMETER

PART TYPE

CONDITIONS

MIN.

MAX.

UNIT

Input low voltage,
except EA, P1.6/SCL, P1.7/SDA

0 to +70

40 to +85

0.5
0.5

0.2V

0.1

0.2V

0.15

V
V

IL1

Input low voltage to EA

0 to +70

40 to +85

0.5
0.5

0.2V

0.3

0.2V

0.35

V
V

IL2

Input low voltage to P1.6/SCL, P1.7/SDA

0.5

0.3V

Input high voltage,
except XTAL1, RST, P1.6/SCL, P1.7/SDA

0 to +70

40 to +85

0.2V

+0.9

0.2V

+1.0

+0.5

V
V

IH1

Input high voltage, XTAL1, RST

0 to +70

40 to +85

0.7V

+0.1

+0.5

V
V

IH2

Input high voltage, P1.6/SCL, P1.7/SDA

0.7V

6.0

Output low voltage, ports 1, 2, 3,
except P1.6/SCL, P1.7/SDA

= 1.6mA

2, 3

0.45

OL1

Output low voltage, port 0, ALE, PSEN

= 3.2mA

2, 3

0.45

OL2

Output low voltage, P1.6/SCL, P1.7/SDA

= 3.0mA

0.4

Output high voltage, ports 1, 2, 3

0 to +70

40 to +85

= 60

= 25

2.4

0.75V

V
V

OH1

Output high voltage; port 0 in external bus mode,
ALE, PSEN, RST

0 to +70

40 to +85

= 400

= 150

2.4

0.75V

V
V

Logical 0 input current, ports 1, 2, 3, 4,
except P1.6/SCL, P1.7/SDA

0 to +70

40 to +85

= 0.45V

50
75

Logical 1-to-0 transition current, ports 1, 2, 3,
except P1.6/SCL, P1.7/SDA

0 to +70

40 to +85

See note 5

650
750

Input leakage current, port 0

0.45V < V

< V

Input leakage current, P1.6/SCL, P1.7/SDA

0V < V

< 6.0V

0V < V

< 6.0V

Power supply current:

See note 6

=6.0V

Active mode @ 16 MHz

Idle mode @ 16 MHz

Power down mode

9, 10

0 to +70

Power down mode

9, 10

40 to +85

135

RST

Internal reset pull-down resistor

150

Pin capacitance

Freq.=1 MHz

NOTES:
1. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I

C specification, so an input voltage below 0.3V

will be recognized as a

logic 0 while an input voltage above 0.7V

will be recognized as a logic 1.

2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V

s of ALE and ports 1 and 3. The noise is due

to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I

can exceed these conditions provided that no

single output sinks more than 5 mA and no more than two outputs exceed the test conditions.

3. Under steady state (non-transient) conditions, I

must be externally limited as follows: Maximum I

= 10 mA per port pin; Maximum

= 26 mA total for Port 0; Maximum I

= 15 mA total for Ports 1, 2, and 3; Maximum I

= 71 mA total for all output pins. If I

exceeds

the test conditions, V

may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.

4. Capacitive loading on ports 0 and 2 may cause the V

on ALE and PSEN to momentarily fall below the 0.9V

specification when the

address bits are stabilizing.

5. Pins of ports 1 , 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its

maximum value when V

is approximately 2 V.

6. See Figures 9 through 11 for I

test conditions.

7. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t

= t

= 10ns;

= V

+ 0.5 V; V

= V

0.5 V; XTAL2 not connected; EA = RST = Port 0 = P1.6 = P1.7 = V

; f

CLK

= 16 MHz. See Figure 9.

8. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t

= t

= 10 ns; V

= V

+ 0.5 V;

= V

0.5 V; XTAL2 not connected; Port 0 = P1.6 = P1.7 = V

; EA = RST = V

; f

CLK

= 16 MHz. See Figure 10.

9. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = P1.6 = P1.7 = V

;

EA = RST = V

. See Figure 11.

10. 2V

max.

Philips Semiconductors

Product specification

87C652/87C654

80C51 8-bit microcontroller
8K/16K, 256 OTP, I

1999 Jul 23

AC ELECTRICAL CHARACTERISTICS

1, 2

16 MHz CLOCK

VARIABLE CLOCK

SYMBOL

FIGURE

PARAMETER

MIN

MAX

MIN

MAX

UNIT

1/t

CLCL

Oscillator frequency Speed Versions
87C654

4, 5

3.5

MHz

LHLL

ALE pulse width

CLCL

AVLL

Address valid to ALE low

CLCL

LLAX

Address hold after ALE low

CLCL

LLIV

ALE low to valid instruction in

150

CLCL

100

LLPL

ALE low to PSEN low

CLCL

PLPH

PSEN pulse width

143

CLCL

PLIV

PSEN low to valid instruction in

CLCL

105

PXIX

Input instruction hold after PSEN

PXIZ

Input instruction float after PSEN

CLCL

AVIV

Address to valid instruction in

208

CLCL

105

PLAZ

PSEN low to address float

Data Memory

AVLL

3, 4

Address valid to ALE low

CLCL

RLRH

3, 4

RD pulse width

275

CLCL

100

WLWH

3, 4

WR pulse width

275

CLCL

100

RLDV

3, 4

RD low to valid data in

148

CLCL

165

RHDX

3, 4

Data hold after RD

RHDZ

3, 4

Data float after RD

CLCL

LLDV

3, 4

ALE low to valid data in

350

CLCL

150

AVDV

3, 4

Address to valid data in

398

CLCL

165

LLWL

3, 4

ALE low to RD or WR low

138

238

CLCL

+50

AVWL

3, 4

Address valid to WR low or RD low

120

CLCL

130

QVWX

3, 4

Data valid to WR transition

CLCL

3, 4

Data setup time before WR

288

CLCL

150

WHQX

3, 4

Data hold after WR

CLCL

RLAZ

3, 4

RD low to address float

WHLH

3, 4

RD or WR high to ALE high

103

CLCL

+40

Shift Register

XLXL

Serial port clock cycle time

0.75

12t

CLCL

QVXH

Output data setup to clock rising edge

492

10t

CLCL

133

XHQX

Output data hold after clock rising edge

CLCL

117

XHDX

Input data hold after clock rising edge

XHDV

Clock rising edge to input data valid

492

10t

CLCL

133

External Clock

CHCX

High time

CLCL

LOW

CLCX

Low time

CLCL

HIGH

CLCH

Rise time

CHCL

Fall time

NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
3. These values are characterized but not 100% production tested.

Philips Semiconductors

Product specification

87C652/87C654

80C51 8-bit microcontroller
8K/16K, 256 OTP, I

1999 Jul 23

AC ELECTRICAL CHARACTERISTICS

1, 2

20 MHz CLOCK

VARIABLE CLOCK

SYMBOL

FIGURE

PARAMETER

MIN

MAX

MIN

MAX

UNIT

1/t

CLCL

Oscillator frequency: Speed Versions
87C654

7, 8

3.5

MHz

LHLL

ALE pulse width

CLCL

AVLL

Address valid to ALE low

CLCL

LLAX

Address hold after ALE low

CLCL

LLIV

ALE low to valid instruction in

135

CLCL

LLPL

ALE low to PSEN low

CLCL

PLPH

PSEN pulse width

105

CLCL

PLIV

PSEN low to valid instruction in

CLCL

PXIX

Input instruction hold after PSEN

PXIZ

Input instruction float after PSEN

CLCL

AVIV

Address to valid instruction in

170

CLCL

PLAZ

PSEN low to address float

Data Memory

AVLL

3, 4

Address valid to ALE low

CLCL

RLRH

3, 4

RD pulse width

200

CLCL

100

WLWH

3, 4

WR pulse width

200

CLCL

100

RLDV

3, 4

RD low to valid data in

160

CLCL

RHDX

3, 4

Data hold after RD

RHDZ

3, 4

Data float after RD

CLCL

LLDV

3, 4

ALE low to valid data in

250

CLCL

150

AVDV

3, 4

Address to valid data in

285

CLCL

165

LLWL

3, 4

ALE low to RD or WR low

100

200

CLCL

+50

AVWL

3, 4

Address valid to WR low or RD low

125

CLCL

QVWX

3, 4

Data valid to WR transition

CLCL

3, 4

Data setup time before WR

220

CLCL

130

WHQX

3, 4

Data hold after WR

CLCL

RLAZ

3, 4

RD low to address float

WHLH

3, 4

RD or WR high to ALE high

CLCL

+25

Shift Register

XLXL

Serial port clock cycle time

0.6

12t

CLCL

QVXH

Output data setup to clock rising edge

367

10t

CLCL

133

XHQX

Output data hold after clock rising edge

CLCL

XHDX

Input data hold after clock rising edge

XHDV

Clock rising edge to input data valid

367

10t

CLCL

133

External Clock

CHCX

High time

CLCL

LOW

CLCX

Low time

CLCL

HIGH

CLCH

Rise time

CHCL

Fall time

Philips Semiconductors

Product specification

87C652/87C654

80C51 8-bit microcontroller
8K/16K, 256 OTP, I

1999 Jul 23

AC ELECTRICAL CHARACTERISTICS I

C INTERFACE

SYMBOL

PARAMETER

INPUT

OUTPUT

SCL TIMING CHARACTERISTICS

; STA

START condition hold time

14 t

CLCL

> 4.0

LOW

SCL LOW time

16 t

CLCL

> 4.7

HIGH

SCL HIGH time

14 t

CLCL

> 4.0

SCL rise time

SCL fall time

0.3

< 0.3

SDA TIMING CHARACTERISTICS

; DAT1

Data set-up time

250 ns

> 20 t

CLCL

; DAT2

SDA set-up time (before rep. START cond.)

250 ns

> 1

; DAT3

SDA set-up time (before STOP cond.)

250 ns

> 8 t

CLCL

; DAT

Data hold time

0 ns

> 8 t

CLCL

; STA

Repeated START set-up time

14 t

CLCL

> 4.7

; STO

STOP condition set-up time

14 t

CLCL

> 4.0

BUF

Bus free time

14 t

CLCL

> 4.7

SDA rise time

SDA fall time

0.3

< 0.3

NOTES:
1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1

3. Spikes on the SDA and SCL lines with a duration of less than 3 t

CLCL

will be filtered out. Maximum capacitance on bus-lines SDA and

SCL = 400 pF.

4. t

CLCL

= 1/f

OSC

= one oscillator clock period at pin XTAL1. For 62 ns < t

CLCL

< 285 ns (16 MHz) > f

OSC

> 3.5 MHz) the SI01 interface meets

the I

C-bus specification for bit-rates up to 100 kbit/s.

TIMING SIO1 (I

C) INTERFACE

tRD

tSU;STA

tBUF

tSU;STO

0.7 VCC

0.3 VCC

0.7 VCC

0.3 VCC

tFD

tRC

tFC

tHIGH

tLOW

tHD;STA

tSU;DAT1

tHD;DAT

tSU;DAT2

tSU;DAT3

START condition

repeated START condition

SDA

(INPUT/OUTPUT)

SCL

(INPUT/OUTPUT)

STOP condition

START or repeated START condition

SU00107A

Philips Semiconductors

Product specification

87C652/87C654

80C51 8-bit microcontroller
8K/16K, 256 OTP, I

1999 Jul 23

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has five characters. The
first character is always `t' (= time). The other
characters, depending on their positions,
indicate the name of a signal or the logical
status of that signal. The designations are:
A Address
C Clock
D Input data
H Logic level high
I Instruction (program memory contents)
L Logic level low, or ALE
P PSEN

Q Output data
R RD signal
t Time
V Valid
W WR signal
X No longer a valid logic level
Z Float
Examples: t

AVLL

= Time for address valid

to ALE low.

LLPL

= Time for ALE low

to PSEN low.

PXIZ

ALE

PSEN

PORT 0

PORT 2

A0A15

A8A15

A0A7

AVLL

PXIX

LLAX

INSTR IN

LHLL

PLPH

LLIV

PLAZ

LLPL

AVIV

SU00006

PLIV

Figure 1. External Program Memory Read Cycle

LLAX

ALE

PSEN

PORT 0

PORT 2

A0A7

FROM RI OR DPL

DATA IN

A0A7 FROM PCL

INSTR IN

P2.0P2.7 OR A8A15 FROM DPH

A8A15 FROM PCH

WHLH

LLDV

LLWL

RLRH

RLAZ

AVLL

RHDX

RHDZ

AVWL

AVDV

RLDV

SU00177

Figure 2. External Data Memory Read Cycle

Philips Semiconductors

Product specification

87C652/87C654

80C51 8-bit microcontroller
8K/16K, 256 OTP, I

1999 Jul 23

VCC0.5

0.45V

0.2VCC+0.9

0.2VCC0.1

NOTE:
AC inputs during testing are driven at V

0.5 for a logic `1' and 0.45V for a logic `0'.

Timing measurements are made at V

min for a logic `1' and V

max for a logic `0'.

SU00010

Figure 6. AC Testing Input/Output

VLOAD

VLOAD+0.1V

VLOAD0.1V

VOH0.1V

VOL+0.1V

NOTE:

TIMING

REFERENCE

POINTS

For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs,
and begins to float when a 100mV change from the loaded V

level occurs. I

20mA.

SU00011

Figure 7. Float Waveform

VCC

RST

XTAL1

XTAL2

VSS

VCC

ICC

(NC)

CLOCK SIGNAL

P1.6

P1.7

*
*

87C652/4

SU00272

Figure 8. I

Test Condition, Active Mode

All other pins are disconnected

NOTE:
*

Ports 1.6 and 1.7 should be connected to V

through resistors of sufficiently high value such that the sink current into these pins does not

exceed the I

OL1

specification.

Philips Semiconductors

Product specification

87C652/87C654

80C51 8-bit microcontroller
8K/16K, 256 OTP, I

1999 Jul 23

EPROM CHARACTERISTICS

The 87C652/87C654 is programmed by using
a modified Quick-Pulse Programming

algorithm. It differs from older methods in the
value used for V

(programming supply

voltage) and in the width and number of the
ALE/PROG pulses.

The 87C652/87C654 contains two signature
bytes that can be read and used by an
EPROM programming system to identify the
device. The signature bytes identify the device
as an 87C652/87C654 manufactured by
Philips Components.

Table 4 shows the logic levels for reading the
signature byte, and for programming the
program memory, the encryption table, and
the lock bits. The circuit configuration and
waveforms for quick-pulse programming are
shown in Figures 12 and 13. Figure 14 shows
the circuit configuration for normal program
memory verification.

Quick-Pulse Programming

The setup for microcontroller quick-pulse
programming is shown in Figure 12. Note
that the 87C652/87C654 is running with a
4 to 6 MHz oscillator. The reason the
oscillator needs to be running is that the
device is executing internal address and
program data transfers.

The address of the EPROM location to be
programmed is applied to ports 1 and 2, as

shown in Figure 12. The code byte to be
programmed into that location is applied to
port 0. RST, PSEN and pins of ports 2 and 3
specified in Table 4 are held at the `Program
Code Data' levels indicated in Table 4. The
ALE/PROG is pulsed low 25 times as shown
in Figure 13.

To program the encryption table, repeat the 25
pulse programming sequence for addresses 0
through 1FH, using the `Pgm Encryption Table'
levels. Do not forget that after the encryption
table is programmed, verification cycles will
produce only encrypted data.

To program the lock bits, repeat the 25 pulse
programming sequence using the `Pgm Lock
Bit' levels. After one lock bit is programmed,
further programming of the code memory and
encryption table is disabled. However, the
other lock bit can still be programmed.

Note that the EA/V

pin must not be allowed

to go above the maximum specified V

level

for any amount of time. Even a narrow glitch
above that voltage can cause permanent
damage to the device. The V

source

should be well regulated and free of glitches
and overshoot.

Program Verification
If lock bit 2 has not been programmed, the
on-chip program memory can be read out for

program verification. The address of the
program memory locations to be read is
applied to ports 1 and 2 as shown in
Figure 14. The other pins are held at the
`Verify Code Data' levels indicated in Table 4.
The contents of the address location will be
emitted on port 0. External pull-ups are
required on port 0 for this operation.

If the encryption table has been programmed,
the data presented at port 0 will be the
exclusive NOR of the program byte with one
of the encryption bytes. The user will have to
know the encryption table contents in order to
correctly decode the verification data. The
encryption table itself cannot be read out.

Reading the Signature Bytes
The signature bytes are read by the same
procedure as a normal verification of
locations 030H and 031H, except that P3.6
and P3.7 need to be pulled to a logic low. The
values are:
(030H) = 15H indicates manufactured by

Philips

(031H) = 99H

Program/Verify Algorithms

Any algorithm in agreement with the
conditions listed in Table 4, and which
satisfies the timing specifications, is suitable.

Table 4. EPROM Programming Modes

MODE

RST

PSEN

ALE/PROG

EA/V

P2.7

P2.6

P3.7

P3.6

Read signature

Program code data

Verify code data

Pgm encryption table

Pgm lock bit 1

Pgm lock bit 2

NOTES:
1. `0' = Valid low for that pin, `1' = valid high for that pin.
2. V

= 12.75 V

0.25 V.

3. V

= 5 V

10% during programming and verification.

ALE/PROG receives 25 programming pulses while V

is held at 12.75 V. Each programming pulse is low for 100

s (

s) and high for a

minimum of 10

Trademark phrase of Intel Corporation.

Philips Semiconductors

Product specification

87C652/87C654

80C51 8-bit microcontroller
8K/16K, 256 OTP, I

1999 Jul 23

EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS

amb

= 21

C to +27

C, V

= 5V

10%, V

= 0V (See Figure 15)

SYMBOL

PARAMETER

MIN

MAX

UNIT

Programming supply voltage

12.5

13.0

Programming supply current

1/t

CLCL

Oscillator frequency

MHz

AVGL

Address setup to PROG low

48t

CLCL

GHAX

Address hold after PROG

48t

CLCL

DVGL

Data setup to PROG low

48t

CLCL

GHDX

Data hold after PROG

48t

CLCL

EHSH

P2.7 (ENABLE) high to V

48t

CLCL

SHGL

setup to PROG low

GHSL

hold after PROG

GLGH

PROG width

110

AVQV

Address to data valid

48t

CLCL

ELQZ

ENABLE low to data valid

48t

CLCL

EHQZ

Data float after ENABLE

48t

CLCL

GHGL

PROG high to PROG low

PROGRAMMING

VERIFICATION

ADDRESS

DATA IN

DATA OUT

LOGIC 1

LOGIC 0

AVQV

EHQZ

ELQV

EHSH

SHGL

GHSL

GLGH

GHGL

AVGL

GHAX

DVGL

GHDX

P1.0P1.7
P2.0P2.3

PORT 0

ALE/PROG

EA/V

P2.7
ENABLE

SU00270

FOR PROGRAMMING VERIFICATION SEE FIGURE 12.
FOR VERIFICATION CONDITIONS SEE FIGURE 14.

Figure 15. EPROM Programming and Verification

Purchase of Philips I

C components conveys a license under the Philips' I

C patent

to use the components in the I

C system provided the system conforms to the

C specifications defined by Philips. This specification can be ordered using the

code 9398 393 40011.

Philips Semiconductors

Product specification

87C652/87C654

80C51 8-bit microcontroller
8K/16K, 256 OTP, I

1999 Jul 23

Definitions

Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381

Date of release: 07-99

Document order number:

9397-750-06607

Philips

Semiconductors

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

[1]

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

Data sheet status

[1]

Please consult the most recently issued datasheet before initiating or completing a design.

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