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Электронный компонент: SA5200D

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Philips Semiconductors
SA5200
RF dual gain-stage
Product Specification
Replaces data of Oct 10 1991
1997 Nov 07
INTEGRATED CIRCUITS
IN
2
GND
2
OUT
2
V
CC
ENABLE
IN
1
GND
1
OUT
1
AMP2
AMP1
4
3
2
1
8
7
6
5
IC17 Data Handbook
Philips Semiconductors
Product specification
SA5200
RF dual gain-stage
52
1997 Nov 07
853-1578 18662
DESCRIPTION
The SA5200 is a dual amplifier with DC to 1200MHz response. Low
noise (NF = 3.6dB) makes this part ideal for RF front-ends, and a
simple power-down mode saves current for battery operated
equipment. Inputs and outputs are matched to 50
.
The enable pin allows the designer the ability to turn the amplifiers
on or off, allowing the part to act as an amplifier as well as an
attenuator. This is very useful for front-end buffering in receiver
applications.
FEATURES
Dual amplifiers
DC - 1200MHz operation
Low DC power consumption (4.2mA per amplifier @ V
CC
= 5V)
Power-Down Mode (I
CC
= 95
A typical)
3.6dB noise figure at 900MHz
Unconditionally stable
Fully ESD protected
Low cost
PIN CONFIGURATION
VC
C
OUT2
GND2
IN2
OUT1
IN1
1
2
3
4
5
6
7
8
GND1
ENABLE
D Package
SR00166
Figure 1. Pin Configuration
Supply voltage 4-9V
Gain S
21
= 7dB at f = 1GHz
Input and output match S
11
, S
22
typically <14dB
APPLICATIONS
Cellular radios
RF IF strips
Portable equipment
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
DWG #
8-Pin Plastic Small Outline (Surfacemount)
40-+85
C
SA5200D
SOT96-1
BLOCK DIAGRAM
IN2
GND2
OUT2
VCC
ENABLE
IN1
GND1
OUT1
AMP2
AMP1
4
3
2
1
8
7
6
5
SR00167
Figure 2. Block Diagram
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
RATING
UNITS
V
CC
Supply voltage
4.0 to 9.0
V
T
A
Operating ambient temperature range
SA Grade
-40 to +85
C
T
J
Operating junction temperature
SA Grade
-40 to +105
C
Philips Semiconductors
Product specification
SA5200
RF dual gain-stage
1997 Nov 07
53
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNITS
V
CC
Supply voltage
1
-0.5 to +9
V
P
D
Power dissipation, T
A
= 25
C (still air)
2
8-Pin Plastic SO
780
mW
T
JMAX
Maximum operating junction temperature
150
C
P
MAX
Maximum power input/output
+20
dBm
T
STG
Storage temperature range
65 to +150
C
NOTE:
1. Transients exceeding 10.5V on V
CC
pin may damage product.
2. Maximum dissipation is determined by the operating ambient temperature and the thermal resistance,
JA
:
8-Pin SO:
JA
= 158
C/W
DC ELECTRICAL CHARACTERISTICS
V
CC
= +5V, T
A
= 25
C; unless otherwise stated.
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNITS
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
Supply voltage
4
5.0
9.0
V
V
CC
= 5V, ENABLE = High
6.4
8.4
10.4
mA
I
CC
Total supply current
V
CC
= 5V, ENABLE = Low
95
255
A
V
CC
= 9V, ENABLE = High
17.8
22.2
mA
V
CC
= 9V, ENABLE = Low
320
960
A
V
T
TTL/CMOS logic threshold voltage
1
1.25
V
V
IH
Logic 1 level
Power-up mode
2.0
V
CC
V
V
IL
Logic 0 level
Power-down mode
-0.3
0.8
V
I
IL
Enable input current
Enable = 0.4V
-1
0
1
A
I
IH
Enable input current
Enable = 2.4V
-1
0
1
A
V
IDC,ODC
Input and output DC levels
0.6
0.83
1.0
V
NOTE:
1. The ENABLE input must be connected to a valid logic level for proper operation of the SA5200.
AC ELECTRICAL CHARACTERISTICS
1
V
CC
= +5V, T
A
= 25
C, either amplifier, enable = 5V; unless otherwise stated.
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNITS
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
S21
Insertion gain
f = 100MHz
9.2
11
13.2
dB
S21
Insertion gain
f = 900MHz
5.2
7.5
dB
S22
Output return loss
f = 900MHz
14.3
dB
S12
Reverse isolation
f = 900MHz
17.9
dB
S11
Input return loss
f = 900MHz
16.5
dB
P-1
Output 1dB compression point
f = 900MHz
4.3
dBm
NF
Noise figure in 50
f = 900MHz
3.6
dB
IP
2
Input second-order intercept point
f = 900MHz
+4.3
dBm
IP
3
Input third-order intercept point
f = 900MHz
1.8
dBm
ISOL
Amplifier-to-amplifier isolation
2
f = 900MHz
25
dB
P
OUT
Saturated output power
f = 900MHz
1.7
dBm
S21
Insertion gain when disabled
f = 100MHz
13
dB
S21
Insertion gain when disabled
f = 900MHz
13.5
dB
NOTE:
1. All measurements include the effects of the SA5200 Evaluation Board (see Figure 4). Measurement system impedance is 50
.
2. Input applied to one amplifier, output taken at the other output. All ports terminated into 50
.
Philips Semiconductors
Product specification
SA5200
RF dual gain-stage
1997 Nov 07
54
APPLICATIONS
SA5200 is a user-friendly, wide-band, unconditionally stable, low
power dual gain amplifier circuit. There are several advantages to
using the SA5200 as a high frequency gain block instead of a
discrete implementation. First is the simplicity of use. The SA5200
does not need any external biasing components. Due to the higher
level of integration and small footprint (SO8) package it occupies
less space on the printed circuit board and reduces the
manufacturing cost of the system. Also the higher level of
integration improves the reliability of the amplifier over a discrete
implementation with several components. The power down mode in
the SA5200 helps reduce power consumption in applications where
the amplifiers can be disabled. And last but not the least is the
impedance matching at inputs and outputs. Only those who have
toiled through discrete transistor implementations for 50
input and
output impedance matching can truly appreciate the elegance and
simplicity of the SA5200 input and output impedance matching to
50
.
A simplified equivalent schematic is shown in 3. Each amplifier is
composed of an NPN transistor with an Ft of 13GHz in a classical
series-shunt feedback configuration. The two wideband amplifiers
are biased from the same bias generator. In normal operation each
amplifier consumes about 4mA of quiescent current (at V
CC
= 5V).
In the disable mode the device consumes about 90
A of current,
most of it is in the TTL enable buffer and the bias generator. The
input impedance of the amplifiers is 50
. The amplifiers have
typical gain of 11dB at 100MHz and 7dB of gain at 1.2GHz.
It can be seen from 3 that any inductance between Pin 7, 3 and the
ground plane will reduce the gain of the amplifiers at higher
frequencies. Thus proper grounding of Pins 7 and 3 is essential for
maximum gain and increased frequency response. 4 shows the
printed circuit board layout and the component placement for the
SA5200 evaluation board. The AC coupling capacitors should be
selected such that at they are shorts at the desired frequency of
operation. Since most low-cost large value surface mount
capacitors cease to be simply capacitors in the UHF range and
exhibit an inductive behavior, it is recommended that high frequency
chip capacitors be utilized in the circuit. A good power supply
bypass is also essential for the performance of the amplifier and
should be as close to the device as practical.
5 shows the typical frequency response of the two channels of
SA5200. The low frequency gain is about 11dB at 100MHz and
slowly drops off to 10dB at 500MHz. The gain is about 8dB at
900MHz and 7dB at 1.2 GHz which is typical of SA5200 with a good
printed circuit board layout. It can also be seen that both channels
have a very well matched frequency response and matched gain to
within 0.1dB at 100MHz and 0.2dB at 900MHz.
SA5200 finds applications in many areas of RF communications. It
is an ideal gain block for high performance, low cost, low power RF
communications transceivers. A typical radio transceiver front-end
is shown in 6. This could be the front-end of a cellular phone, a
VHF/ UHF hand-held transceiver, UHF cordless telephone or a
spread spectrum system. The SA5200 can be used in the receiver
path of most systems as an LNA and pre-amplifier. The bandpass
filter between the two amplifiers also minimize the noise into the first
mixer. In the transmitter path, SA5200 can be used as a buffer to
the VCO and isolate the VCO from any load variations due to the
power level changes in the power amplifier. This improves the
stability of the VCOs. The SA5200 can also be used as a pre-driver
to the power amplifier modules.
The two amplifiers in SA5200 can be easily cascaded to have a
13dB gain block at 900MHz. At 100MHz the gain will be 22dB and a
noise figure of about 5.5dB. The SA5200 can be operated at a
higher voltage up to 9V for much improved 1dB output compression
point and higher 3rd order intercept point.
Several stages of SA5200 can also be cascaded and be used as an
IF amplifier strip for DBS/TV/GPS receivers. 7 shows a 60dB gain
IF strip at 180MHz. The noise figure for the cascaded amplifier
chain is given by equation 1.
NF (total) = NF1 + NF2/G1 + NF3/G1*G2 + NF4/G1*G2*G3 + ...
(Equation. 1)
NOTE: The noise figure and gain should not be in dB in the above
equation.
Since the noise figure for each stage is about 3.6dB and the gain is
about 11dB, the noise figure for the 60dB gain IF strip will be about
6.4dB.
In applications where a single amplifier is required with a 7.5dB gain
at 900MHz and current consumption is of paramount importance
(battery powered receivers), the amplifier A1 can be used and
amplifier A2 can be disabled by leaving GND2 (Pin 3) unconnected.
This will reduce the total current consumption for the IC to a meager
4mA.
The ENABLE pin is useful for Time-Division-Duplex systems where
the receiver can be disabled for a period of time. In this case the
overall system supply current will be decreased by 8mA.
The ENABLE pin can also be used to improve the system dynamic
range. For input levels that are extremely high, the SA5200 can be
disabled. In this case the input signal is attenuated by 13dB. This
prevents the system from being overloaded as well as improves the
system's overall dynamic range. In the disabled condition the
SA5200 IP
3
increases to nearly +20dBm.
Philips Semiconductors
Product specification
SA5200
RF dual gain-stage
1997 Nov 07
55
BIAS
GENERATOR
PIN 2
OUT2
PIN 3
GND2
AMP2
PIN 4
IN2
RF
RC
RE
PIN 8
OUT1
PIN 7
GND1
AMP1
PIN 6
IN1
RF
RC
RE
PIN 5
ENABLE
GND1
PIN 1
VCC
SR00168
Figure 3. Simplified Equivalent Schematic of SA5200
SR00169
Figure 4. Printed Circuit Board Layout of the SA5200 Evaluation Board
Philips Semiconductors
Product specification
SA5200
RF dual gain-stage
1997 Nov 07
56
SR00170
Figure 5. Typical Frequency Response of SA5200 in a 50
System
ENABLE
NE5200
ANTENNA
IF OUT
Rx
LO
NE602A
ENABLE
NE5200
Tx
VCO
MODULATION
FILTER
FILTER
POWER
AMP
DUPLEX
FILTER
SR00171
Figure 6. Typical Radio Transceiver Front-End
Philips Semiconductors
Product specification
SA5200
RF dual gain-stage
1997 Nov 07
57
NE5200
IF OUT
NE5200
NE5200
IF IN
IF OUT
SR00172
Figure 7. 60dB IF Gain Block for 100-300MHz IF for GPS/DBS Systems
20
VCC (V)
I (mA) CC
4
5
6
7
8
9
+85
C
18
16
14
12
10
8
6
4
40
C
SR00173
Figure 8. Supply Current vs Supply Voltage and Temperature
I (
A)
CC
4
5
6
7
8
9
VCC (V)
500
450
400
350
300
250
200
150
100
50
0
+85
C
40
C
+25
C
SR00175
Figure 9. Disabled Supply Current vs V
CC
and Temperature
-5
-10
-15
-20
-25
10
100
1000
2000
4V
5V
6V
7V
9V
TA = +25
C
FREQUENCY (MHz)
S (dB)
11
SR00174
Figure 10. Input Match vs Frequency and V
CC
-8
VCC = 5V
S (dB)
11
-10
-12
-14
-16
-18
-20
10
100
1000
2000
FREQUENCY (MHz)
+85
C
+25
C
-40
C
SR00176
Figure 11. Input Match vs Frequency and Temperature
Philips Semiconductors
Product specification
SA5200
RF dual gain-stage
1997 Nov 07
58
14
S (dB)
21
10
100
1000
2000
FREQUENCY (MHz)
12
10
8
6
4
2
0
9V
7V
6V
5V
4V
TA = +25
C
SR00177
Figure 12. Insertion Gain vs Frequency and V
CC
800
9V
850
900
950
1000
1050
1100
1150
1200
10
9.5
9
8.5
8
7.5
7
6.5
6
7V
6V
5V
4V
TA = +25
C
FREQUENCY (MHz)
S (dB)
21
SR00178
Figure 13. Insertion Gain vs Frequency and V
CC
-- Expanded Detail --
S (dB)
21
10
100
1000
2000
FREQUENCY (MHz)
12
10
8
6
4
2
0
-40
C
+25
C
+85
C
VCC = 5V
SR00180
Figure 14. Insertion Gain vs Frequency and Temperature
S (dB)
21
800
FREQUENCY (MHz)
10
9.5
9
8.5
8
7.5
7
6.5
6
5.5
5
850
900
950
1000
1050
1100
1150
1200
-40
C
+25
C
+85
C
VCC = 5V
SR00179
Figure 15. Insertion Gain vs Frequency and Temperature
Expanded Detail
Philips Semiconductors
Product specification
SA5200
RF dual gain-stage
1997 Nov 07
59
S (dB)
21
10
100
1000
2000
FREQUENCY (MHz)
12
11
10
9
8
7
6
5
4
3
2
CH1
CH2
VCC = 5V
TA = +25
C
SR00181
Figure 16. Insertion Gain Matching
(CH1 vs CH2) vs Frequency
S (dB)
12
10
100
1000
2000
FREQUENCY (MHz)
-12
VCC = 5V
-18
-22
+85
C
-40
C
-20
-14
-16
-10
+25
C
SR00183
Figure 17. Reverse Insertion Gain vs Frequency and
Temperature
9V
-10
7V
6V
5V
4V
FREQUENCY (MHz)
S (dB)
22
-15
-20
-25
-30
10
100
1000
2000
TA = +25
C
SR00182
Figure 18. Output Match vs Frequency and V
CC
S (dB)
22
10
100
1000
2000
FREQUENCY (MHz)
-12
VCC = 5V
-18
-22
+85
C
-40
C
+25
C
-10
-16
-14
-20
SR00184
Figure 19. Output Match vs Frequency and Temperature
Philips Semiconductors
Product specification
SA5200
RF dual gain-stage
1997 Nov 07
510
S (dB)
10
100
1000
2000
FREQUENCY (MHz)
-0
VCC = 5V
-5
-10
-15
-20
-25
S11
S22
S12
S21
TA = +25
C
Figure 20. S-parameters vs Frequency for Disabled Amplifier
S (dB)
21
10
100
1000
2000
FREQUENCY (MHz)
-10
CH1
CH2
VCC = 5V
TA = +25
C
-15
-20
-25
Figure 21. Insertion Gain Matching Disabled (CH1 vs CH2) vs
Frequency
S (dB)
21
10
100
1000
2000
FREQUENCY (MHz)
0
ENABLED
VCC = 5V
TA = +25
C
-20
-40
-60
-80
-100
DISABLED
Figure 22. CH1 Input to CH2 Output Isolation vs Frequency
NF (dB)
10
100
1000
2000
FREQUENCY (MHz)
4
TA = +25
C
4V
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
9V
5V
6V & 7V
Figure 23. Noise Figure vs Frequency and V
CC
in a 50
System
Philips Semiconductors
Product specification
SA5200
RF dual gain-stage
1997 Nov 07
511
9V
5
7V
6V
5V
4V
FREQUENCY (MHz)
P
(dBm) -1
10
100
1000
2000
TA = +25
C
0
-5
-10
SR00185
Figure 24. 1dB Output Compression Point vs Frequency and
V
CC
9V
5
7V
6V
5V
4V
FREQUENCY (MHz)
P
(dBm) SA
T
10
100
1000
2000
TA = +25
C
0
-5
-10
SR00187
Figure 25. Saturated Output Power vs Frequency and V
CC
16
VCC (V)
IP
(dBm) 3
4
TA = +25
C
14
12
10
8
6
4
2
0
5
6
7
8
9
DISABLED
900MHz
500MHz
100MHz
SR00186
Figure 26. Third-Order Output Intercept vs Frequency and V
CC
20
VCC (V)
IP
(dBm) 3
4
TA = +25
C
5
6
7
8
9
DISABLED
f = 900MHz
15
10
5
0
-5
SR00188
Figure 27. Third-Order Input Intercept vs Frequency and V
CC
Philips Semiconductors
Product specification
SA5200
RF dual gain-stage
1997 Nov 07
512
25
VCC (V)
IP
(dBm) 2
4
5
6
7
8
9
DISABLED
900MHz
20
15
10
5
0
100MHz
500MHz
TA = +25
C
SR00191
Figure 28. Second-Order Output Intercept vs Frequency and
V
CC
ENABLE
OUT
ENABLE
OUT
SR00189
Figure 29. Switching Speed; f
IN
= 10MHz at 26dBm, V
DD
= 5V,
Coupling Capacitors Set to 0.01
F
4
IP
(dBm) 2
25
5
6
7
8
9
20
15
10
5
0
VCC (V)
DISABLED
f = 900MHz
TA = +25
C
SR00190
Figure 30. Second-Order Input Intercept vs Frequency and V
CC
ENABLE
OUT
SR00192
Figure 31. Switching Speed; f
IN
= 50MHz at 26dBm,
V
DD
= 5V, Coupling Capacitors Set to 100pF
Philips Semiconductors
Product specification
SA5200
RF dual gain-stage
1997 Nov 07
13
SO8:
plastic small outline package; 8 leads; body width 3.9mm
SOT96-1
Philips Semiconductors
Product specification
SA5200
RF dual gain-stage
1997 Nov 07
14
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation
register eligible circuits under the Semiconductor Chip Protection Act.
Copyright Philips Electronics North America Corporation 1993
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381
DEFINITIONS
Data Sheet Identification
Product Status
Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.