Philips Semiconductors

Product specification

SA7025

1GHz low-voltage Fractional-N synthesizer

1996 Aug 6

853-1786 17157

DESCRIPTION

The SA7025 is a monolithic low power, high performance dual
frequency synthesizer fabricated in QUBiC BiCMOS technology.
Featuring Fractional-N division with selectable modulo 5 or 8
implemented in the Main synthesizer to allow the phase detector
comparison frequency to be five or eight times the channel spacing.
This feature reduces the overall division ratio yielding a lower noise
floor and faster channel switching. The phase detectors and charge
pumps are designed to achieve phase detector comparison
frequencies up to 5MHz. A triple modulus prescaler (divide by
64/65/72) is integrated on chip with a maximum input frequency of
1.04GHz. Programming and channel selection are realized by a
high speed 3-wire serial interface.

FEATURES

Operation up to 1.04GHz

Fast locking by "Fractional-N" divider

Auxiliary synthesizer

Digital phase comparator with proportional and integral charge
pump output

High speed serial input

Low power consumption

Programmable charge pump currents

Supply voltage range 2.7 to 5.5V

Excellent input sensitivity: V

RF_IN

= 20dBm

APPLICATIONS

NADC (North American Digital Cellular)

PDC (Personal Digital Cellular)

Cellular radio

Spread-spectrum receivers

PIN CONFIGURATION

VSS

DATA

CLOCK

DK Package

STROBE

TEST

VDD

PHA

VDDA

PHP

VSSA

PHI

LOCK

RFIN

VCCP

REFIN

AUXIN

SR00600

Figure 1. Pin Configuration

ORDERING INFORMATION

DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

DWG #

20-Pin Plastic Shrink Small Outline Package (SSOP)

40 to +85

SA7025DK

SOT266-1

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

RATING

UNITS

Supply voltage, V

, V

DDA

, V

CCP

-0.3 to +6.0

Voltage applied to any other pin

-0.3 to (V

+ 0.3)

STG

Storage temperature range

-65 to +150

Operating ambient temperature range

-40 to +85

NOTE: Thermal impedance (

) = 117

C/W. This device is ESD sensitive.

Philips Semiconductors

Product specification

SA7025

1GHz low-voltage Fractional-N synthesizer

1996 Aug 6

PIN DESCRIPTIONS

Symbol

Pin

Description

CLOCK

Serial clock input

DATA

Serial data input

STROBE

Serial strobe input

Digital ground

Prescaler positive input

Prescaler negative input

CCP

Prescaler positive supply voltage. This pin supplies power to the prescaler and RF input buffer

REF

Reference divider input

Auxiliary current setting; resistor to V

SSA

AUX

Auxiliary divider input

PHA

Auxiliary phase detector output

SSA

Analog ground

PHI

Integral phase detector output

PHP

Proportional phase detector output

DDA

Analog supply voltage. This pin supplies power to the charge pumps, Auxiliary prescaler, Auxiliary and Reference
buffers.

Main current setting; resistor to V

SSA

Fractional compensation current setting; resistor to V

SSA

LOCK

Lock detector output

TEST

Test pin; connect to V

Digital supply voltage. This pin supplies power to the CMOS digital part of the device

Philips Semiconductors

Product specification

SA7025

1GHz low-voltage Fractional-N synthesizer

1996 Aug 6

DC ELECTRICAL CHARACTERISTICS

= V

DDA

= V

CCP

= 3V; T

= 25

C, unless otherwise specified.

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNITS

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

SUPPLY

Recommended operating conditions

CCP

= V

, V

DDA

2.7

5.5

STANDBY

Total standby supply currents

EM = EA = 0, I

= I

= 0

500

Operational supply currents: I = I

+ I

CCP

+ I

DDA

; I

= 25

A, I

= 25

A, (see Note 5)

AUX

Operational supply currents

EM = 0, EA = 1

3.5

MAIN

Operational supply currents

EM = 1, EA = 0

5.5

TOTAL

Operational supply currents

EM = EA = 1

7.5

Digital inputs CLK, DATA, STROBE

High level input voltage range

0.7xV

Low level input voltage range

0.3xV

Digital outputs LOCK

Output voltage LOW

= 2mA

0.4

Output voltage HIGH

= 2mA

0.4

Charge pumps: V

DDA

= 3V / I

= 25

A or V

DDA

= 5V / I

= 62.5

A, V

PHX

in range, unless otherwise specified. (See Note 16)

Setting current range for any setting re-

2.7V < V

DDA

< 5.5V

sistor

4.5V < V

DDA

< 5.5V

62.5

PHOUT

Output voltage range

0.7

DDA

0.8

Charge pump PHA

Output current PHA

= 62.5

A; V

PHA

= V

DDA

400

500

600

PHA

Output current PHA

= 25

A; V

PHA

= V

DDA

160

200

240

PHP_A

| I

PHP_A

Relative output current variation PHA

= 62.5

2, 13

Output current matching PHA pump

DDA

= 3V, I

= 25

PHA_M

Output current matching PHA pump

DDA

= 5V, I

= 62.5

Charge pump PHP, normal mode

1, 4, 6

= V

DDA

Output current PHP

= 62.5

A; V

PHP

= V

DDA

440

550

660

PHP_N

Output current PHP

= 25

A; V

PHP

= V

DDA

175

220

265

PHP_N

Relative output current variation PHP

= 62.5

2, 13

Output current matching PHP

DDA

= 3V, I

= 25

PHP_N_M

normal mode

DDA

= 5V, I

= 62.5

Charge pump PHP, speed-up mode

1, 4, 7

= V

DDA

Output current PHP

= 62.5

A; V

PHP

= V

DDA

2.20

2.75

3.30

PHP_S

Output current PHP

= 25

A; V

PHP

= V

DDA

0.85

1.1

1.35

PHP_S

Relative output current variation PHP

= 62.5

2, 13

Output current matching PHP

DDA

= 3V, I

= 25

250

PHP_S_M

speed-up mode

DDA

= 5V, I

= 62.5

300

Charge pump PHI, speed-up mode

1, 4, 8

= V

DDA

Output current PHI

= 62.5

A; V

PHI

= V

DDA

4.4

5.5

6.6

PHI

Output current PHI

= 25

A; V

PHI

= V

DDA

1.75

2.2

2.65

PHI

Relative output current variation PHI

= 62.5

2, 13

Output current matching PHI pump

DDA

= 3V, I

= 25

500

PHI_M

Output current matching PHI pump

DDA

= 5V, I

= 62.5

600

Fractional compensation PHP, normal mode

1, 9

= V

DDA

, V

PHP

= V

DDA

Fractional compensation output current

= 62.5

A;F

= 1 to 7

625

400

250

PHP_F_N

PHP vs F

= 25

A;F

= 1 to 7

250

180

100

Philips Semiconductors

Product specification

SA7025

1GHz low-voltage Fractional-N synthesizer

1996 Aug 6

DC ELECTRICAL CHARACTERISTICS

(Continued)

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNITS

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Fractional compensation PHP, speed up mode

1, 10

PHP

= V

DDA

, V

= V

DDA

Fractional compensation output current

= 62.5

A;F

= 1 to 7

3.35

2.0

1.1

PHP_F_S

PHP vs F

= 25

A;F

= 1 to 7

1.35

1.0

0.5

Pump leakage

Fractional compensation PHI, speed up mode

1, 11

PHP

= V

DDA

/2, V

= V

DDA

Fractional compensation output current

= 62.5

A;F

= 1 to 7

5.4

4.0

2.6

PHI_F

PHI vs F

= 25

A;F

= 1 to 7

2.15

1.6

1.05

Charge pump leakage currents, charge pump not active

PHP_L

Output leakage current PHP; normal
mode

PHP

= 0.7 to V

DDA

0.8

0.1

PHI_L

Output leakage current PHI; normal
mode

PHI

= 0.7 to V

DDA

0.8

0.1

PHA_L

Output leakage current PHA

PHA

= 0.7 to V

DDA

0.8

0.1

AC ELECTRICAL CHARACTERISTICS

= V

DDA

= V

CCP

= 3V; T

= 25

C; f

RF_IN

= 1GHz, input level = 20dBm; unless otherwise specified. Test Circuit, Figure 4. The parameters

listed below are tested using automatic test equipment to assure consistent electrical characteristics. The limits do not represent the ultimate
performance limits of the device. Use of an optimized RF layout will improve many of the listed parameters.

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNITS

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Main divider

Input signal frequency

Direct coupled input

1.04

GHz

RF_IN

Input signal frequency

1000pF input coupling

1.04

GHz

RF_IN

Input sensitivity

1040MHz

dBm

Reference divider (V

= V

DDA

= 3V or V

= 3V / V

DDA

= 5V)

Input signal frequency

2.7 < V

and V

DDA

< 5.5V

MHz

REF_IN

Input signal frequency

2.7 < V

and V

DDA

< 4.5V

MHz

Input signal range AC coupled

2.7 < V

and V

DDA

< 5.5V

500

REF_IN

Input signal range, AC coupled

2.7 < V

and V

DDA

< 4.5V

300

P-P

Reference divider input impedance

100

REF_IN

Reference divider input impedance

Auxiliary divider

Input signal frequency

PA = "0", prescaler enabled

4.5V

DDA

5.5V

150

MHz

AUX_IN

Input signal frequency

MHz

PA = "1", prescaler disabled

4.5V

DDA

5.5V

AUX_IN

Input signal range, AC coupled

200

P-P

Auxiliary divider input impedance

100

AUX_IN

Auxiliary divider input impedance

Serial interface

CLOCK

Clock frequency

MHz

Set-up time: DATA to CLOCK,
CLOCK to STROBE

Hold time; CLOCK to DATA

Pulse width; CLOCK

Pulse width; STROBE

B, C, D, E words

In-Loop Performance

DDA

= 5V, V

= 2.7V

Main loop residual FM

FVCO = 1030MHz

300

600

Philips Semiconductors

Product specification

SA7025

1GHz low-voltage Fractional-N synthesizer

1996 Aug 6

AC ELECTRICAL CHARACTERISTICS (continued)

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNITS

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Pulse width; STROBE

A word, PR = `01'

VCO

(NM2

65)

)

Pulse width STROBE

A word, PR = `10'

VCO

[(NM2

65)

)

(NM3

)

72]

)

NOTES:
1. When a serial input "A" word is programmed, the main charge pumps on PHP and PHI are in the "speed up mode" as long as STROBE = H.

When this is not the case, the main charge pumps are in the "normal mode".

2. The relative output current variation is defined thus:

OUT

)

|(I

)

; with V

= 0.7V, V

= V

DDA

0.8V (see Figure 3).

3. F

is the value of the 3 bit fractional accumulator.

4. Monotonicity is guaranteed with C

= 0 to 255.

5. Power supply current measured with V

= V

CCP

= 3V, V

DDA

= 5V, f

RF IN

= 915.99MHz, XTAL at 21.36MHz, AUX at 85.92MHz (PA = `0'),

Main comp frequency = 240kHz, Auxiliary comp frequency = 120kHz, CN = 160, CL = 0, CK = 0. Internal registers NM1 = 52, NM2 = 0,
NM3 = 4, PR = `10', SM = `00', SA = `01', NA = 179, NF = 5, FMOD = 8, NR = 89, PA = 0, IRN = IRA = IRF = 25

A, lock condition, normal

mode. Operational supply current = I

DDA

+ I

CCP

6. Specification condition: CN = 255
7. Specification conditions:

1) CN = 255; CL = 1, or
2) CN = 75; CL = 3

8. Typical output current | I

PHI

| = I

x CN x 2

(CL+1)

x CK/32:

1) CN = 160; CL = 3; CK = 1, or
2) CN = 160; CL = 2; CK = 2, or
3) CN = 160; CL = 1; CK = 4, or
4) CN = 160; CL = 0; CK = 8

9. Any RFD, CL = 1 for speed-up pump. The integral pump is intended for switching only and the fractional compensation is not guaranteed.
10. Specification conditions: F

= 1 to 7; CL = 1.

11. Specification conditions:

1) F

= 1 to 7; CL = 1; CK = 2, or

2) F

= 1 to 7; CL = 2; CK = 1.

12. The matching is defined by the sum of the P and the N pump for a given output voltage.
13. Limited analog supply voltage range 4.5 to 5.5V.
14. For f

< 50MHz, low frequency operation requires DC-coupling and a minimum input slew rate of 32V/

15. Guaranteed by design.
16. Close in noise for the charge pumps is tested on a sample basis in a typical application in order to eliminate parts outside the normal

distribution.

17. F

XTAL

= 14.4MHz, V

XTAL

= 500mV

P-P

, comparison frequency = 200kHz, Loop bandwidth = 5kHz, Audio filter = 300Hz to 15kHz.

Philips Semiconductors

Product specification

SA7025

1GHz low-voltage Fractional-N synthesizer

1996 Aug 6

AC TIMING CHARACTERISTICS

DATA

tSW

CLOCK

STROBE

CLOCK ENABLED

CLOCK

DISABLED

STORE DATA

SHIFT IN DATA

CLOCK

STROBE (B, C, D, E) WORDS

STROBE

(A WORD)

50%

tSU

LAST CLOCK

FIRST CLOCK

50%

tSU

D22,

D30

D23,

D31

SR00604

Figure 5. Serial Input Timing Sequence

FUNCTIONAL DESCRIPTION

Serial Input Programming

The serial input is a 3-wire input (CLOCK, STROBE, DATA) to
program all counter ratios, DACs, selection and enable bits. The
programming data is structured into 24 or 32 bit words; each word
includes 1 or 4 address bits. Figure 5 shows the timing diagram of
the serial input. When the STROBE = L, the clock driver is enabled
and on the positive edges of the CLOCK the signal on DATA input is
clocked into a shift register. When the STROBE = H, the clock is
disabled and the data in the shift register remains stable.
Depending on the 1 or 4 address bits the data is latched into
different working registers or temporary registers. In order to fully
program the synthesizer, 4 words must be sent: D, C, B and A.
Figure 6 and Table 1 shows the format and the contents of each
word. The E word is for testing purposes only. The E (test) word is
reset when programming the D word. The data for CN and PR is
stored by the B word in temporary registers. When the A word is
loaded, the data of these temporary registers is loaded together with
the A word into the work registers which avoids false temporary
main divider input. CN is only loaded from the temporary registers
when a short 24 bit A0 word is used. CN will be directly loaded by
programming a long 32 bit A1 word. The flag LONG in the D word
determines whether A0 (LONG = "0") or A1 (LONG = "1") format is
applicable. The A word contains new data for the main divider.

Main Divider Synchronization

The A word is loaded only when a main divider synchronization
signal is also active in order to avoid phase jumps when
reprogramming the main divider. The synchronization signal is
generated by the main divider. The signal is active while the NM1
divider is counting down from the programmed value. The new A
word will be loaded after the NM1 divider has reached its terminal
count; also, at this time a main divider output pulse will be sent to
the main phase detector. The loading of the A word is disabled
while the NM2 or NM3 dividers are counting up to their programmed

values. Therefore, the new A word will be correctly loaded provided
that the STROBE signal has been at an active high value for at least
a minimum number of VCO input cycles at RF

or RF

t_strobe_min

VCO

(NM

65)

)

for PR

`01

t_strobe_min

VCO

[NM

)

(NM

)

72]

)

for PR

`10

Programming the A word means also that the main charge pumps
on output PHP and PHI are set into the speed-up mode as long as
the STROBE is H.

Auxiliary Divider

The input signal on AUX_IN is amplified to logic level by a
single-ended CMOS input buffer, which accepts low level AC
coupled input signals. This input stage is enabled if the serial
control bit EA = "1". Disabling means that all currents in the input
stage are switched off. A fixed divide by 4 is enabled if PA = "0".
This divider has been optimized to accept a high frequency input
signal. If PA = "1", this divider is disabled and the input signal is fed
directly to the second stage, which is a 12-bit programmable divider
with standard input frequency (40MHz). The division ratio can be
expressed as:

if PA = "0": N = 4 x NA

if PA = "1": N = NA; with NA = 4 to 4095

Reference Divider

The input signal on REF_IN is amplified to logic level by a
single-ended CMOS input buffer, which accepts low level AC
coupled input signals. This input stage is enabled by the OR
function of the serial input bits EA and EM. Disabling means that all
currents in the input stage are switched off. The reference divider
consists of a programmable divider by NR (NR = 4 to 4095) followed
by a three bit binary counter. The 2 bit SM register (see Figure 7)
determines which of the 4 output pulses is selected as the main

Philips Semiconductors

Product specification

SA7025

1GHz low-voltage Fractional-N synthesizer

1996 Aug 6

phase detector input. The 2 bit SA register determines the selection
of the auxiliary phase detector signal.

Main Divider

The differential inputs are amplified (to internal ECL logic levels) and
provide excellent sensitivity (20dBm at 1GHz) making the prescaler
ideally suited to directly interface to a VCO as integrated on the
SA620 RF gain stage, VCO and mixer device. The internal triple
modulus prescaler feedback loop FB controls the selection of the
divide by ratios 64/65/72, and reduces the minimum system division
ratio below the typical value required by standard dual modulus
(64/65) devices.

This input stage is enabled when serial control bit EM = "1".
Disabling means that all currents in the prescaler are switched off.

The main divider is built up by a 12 bit counter plus a sign bit.
Depending on the serial input values NM1, NM2, NM3, and the
prescaler select PR, the counter will select a prescaler ratio during a
number of input cycles according to Table 2 and Table 3.

The loading of the work registers NM1, NM2, NM3 and PR is
synchronized with the state of the main counter, to avoid extra
phase disturbance when switching over to another main divider ratio
as explained in the Serial Input Programming section.

At the completion of a main divider cycle, a main divider output
pulse is generated which will drive the main phase comparator.
Also, the fractional accumulator is incremented with NF. The

accumulator works modulo Q. Q is preset by the serial control bit
FMOD to 8 when FMOD = "1". Each time the accumulator
overflows, the feedback to the prescaler will select one cycle using
prescaler ratio R2 instead of R1.

As shown above, this will increase the overall division ratio by 1 if
R2 = R1 + 1. The mean division ratio over Q main divider will then
be

)

Programming a fraction means the prescaler with main divider will
divide by N or N + 1. The output of the main divider will be
modulated with a fractional phase ripple. This phase ripple is
proportional to the contents of the fractional accumulator FRD,
which is used for fractional current compensation.

Phase Detectors

The auxiliary and main phase detectors are a two D-type flip-flop
phase and frequency detector shown in Figure 8. The flip-flops are
set by the negative edges of output signals of the dividers. The
rising edge of the signal, L, will reset the flip-flops after both flip-flops
have been set. Around zero phase error this has the effect of
delaying the reset for 1 reference input cycle. This avoids
non-linearity or deadband around zero phase error. The flip-flops
drive on-chip charge pumps. A source current from the charge
pump indicates the VCO frequency will be increased; a sink current
indicates the VCO frequency will be decreased.

Philips Semiconductors

Product specification

SA7025

1GHz low-voltage Fractional-N synthesizer

1996 Aug 6

MSB

LSB

WORD

ADDRESS BITS

TEST BITS

D31

NM1

NM2

NM3

NM2

NM1

NM2

NM3

NM2

D23

PR = "01"

PR = "10"

0 0

P
A

E
M

E
A

F
M
O
D

L
O
N
G

1 1

D23

0 0

LAST IN

FIRST IN

SR00605

Figure 6. Serial Input Word Format

Current Settings

The SA7025 has 3 current setting pins: RA, RN and RF. The active
charge pump currents and the fractional compensation currents are
linearly dependent on the current connected between the current
setting pin and V

. The typical value R (current setting resistor)

can be calculated with the formula:

DDA

0.9

150

The current can be set to zero by connecting the corresponding pin
to V

DDA

Auxiliary Output Charge Pumps

The auxiliary charge pumps on pin PHA are driven by the auxiliary
phase detector and the current value is determined by the external
resistor RA at pin RA. The active charge pump current is typically:

PHA

Main Output Charge Pumps and Fractional
Compensation Currents

The main charge pumps on pin PHP and PHI are driven by the main
phase detector and the current value is determined by the current at
pin RN and via a number of DACs which are driven by registers of
the serial input. The fractional compensation current is determined
by the current at pin RF, the contents of the fractional accumulator
FRD and a number of DACs driven by registers from the serial input.
The timing for the fractional compensation is derived from the
reference divider. The current is on during 1 input reference cycle
before and 1 cycle after the output signal to the phase comparator.
Figure 9 shows the waveforms for a typical case.

Philips Semiconductors

Product specification

SA7025

1GHz low-voltage Fractional-N synthesizer

1996 Aug 6

Table 1. Function Table

Symbol

Bits

Function

NM1

Number of main divider cycles when prescaler modulus = 64

NM2

8 if PR = "01"
4 if PR = "10"

Number of main divider cycles when prescaler modulus = 65

NM3

4 if PR = "10"

Number of main divider cycles when prescaler modulus = 72

Prescaler type in use
PR = "01": modulus 2 prescaler (64/65)
PR = "10": modulus 3 prescaler (64/65/72)

Fractional-N increment

FMOD

Fractional-N modulus selection flag
"1": modulo 8
"0": modulo 5

LONG

A word format selection flag
"0": 24 bit A0 format
"1": 32 bit A1 format

Binary current setting factor for main charge pumps

Binary acceleration factor for proportional charge pump current

Binary acceleration factor for integral charge pump current

Main divider enable flag

Auxiliary divider enable flag

Reference select for main phase detector

Reference select for auxiliary phase detector

Reference divider ratio

Auxiliary divider ratio

Auxiliary prescaler mode:
PA = "0": divide by 4
PA = "1": divide by 1

Not including reset cycles and Fractional-N effects.

SA = "11"

SA = "10"

SA = "01"

SA = "00"

SM = "11"

SM = "10"

SM = "01"

SM = "00"

MAIN SELECT

AUXILIARY SELECT

REFERENCE

INPUT

DIVIDE BY NR

MAIN

DETECTOR

PHASE

AUXILIARY

DETECTOR

PHASE

SR00606

Figure 7. Reference Divider

Table 2. Prescaler Ratio

The total division ratio from prescaler to the phase detector may be expressed as:

if PR = "01"

N = (NM1 + 2) x 64 + NM2 x 65

N' = (NM1 + 1) x 64 + (NM2 + 1) x 65 (*)

if PR = "10"

N = (NM1 + 2) x 64 + NM2 x 65 + (NM3 + 1) x 72

N' = (NM1 + 1) x 64 + (NM2 + 1) x 65 + (NM3 + 1) x 72 (*)

(*) When the fractional accumulator overflows the prescaler ratio = 65 (64 + 1) and the total division ratio N' = N + 1

Philips Semiconductors

Product specification

SA7025

1GHz low-voltage Fractional-N synthesizer

1996 Aug 6

Table 3. PR Modulus

Modulus Prescaler

Bit Capacity

NM1

NM2

NM3

When the serial input A word is loaded, the output circuits are in the
"speed-up mode" as long as the STROBE is H, else the "normal
mode" is active. In the "normal mode" the current output PHP is:

PHP_N

PHP

)

PHP_comp

where:

PHP

:charge pump current

PHP_comp

FRD

128

:fractional comp.

current

The current in PHI is zero in "normal mode".

In "speed-up mode" the current in output PHP is:

PHP_S

PHP

)

PHP_comp

PHP

)

PHP_comp

FRD

128

)

In "speed-up mode" the current in output PHI is:

PHI_S

PHI

)

PHI_comp

where:

PHI

)

) CK

PHI_comp

FRD

128

)

) CK

Figure 9 shows that for proper fractional compensation, the area of
the fractional compensation current pulse must be equal to the area
of the charge pump ripple output. This means that the current
setting on the input RN, RF is approximately:

VCO

)

INR

)

where:

fractional-N modulus

VCO

= f

INM

input frequency of the prescaler

INR

input frequency of the reference divider

PHI pump is meant for switching only. Current and compensation
are not as accurate as PHP.

REF_IN

REFERENCE

DIVIDER

AUX/MAIN

DIVIDER

"1"

N-TYPE

CHARGE PUMP

P-TYPE

CHARGE PUMP

VDDA

VSSA

REF_IN

SR00607

Figure 8. Phase Detector Structure with Timing

Philips Semiconductors

Product specification

SA7025

1GHz low-voltage Fractional-N synthesizer

1996 Aug 6

REFERENCE R

MAIN N

DETECTOR

OUTPUT

CONTENTS

ACCUM.

FRACTIONAL

COMPENSATION

CURRENT

N + 1

PULSE-WIDTH

MODULATION

OUTPUT ON

PHP, PHI

PULSE-LEVEL
MODULATION

TIME

VCO CYCLES

SR00608

Figure 9. Waveforms for NF = 2, Fraction = 0.4

Lock Detect

The output LOCK is H when the auxiliary phase detector AND the
main phase detector indicates a lock condition. The lock condition
is defined as a phase difference of less than +1 cycle on the
reference input REF_IN. The lock condition is also fulfilled when the
relative counter is disabled (EM = "0" or respectively EA = "0") for
the main, respectively auxiliary counter.

Test Modes

The lock output is selectable as f

REF

, f

AUX

, f

MAIN

and lock. Bits T1

and T0 of the E word control the selection (see Figures 6 and 10).

If T1 = T0 = Low, or if the E-word is not sent, the lock output is
configured as the normal lock output described in the Lock Detect
section.

If T1 = Low and T0 = High, the lock output is configured as f

REF

The signal is the buffered output of the reference divider NR and the
3-bit binary counter SM. The f

REF

signal appears as normally low

and pulses high whenever the divider reaches terminal count from
the value programmed into the NR and SM registers. The f

REF

signal can be used to verify the divide ratio of the Reference divider.

If T1 = High and T0 = Low, the lock output is configured as f

AUX

The signal is normally high and pulses low whenever the divider
reaches terminal count from the value programmed into the NA and

PA registers. The f

AUX

signal can be used to verify the divide ratio

of the Auxiliary divider.

If T1 = High and T0 = High, the lock output is configured as f

MAIN

The signal is the buffered output of the MAIN divider. The f

MAIN

signal appears as normally high and pulses low whenever the
divider reaches terminal count from the value programmed into the
NM1, NM2 or NM3 registers. The f

MAIN

signal can be used to verify

the divide ratio of the MAIN divider and the prescaler.

Philips Semiconductors

Product specification

SA7025

1GHz low-voltage Fractional-N synthesizer

1996 Aug 6

Test Pin

The Test pin, Pin 19, is a buffered logic input which is exclusively
ORed with the output of the prescaler. The output of the XOR gate
is the input to the MAIN divider. The Test pin must be connected to
V

during normal operation as a synthesizer. This pin can be used

as an input for verifying the divide ratio of the MAIN divider; while in
this condition the input to the prescaler, RF

, may be connected to

CCP

through a 10k

resistor in order to place prescaler output into

a known state.

MAIN

DIVIDER

REF

DIVIDER

AUX

DIVIDER

LOCK

MAIN

AUX

SELECT

LOGIC

SR00609

Figure 10. Test Mode Diagram

PIN FUNCTIONS

PIN

No.

PIN

MNEMONIC

DC V

EQUIVALENT CIRCUIT

PIN

No.

PIN

MNEMONIC

DC V

EQUIVALENT CIRCUIT

CLOCK

DATA

LOCK

STROBE

TEST

2.1

VDD

VSS

2.1

2.5k

VCCP = 3V

VSS

100k

REF

1.8

AUX

1.8

VDDA = 3V

VSS

ENABLE

1.35

VDDA = 3V

VSSA

PHA

PHI

PHP

VDDA

VSSA

VDD

VSS

SR00610

Figure 11. Pin Functions

Philips Semiconductors

Product specification

SA7025

1GHz low-voltage Fractional-N synthesizer

1996 Aug 6

TYPICAL PERFORMANCE CHARACTERISTICS

t = 40

t = 25

t = 85

SUPPLY VOLTAGE (V)

VCCP

= VDDA = VDD

EM = EA = 1, Note5

2.7

3.5

4.5

5.5

I T

(mA)

SR00611

Figure 12. Operational Supply Current vs Supply Voltage and

Temperature

SUPPLY VOLTAGE (V)

VCCP

= VDDA = VDD

EA=0, EM=1, Note5

2.7

3.5

4.5

5.5

I T

(mA)

t = 40

t = 25

t = 85

SR00612

Figure 13. Auxiliary Operational Supply Current vs Supply

Voltage and Temperature

2.7V

3.5V

4.5V

5.5V

TA = 25

N = 3971.625

VDD = VCCP

FREQUENCY (MHz)

500

INPUT POWER (dBm)

550

600

650

700

750

800

850

900

950

1000

1050

100

150

SR00613

Figure 14. Main Divider Input Power vs frequency and Supply

SUPPLY VOLTAGE (V)

VCCP

= VDDA = VDD

EA=0, EM=1, Note5

8.5

7.5

6.5

5.5

4.5

2.7

3.5

4.5

5.5

I T

(mA)

t = 40

t = 25

t = 85

SR00614

Figure 15. Main Operational Supply Current vs Supply Voltage

and Temperature

AUXILIARY INPUT FREQUENCY (MHz)

VDD = 3V, VDDA = 5V

Pin = 10dBm,

ref divider halted

3.5

100

150

I T

(mA)

2.5

1.5

t = 40

t = 25

t = 85

SR00615

Figure 16. Auxiliary Operational Supply Current vs Frequency

and Temperature

t=40

t=25

t=85

VDD = VCCP = 3V

N=3971.625

FREQUENCY (MHz)

500

INPUT POWER (dBm)

550

600

650

700

750

800

850

900

950

1000

1050

100

150

SR00616

Figure 17. Main Divider Input Power vs Frequency and

Temperature

Philips Semiconductors

Product specification

SA7025

1GHz low-voltage Fractional-N synthesizer

1996 Aug 6

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

3/3V
3/5V
5/5V

N=100

VDD/VDDA

INPUT POWER (dBm)

FREQUENCY (MHz)

SR00617

Figure 18. Reference Divider Minimum Input Power vs

frequency and Supply

MINIMUM

INPUT

POWER (dBm)

TA =amb,
PA=1,
N=100

110

130

150

FREQUENCY (MHz)

VDD/VDDA

3/3V
3/5V
5/5V

SR00618

Figure 19. Auxiliary Divider Minimum Input Power vs

Frequency and Supply

TA = amb,
PA=0,
N=25

100

150

200

250

FREQUENCY (MHz)

VDD/VDDA

MINIMUM

INPUT

POWER (dBm)

3/3V
3/5V
5/5V

Figure 20. Auxiliary Divider Minimum Input Power vs

Frequency and Supply

MINIMUM

INPUT

POWE (dBm)

FREQUENCY (dBm)

VDD= 3V,
VDDA= 5V,
N = 100

t = 40

t = 25

t = 85

SR00631

Figure 21. Reference Divider Minimum Input Power vs

Frequency and Temperature

VDD =3V,
VDDA=5V,
PA=1,
N=100

FREQUENCY (MHz)

MINIMUM

INPUT

POWER (dBm)

t = 40

t = 25

t = 85

SR00632

Figure 22. Auxiliary Divider Minimum Input Power vs

Frequency and Temperature

VDD=3V,
VDDA=5V

100

150

200

FREQUENCY (MHz)

MINIMUM

INPUT

POWER (dBm)

t = 40

t = 25

t = 85

PA=0,
N=25

SR00619

Figure 23. Auxiliary Divider Minumum Input Power vs

Frequency and Temperature

Philips Semiconductors

Product specification

SA7025

Low-voltage 1GHz fractional-N synthesizer

Philips

Semiconductors

Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.

LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381

DEFINITIONS

Data Sheet Identification

Product Status

Definition

Objective Specification

Preliminary Specification

Product Specification

Formative or in Design

Preproduction Product

Full Production

This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.

This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.

Philips Semiconductors and Philips Electronics North America Corporation

print code

Document order number:

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SA7025

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SA7025