Philips Semiconductors
Product specification
SA703
Divide by: 128/129/144 triple modulus low power
ECL prescaler
717
1993 Jun 17
853-1710 10044
DESCRIPTION
The SA703 triple modulus (Divide By 128/129/144) low power ECL
prescaler is used in synthesizer systems to achieve low phase lock
time, broad operating range, high reference frequency and small
frequency step sizes. The minimum supply voltage is 2.7V and is
compatible with the UMA1005 synthesizer from Philips and other
logic circuits. The low supply current allows application in battery
operated low-power equipment. Maximum input signal frequency is
1.1GHz for cellular and other land mobile applications. There is no
lower frequency limit due to a fully static design. The circuit is
implemented in ECL technology on the QUBiC process. The circuit
will be available in an 8-pin SO package with 150 mil package width
and in 8-pin dual in-line plastic package.
APPLICATIONS
Cellular phones
Cordless phones
RF LANs
Test and measurement
Military radio
PIN CONFIGURATION
IN
VCC
MC2
OUT
IN
MC1
1
2
3
4
5
6
7
8
GND
OUT
N, D Package
SR00551
Figure 1. Pin Configuration
VHF/UHF mobile radio
VHF/UHF hand-held radio
FEATURES
Low voltage operation
Low current consumption
Operation up to 1.1GHz
ESD hardened
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
DWG #
8-Pin Plastic Dual In-Line Package (DIP)
-40 to +85
C
SA703N
SOT97-1
8-Pin Plastic Small Outline (SO) package (Surface-mount)
-40 to +85
C
SA703D
SOT96-1
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNITS
V
CC
Supply voltage
-0.3 to +7.0
V
V
IN
Voltage applied to any other pin
-0.3 to (V
CC
+ 0.3)
V
I
O
Output current
10
mA
T
STG
Storage temperature range
-65 to +125
C
T
A
Operating ambient temperature range
-55 to +125
C
JA
Thermal impedance
D package
N package
158
108
C/W
Philips Semiconductors
Product specification
SA703
Divide by: 128/129/144 triple modulus low power ECL
prescaler
1993 Jun 17
719
DC ELECTRICAL CHARACTERISTICS
The following DC specifications are valid for T
A
= 25
C and V
CC
= 3.0V; unless otherwise stated. Test circuit Figure 4.
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNITS
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
Power supply voltage range
f
IN
= 1GHz, input level = 0dBm
2.7
6.0
V
I
CC
Supply current
No load
4.5
mA
V
OH
Output high level
I
OUT
= 1.2mA
V
CC
-1.4
V
V
OL
Output low level
V
CC
-2.6
V
V
IH
MC1 input high threshold
2.0
V
CC
V
V
IL
MC1 input low threshold
0.3
0.8
V
V
IH
MC2 input high threshold
2.0
V
CC
V
V
IL
MC2 input low threshold
0.3
0.8
V
I
IH
MC1 input high current
V
MC1
= V
CC
= 6V
0.1
50
A
I
IL
MC1 input low current
V
MC1
= 0V, V
CC
= 6V
100
30
A
I
IH
MC2 input high current
V
MC2
= V
CC
= 6V
0.1
50
A
I
IL
MC2 input low current
V
MC2
= 0V, V
CC
= 6V
100
30
A
AC ELECTRICAL CHARACTERISTICS
These AC specifications are valid for V
CC
= 3.0V, f
IN
= 1GHz, input level = 0dBm, T
A
= 25
C; unless otherwise stated. Test circuit Fig. 4.
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNITS
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V
IN
Input signal amplitude
1
1000pF input coupling
0.05
2.0
V
P-P
f
IN
Input signal frequency
Direct coupled input
2
0
1.1
GHz
f
IN
Input signal frequency
1000pF input coupling
1.1
GHz
R
ID
Differential input resistance
DC measurement
5
k
V
O
Output voltage
V
CC
= 5.0V
1.6
V
P P
V
O
Output voltage
V
CC
= 3.0V
1.2
V
P-P
t
S
Modulus set-up time
1
5
ns
t
H
Modulus hold time
1
0
ns
t
PD
Propagation time
10
ns
NOTES:
1. Maximum limit is not tested, however, it is guaranteed by design and characterization.
2. For f
IN
< 50MHz, minimum input slew rate of 32V/
s is required.
DESCRIPTION OF OPERATION
The SA703 comprises a frequency divider circuit implemented using
a divide by 4 or 5 synchronous prescaler followed by a 5 stage
synchronous counter, see BLOCK DIAGRAM. The normal
operating mode is for MC1 (Modulus Control) to be set high and
MC2 input to be set low in which case the circuit comprises a divide
by 128. For divide by 129 the MC1 singal is forced low, causing the
prescaler circuit to switch into divide by 5 operation for the last cycle
of the synchronous counter. For divide by 144, MC2 is set high
configuring the prescaler to divide by 4 and the counter to divide by
36. A truth table for the modulus values is given in Table 1.
For minimization of propagation delay effects, the second divider
circuit is synchronous to the divide by 4/5 stage output.
The prescaler input is positive edge sensitive, and the output at the
final count is a falling edge with propagation delay t
PD
relative to the
input. The rising edge of the output occurs at the count 64 with
delay t
PD
.
The MC1 and MC2 inputs are TTL compatible threshold inputs
operating at a reduced input current. CMOS and low voltage
interface capability are allowed.
The prescaler input is differential and ECL compatible. The output is
differential ECL compatible.
Table 1.
Modulus
MC1
MC2
128
1
0
129
0
0
144
0
1
144
1
1
Philips Semiconductors
Product specification
SA703
Divide by: 128/129/144 triple modulus low power ECL
prescaler
1993 Jun 17
721
IN
VCC
MC2
OUT
OUT
MC1
GND
IN
50
50
IN
IN
C1
1000pF
C2
1000pF
50
R1
50
R2
MC1
VCC
MC2
2.2k
R3
C4
5pF
OUT
C3
0.1
F
2.2k
R4
C5
5pF
OUT
SR00554
Figure 4. SA703 Test Circuit
0
5
10
15
20
25
30
35
40
200
400
600
800
1000
1200
25
C
MINIMUM INPUT POWER (dBm)
FREQUENCY (MHz)
40
C
85
C
VCC = 3.0V
SR00555
Figure 5. Minimum Input Power vs Frequency and Temperature
Philips Semiconductors
Product specification
SA703
Divide by: 128/129/144 triple modulus low power ECL
prescaler
1993 Jun 17
722
0
5
10
15
20
25
30
35
40
200
400
600
800
1000
1200
TA = 25
C
2.7V
3.0V
6.0V
MINIMUM INPUT POWER (dBm)
FREQUENCY (MHz)
SR00556
Figure 6. Minimum Input Power vs Frequency and V
CC
VCC (V)
6
5.5
5
4.5
4
3.5
3
2.7
3
6
7
I (mA) CC
85
C
40
C
25
C
SR00557
Figure 7. Supply Current vs Supply Voltage and Temperature With No Load
Philips Semiconductors
Product specification
SA703
Divide by: 128/129/144 triple modulus low power ECL
prescaler
1993 Jun 17
723
R3
L4
R1
C2
C1
INPUT
4
6nH
0.4pF
0.9pF
3000
0
j0.2
j0.5
j1
j2
j5
j5
j2
j1
j0.5
j0.2
0.2
0.5
1
2
5
VCC = 3V
TA = 25
C
EQUIVALENT INPUT IMPEDANCE
50
300
600
900
1200
SR00558
Figure 8. Typical N Package Input Impedance
R3
L4
R1
C2
C1
INPUT
2
3nH
0.2pF
0.9pF
3000
0
j0.2
j0.5
j1
j2
j5
j5
j2
j1
j0.5
j0.2
0.2
0.5
1
2
5
VCC = 3V
TA = 25
C
EQUIVALENT INPUT IMPEDANCE
50
300
600
900
1200
SR00559
Figure 9. Typical D Package Input Impedance
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