Philips Semiconductors

Product specification

SA8026

2.5GHz low voltage fractional-N dual frequency
synthesizer

1999 Nov 04

8532141 22633

GENERAL DESCRIPTION

The SA8026 BICMOS device integrates programmable dividers,
charge pumps and a phase comparator to implement a
phase-locked loop. The device is designed to operate from 3 NiCd
cells, in pocket phones, with low current and nominal 3 V supplies.

The synthesizer operates at VCO input frequencies up to 2.5 GHz.
The synthesizer has fully programmable main, auxiliary and
reference dividers. All divider ratios are supplied via a 3-wire serial
programming bus.

Separate power and ground pins are provided to the analog and
digital circuits. The ground leads should be externally short-circuited
to prevent large currents flowing across the die and thus causing
damage. V

DDCP

must be greater than or equal to

The charge pump current (gain) is set by an external resistance at
R

SET

Passive loop filters could be used; the charge pump

operates within a wide voltage compliance range to provide a wider
tuning range.

FEATURES

Low phase noise

Low power

Fully programmable main and auxiliary dividers

Normal & Integral charge pumps outputs

Fast Locking Adaptive mode design

Internal fractional spurious compensation

Hardware and software power down

Split supply for V

and V

DDCP

SR01649

LOCK

TEST

GND

RFin+

RFin

GND

PHP

PHI

GND

PON

STROBE

DATA

CLOCK

REFin+

REFin

SET

AUXin

DDCP

PHA

Figure 1.

Pin Configuration

APPLICATIONS

350 to 2500 MHz wireless equipment

Cellular phones (all standards)

WLAN

Portable battery-powered radio equipment.

QUICK REFERENCE DATA

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply voltage

2.7

5.5

DDCP

Analog supply voltage

DDCP

2.7

5.5

DDCP

Total supply current

Main and Aux. on

DDCP

Total supply current in power-down mode

VCO

Input frequency

350

2500

MHz

AUX

Input frequency

550

MHz

REF

Crystal reference input frequency

MHz

Maximum phase comparator frequency

MHz

amb

Operating ambient temperature

+85

ORDERING INFORMATION

TYPE NUMBER

PACKAGE

TYPE NUMBER

NAME

DESCRIPTION

VERSION

SA8026DH

TSSOP20

Plastic thin shrink small outline package; 20 leads; body width 4.4 mm

SOT3601

Philips Semiconductors

Product specification

SA8026

2.5GHz low voltage fractional-N dual frequency
synthesizer

1999 Nov 04

SR01496

CLOCK

DATA

STROBE

RFin+

RFin

REFin+

REFin

AUXin

TEST

LOAD SIGNALS

ADDRESS DECODER

2BIT SHIFT

22BIT SHIFT

CONTROL

LATCH

MAIN DIVIDER

REFERENCE

DIVIDER

2 2 2 2

LATCH

AMP

LATCH

AUX DIVIDER

PHASE

DETECTOR

PHASE

DETECTOR

COMP

PUMP

BIAS

PUMP

CURRENT

SETTING

DDCP

GND

7, 10

GND

SET

PHP

PHI

LOCK

PHA

PON

Figure 2.

Block Diagram

PINNING

SYMBOL

PIN

DESCRIPTION

LOCK

Lock detect output

TEST

Test (should be either grounded or
connected to V

)

Digital supply

GND

Digital ground

RFin+

RF input to main divider

RFin

RF input to main divider

GND

Charge pump ground

PHP

Main normal charge pump

PHI

Main integral charge pump

GND

Charge pump ground

SYMBOL

PIN

DESCRIPTION

PHA

Auxiliary charge pump output

AUXin

Input to auxiliary divider

DDCP

Charge pump supply voltage

SET

External resistor from this pin to ground
sets the charge pump current

REFin

Reference input

REFin+

Reference input

CLOCK

Programming bus clock input

DATA

Programming bus data input

STROBE

Programming bus enable input

PON

Power down control

Philips Semiconductors

Product specification

SA8026

2.5GHz low voltage fractional-N dual frequency
synthesizer

1999 Nov 04

Limiting values

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

Digital supply voltage

0.3

+5.5

DDCP

Analog supply voltage

0.3

+5.5

DDCP

Difference in voltage between V

DDCP and

DDCP

)

0.3

+2.8

Voltage at pins 1, 2, 5, 6, 12, 15 to 20

0.3

+ 0.3

Voltage at pin 8, 9, 11

0.3

DDCP

+ 0.3

GND

Difference in voltage between GND

and GND (these pins should be

connected together)

0.3

+0.3

stg

Storage temperature

+125

amb

Operating ambient temperature

+85

Maximum junction temperature

150

Handling

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal
precautions appropriate to handling MOS devices.

Thermal characteristics

SYMBOL

PARAMETER

VALUE

UNIT

th ja

Thermal resistance from junction to ambient in free air

135

K/W

Philips Semiconductors

Product specification

SA8026

2.5GHz low voltage fractional-N dual frequency
synthesizer

1999 Nov 04

CHARACTERISTICS

DDCP

= V

= +3.0V,

amb

= +25

unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply; pins 3, 13

Digital supply voltage

2.7

5.5

DDCP

Analog supply voltage

DDCP

2.7

5.5

DDTotal

Synthesizer operational total supply current

= +3.0V

(with main and aux on)

Standby

Total supply current in power-down mode

logic levels 0 or V

RFin main divider input; pins 5, 6

VCO

VCO input frequency

350

2500

MHz

RFin(rms)

AC-coupled input signal level

(external) = R

= 50

;

single-ended drive;
max. limit is indicative
@ 500 to 2500 MHz

dBm

IRFin

Input impedance (real part)

VCO

= 2.4 GHz

300

IRFin

Typical pin input capacitance

VCO

= 2.4 GHz

main

Main divider ratio

512

65535

PCmax

Maximum loop comparison frequency

indicative, not tested

MHz

AUX reference divider input; pin 12

AUXin

Input frequency range

550

MHz

AC coupled input signal level

(external) = R

= 50

;

dBm

AUXin

AC-coupled input signal level

(

)

max. limit is indicative

632

AUXin

Input impedance (real part)

VCO

= 500 MHz

3.9

AUXin

Typical pin input capacitance

VCO

= 500 MHz

0.5

AUX

Auxiliary division ratio

128

16383

Reference divider input; pins 15, 16

REFin

Input frequency range from TCXO

MHz

RFin

AC-coupled input signal level

single-ended drive;
max. limit is indicative

360

1300

REFin

Input impedance (real part)

REF

= 20 MHz

REFin

Typical pin input capacitance

REF

= 20 MHz

REF

Reference division ratio

SA = SM = "000"

1023

Charge pump current setting resistor input; pin 14

SET

External resistor from pin to ground

7.5

SET

Regulated voltage at pin

SET

= 7.5 k

1.25

Charge pump outputs (including fractional compensation pump); pins 8, 9, 11; R

SET

= 7.5 k

, FC = 80

Charge pump current ratio to I

SET

Current gain = I

SET

+15

MATCH

Sink-to-source current matching

= 1/2 V

DDCP

+10

ZOUT

Output current variation versus V

in compliance range

+10

LPH

Charge pump off leakage current

= 1/2 V

DDCP

+10

Charge pump voltage compliance

0.7

DDCP

0.8

Philips Semiconductors

Product specification

SA8026

2.5GHz low voltage fractional-N dual frequency
synthesizer

1999 Nov 04

CHARACTERISTICS (continued)

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Phase noise (condition R

SET

= 7.5 k

, CP = 00)

Synthesizer's contribution to close-in phase noise
of 900 MHz RF signal at 1 kHz offset.

GSM

REF

= 13MHz, TCXO,

dBc/Hz

Synthesizer's contribution to close-in phase noise
of 1800 MHz RF signal at 1 kHz offset.

REF

= 13MHz, TCXO,

COMP

= 1MHz

indicative, not tested

dBc/Hz

(f)

Synthesizer's contribution to close-in phase noise
of 800 MHz RF signal at 1 kHz offset.

TDMA

REF

= 19.44MHz, TCXO,

dBc/Hz

Synthesizer's contribution to close-in phase noise
of 2100 MHz RF signal at 1 kHz offset.

REF

= 19.44MHz, TCXO,

COMP

= 240kHz

indicative, not tested

dBc/Hz

Interface logic input signal levels; pins 2, 17, 18, 19, 20

HIGH level input voltage

0.7*V

+0.3

LOW level input voltage

0.3

0.3*V

LEAK

Input leakage current

logic 1 or logic 0

0.5

+0.5

Lock detect output signal (in push/pull mode); pin 1

LOW level output voltage

sink

= 2mA

0.4

HIGH level output voltage

source

= 2mA

0.4

NOTES:

1. I

SET =

SET

bias current for charge pumps.

2. The relative output current variation is defined as:

OUT

)

I(I

)

; with V

0.7V, V

DDCP

0.8V (See Figure 3.)

CURRENT

SR00602

ZOUT

Figure 3.

Relative Output Current Variation

Philips Semiconductors

Product specification

SA8026

2.5GHz low voltage fractional-N dual frequency
synthesizer

1999 Nov 04

FUNCTIONAL DESCRIPTION

Main Fractional-N divider

The RFin inputs drive a pre-amplifier to provide the clock to the first
divider stage. For single ended operation, the signal should be fed to
one of the inputs while the other one is AC grounded. The
pre-amplifier has a high input impedance, dominated by pin and pad
capacitance. The circuit operates with signal levels from 18 dBm to
0 dBm, and at frequencies as high as 2.5 GHz. The divider consists
of a fully programmable bipolar prescaler followed by a CMOS
counter. Total divide ratios range from 512 to 65536.

At the completion of a main divider cycle, a main divider output
pulse is generated which will drive the main phase comparator. Also,
the fractional accumulator is incremented by the value of NF. The
accumulator works with modulo Q set by FMOD. When the
accumulator overflows, the overall division ratio N will be increased
by 1 to N + 1, the average division ratio over Q main divider cycles
(either 5 or 8) will be

Nfrac

)

The output of the main divider will be modulated with a fractional
phase ripple. The phase ripple is proportional to the contents of the
fractional accumulator and is nulled by the fractional compensation
charge pump.

The reloading of a new main divider ratio is synchronized to the
state of the main divider to avoid introducing a phase disturbance.

Auxiliary divider

The AUXin input drives a pre-amplifier to provide the clock to the
first divider stage. The pre-amplifier has a high input impedance,
dominated by pin and pad capacitance. The circuit operates with
signal levels from 18dBm to 0 dBm (80 to 636 mVpp), and at
frequencies as high as 550 MHz. The divider consists of a fully
programmable bipolar prescaler followed by a CMOS counter. Total
divide ratios ranges from 128 to 16383.

Reference divider

The reference divider consists of a divider with programmable
values between 4 and 1023 followed by a three bit binary counter.
The 3 bit SM (SA) register (see figure 4) determines which of the 5
output pulses are selected as the main (auxiliary) phase detector
input.

Phase detector (see Figure 5)

The reference and main (aux) divider outputs are connected to a
phase/frequency detector that controls the charge pump. The pump
current is set by an external resistor in conjunction with control bits
CP0 and CP1 in the C-word (see Charge Pump table). The dead
zone (caused by finite time taken to switch the current sources on or
off) is cancelled by forcing the pumps ON for a minimum time at
every cycle (backlash time) providing improved linearity.

SR01415

DIVIDE BY R

REFERENCE
INPUT

SM="000"

SM="001"

SM="010"

SM="011"

SM="100"

SA="100"

SA="011"

SA="010"

SA="001"

SA="000"

MAIN

PHASE

DETECTOR

AUXILIARY

PHASE

DETECTOR

Figure 4.

Reference Divider

Philips Semiconductors

Product specification

SA8026

2.5GHz low voltage fractional-N dual frequency
synthesizer

1999 Nov 04

Main Output Charge Pumps and Fractional
Compensation Currents (see Figure 6)

The main charge pumps on pins PHP and PHI are driven by the
main phase detector and the charge pump current values are
determined by the current at pin R

SET

in conjunction with bits CP0,

CP1 in the C-word (see table of charge pump ratios). The fractional
compensation is derived from the current at R

SET

, the contents of

the fractional accumulator FRD and by the program value of the
FDAC. The timing for the fractional compensation is derived from
the main divider. The main charge pumps will enter speed up mode
after the A-word is set and strobe goes High. When strobe goes
Low, charge pump will exit speed up mode.

Principle of Fractional Compensation

The fractional compensation is designed into the circuit as a means
of reducing or eliminating fractional spurs that are caused by the
fractional phase ripple of the main divider. If I

COMP

is the

compensation current and I

PUMP

is the pump current, then for each

charge pump:

PUMP_TOTAL

= I

PUMP

+ I

COMP

The compensation is done by sourcing a small current, I

COMP

, see

Figure 7, that is proportional to the fractional error phase. For proper
fractional compensation, the area of the fractional compensation
current pulse must be equal to the area of the fractional charge
pump ripple. The width of the fractional compensation pulse is fixed
to 128 VCO cycles, the amplitude is proportional to the fractional
accumulator value and is adjusted by FDAC values (bits FC70 in
the B-word). The fractional compensation current is derived from the
main charge pump in that it follows all the current scaling through
external resistor setting, R

SET

, programming or speed-up operation.

For a given charge pump,

COMP

= ( I

PUMP

/ 128 ) * ( FDAC / 5*128) * FRD

FRD is the fractional accumulator value.

The target values for FDAC are: 128 for FMOD = 1 (modulo 5) and
80 for FMOD = 0 (modulo 8).

SR01416

REFERENCE R

MAIN M
DIVIDE RATIO

DETECTOR
OUTPUT

ACCUMULATOR

FRACTIONAL
COMPENSATION
CURRENT

OUTPUT ON
PUMP

N+1

PULSE
WIDTH
MODULATION

PULSE LEVEL
MODULATION

NOTE: For a proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the charge pump ripple output.

Figure 6.

Waveforms for NF = 2 Modulo 5

fraction =

SR01800

MAIN DIVIDER

FRACTIONAL

ACCUMULATOR

REF

COMP

PUMP

LOOP FILTER

& VCO

Figure 7.

Current Injection Concept

Philips Semiconductors

Product specification

SA8026

2.5GHz low voltage fractional-N dual frequency
synthesizer

1999 Nov 04

Auxiliary Output Charge Pumps

The auxiliary charge pump on pin PHA are driven by the auxiliary phase detector and PHP, PHI are driven by the main phase detector. The
current value is determined by the external resistor attached to pin R

SET

Main and auxiliary charge pump currents

CP1

CP0

PHA

PHP

PHPSU

PHI

1.5xl

SET

3xI

SET

15xl

SET

36xl

SET

0.5xl

SET

1xl

SET

5xl

SET

12xl

SET

1.5xl

SET

3xl

SET

15xl

SET

0.5xl

SET

1xl

SET

5xl

SET

NOTES
1. I

SET

= V

SET

: bias current for charge pumps.

2. CP1 is used to disable the PHI pump, I

PHPSU

is the total current at pin PHP during speed up condition.

Lock Detect

The output LOCK maintains a logic `1' when the auxiliary phase
detector ANDed with the main phase detector indicates a lock
condition. The lock condition for the main and auxiliary synthesizers
is defined as a phase difference of less than

1 period of the

frequency at the input REF

in+,

. One counter can fulfill the lock

condition when the other counter is powered down. Out of lock (logic
'0') is indicated when both counters are powered down.

Power-down mode

The power-down signal can be either hardware (PON) or software
(PD). The PON signal is exclusively ORed with the PD bits in
B-word. If PON = 0, then the part is powered up when PD = 1. PON
can be used to invert the polarity of the software bit PD. When the
synthesizer is reactivated after power-down, the main and reference
dividers are synchronized to avoid possibility of random phase
errors on power-up.

Philips Semiconductors

Product specification

SA8026

2.5GHz low voltage fractional-N dual frequency
synthesizer

1999 Nov 04

Serial programming bus

The serial input is a 3-wire input (CLOCK, STROBE, DATA) to
program all counter divide ratios, fractional compensation DAC,
selection and enable bits. The programming data is structured into
24 bit words; each word includes 2 or 3 address bits. Figure 8
shows the timing diagram of the serial input. When the STROBE
goes active HIGH, the clock is disabled and the data in the shift
register remains unchanged. Depending on the address bits, the

data is latched into different working registers or temporary
registers. In order to fully program the synthesizer, 3 words must be
sent: C, B, and A. Table 1 shows the format and the contents of
each word. The D word is normally used for testing purposes. When
sending the B-word, data bits FC70 for the fractional compensation
DAC are not loaded immediately. Instead they are stored in
temporary registers. Only when the A-word is loaded, these
temporary registers are loaded together with the main divider ratio.

Serial bus timing characteristics. See Figure 8.

= V

DDCP

=+3.0V; T

amb

= +25

C unless otherwise specified.

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

Serial programming clock; CLK

Input rise time

Input fall time

Clock period

100

Enable programming; STROBE

START

Delay to rising clock edge

Minimum inactive pulse width

1/f

COMP

SU;E

Enable set-up time to next clock edge

Register serial input data; DATA

SU;DAT

Input data to clock set-up time

HD;DAT

Input data to clock hold time

Application information

SR01417

CLK

DATA

STROBE

ADDRESS

LSB

SU;DAT

HD;DAT

SU;E

START

MSB

Figure 8.

Serial Bus Timing Diagram

Philips Semiconductors

Product specification

SA8026

2.5GHz low voltage fractional-N dual frequency
synthesizer

1999 Nov 04

Data format

Table 1. Format of programmed data

Last In

MSB

Serial Programming Format

First In LSB

p23

p22

p21

p20

../..

Table 2. A word, length 24 bits

Last In

MSB

LSB

First In

Address

fmod

Fractional-N

Main Divider ratio

Spare

NF2

NF1

NF0

N15

N14

N13

N12

N11

N10

SK1

SK2

Default

A word select

Fixed to 00.

Fractional Modulus select

FM 0 = modulo 8, 1 = modulo 5.

Fractional-N Increment

NF2..0 Fractional N Increment values 000 to 111.

N-Divider

N0..N15, Main divider values 512 to 65535 allowed for divider ratio.

Table 3. B word, length 24 bits

Address

Reference Divider

Lock

Fractional Compensation DAC

Main

Aux

FC7

FC6

FC5

FC4

FC3

FC2

FC1

FC0

Default

B word select

Fixed to 01

R-Divider

R0..R9, Reference divider values 4 to 1023 allowed for divider ration.

Lock detect output

L1 L0
0 0

Combined main, aux. lock detect signal present at the LOCK pin (push/pull).

0 1

Combined main, aux, lock detect signal present at the LOCK pin (open drain).

1 0

Main lock detect signal present at the LOCK pin (push/pull).

1 1

Auxiliary loop lock detect signal present at the LOCK pin (push/pull).

When auxiliary loop and main loop are in power down mode, the lock indicator is low.

Power down

Main = 1: power to N-divider, reference divider, main charge pumps, Main = 0 to power down.
Aux = 1: power to Aux divider, reference divider, aux charge pump, Aux = 0 to power down.

Fractional Compensation

FC7..0 Fractional Compensation charge pump current DAC, values 0 to 255.

Table 4. C word, length 24 bits

Address

Auxiliary Divider

A13

A12

A11

A10

CP1

CP0

SM2

SM1

SM0

SA2

SA1

SA0

Default

C word select

Fixed to 10

A-Divider

A0..A13, Auxiliary divider values 128 to 16383 allowed for divider ratio.

Charge pump current Ratio

CP1, CP0: Charge pump current ratio, see table of charge pump currents.

Main comparison select

comparison divider select for main phase detector.

Aux comparison select

Comparison divider select for auxiliary phase detector.

Table 5. D word, length 24 bits

Address

Synthesizer Test Bits

Tspu

Default

Tspu: Speed up = 1

Forces the main charge pumps in speed-up mode all the time.
NOTE: All test bits must be set to 0 for normal operation.

Philips Semiconductors

Product specification

SA8026

2.5GHz low voltage fractional-N dual frequency
synthesizer

1999 Nov 04

TYPICAL PERFORMANCE CHARACTERISTICS

SR01855

3000

2000

1000

2000

3000

0.25

0.5

0.75

1.25

1.5

1.75

2.25

2.5

2.75

ICP

(uA)

COMPLIANCE VOLTAGE (V)

SET

= 206.67

SET

= 206.67

SET

= 165.33

SET

= 165.33

SET

= 103.33

SET

= 103.33

SET

= 51.67

SET

= 51.67

Figure 9.

PHI Charge Pump vs. I

SET

(CP = 01; Temp = 25

SR01856

2500

2000

1500

1000

500

1000

1500

2000

2500

0.25 0.5 0.75

1.25 1.5 1.75

2.25 2.5 2.75

3.25 3.5

Icp (uA)

COMPLIANCE VOLTAGE (V)

+85

+25

Figure 10.

PHI Charge Pump Output vs. Temperature

(CP = 01; V

= 3.0 V; I

SET

= 165.33

SR01857

8000

6000

4000

2000

4000

6000

8000

0.25 0.5 0.75

1.25 1.5 1.75

2.25 2.5 2.75

Icp (uA)

COMPLIANCE VOLTAGE (V)

SET

= 206.67

SET

= 165.33

SET

= 103.33

SET

= 51.67

SET

= 51.67

SET

= 103.33

SET

= 165.33

SET

= 206.67

Figure 11.

PHI Charge Pump vs. I

SET

(CP = 00; TEMP = 25

SR01858

8000

6000

4000

2000

4000

6000

8000

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5

Icp (uA)

COMPLIANCE VOLTAGE (V)

+85

+25

Figure 12.

PHI Charge Pump Output vs. Temperature

(CP = 00; V

= 3.0 V; I

SET

= 165.33

SR01859

800

600

400

200

400

600

800

0.25 0.5 0.75

1.25 1.5 1.75

2.25 2.5 2.75

Icp (uA)

COMPLIANCE VOLTAGE (V)

SET

= 206.67

SET

= 165.33

SET

= 103.33

SET

= 51.67

SET

= 51.67

SET

= 103.33

SET

= 165.33

SET

= 206.67

Figure 13.

PHP Charge Pump Output vs. I

SET

(CP = 10; Temp = 25

SR01860

600

400

200

400

600

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5

Icp (uA)

COMPLIANCE VOLTAGE (V)

+85

+25

Figure 14.

PHP Charge Pump Output vs. Temperature

(CP = 10; V

= 3.0 V; I

SET

= 165.33

Philips Semiconductors

Product specification

SA8026

2.5GHz low voltage fractional-N dual frequency
synthesizer

1999 Nov 04

TYPICAL PERFORMANCE CHARACTERISTICS

(Continued)

SR01861

250

200

150

100

150

200

250

0.25 0.5 0.75

1.25 1.5 1.75

2.25 2.5 2.75

Icp (uA)

COMPLIANCE VOLTAGE (V)

SET

= 206.67

SET

= 165.33

SET

= 103.33

SET

= 51.67

SET

= 206.67

SET

= 165.33

SET

= 103.33

SET

= 51.67

Figure 15.

PHP Charge Pump Output vs. I

SET

(CP = 11; Temp = 25

SR01862

200

150

100

150

200

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5

+85

+25

Icp (uA)

COMPLIANCE VOLTAGE (V)

Figure 16.

PHP Charge Pump Output vs. Temperature

(CP = 11; V

= 3.0 V; I

SET

= 165.33

SR01863

Icp (uA)

1500

1000

500

1000

1500

0.25 0.5 0.75

1.0 1.25 1.5 1.75

2.25

2.5 2.75

COMPLIANCE VOLTAGE (V)

SET

= 206.67

SET

= 165.33

SET

= 103.33

SET

= 51.67

SET

= 206.67

SET

= 165.33

SET

= 103.33

SET

= 51.67

Figure 17.

PHPSU Charge Pump Output vs. I

SET

(CP = 01; Temp = 25

SR01864

Icp (uA)

1000

800

600

400

200

400

600

800

1000

0.25 0.5 0.75

1 1.25 1.5 1.75 2

2.25 2.5 2.75

3.25 3.5

COMPLIANCE VOLTAGE (V)

+85

+25

Figure 18.

PHPSU Charge Pump Output vs. Temperature

(CP = 01; V

= 3.0 V; I

SET

= 165.33

SR01870

Icp (uA)

3500

2500

1500

500

1500

2500

3500

0.25

0.5

0.75

1.25

1.5

1.75

2.25

2.5

2.75

COMPLIANCE VOLTAGE (V)

SET

= 206.67

SET

= 165.33

SET

= 103.33

SET

= 51.67

SET

= 206.67

SET

= 165.33

SET

= 103.33

SET

= 51.67

Figure 19.

PHPSU Charge Pump Output vs. I

SET

(CP = 00; Temp = 25

SR01865

3000

Icp (uA)

2000

1000

2000

3000

0.25 0.5 0.75

1.25 1.5 1.75

2.25 2.5 2.75

3.25 3.5

+85

+25

COMPLIANCE VOLTAGE (V)

Figure 20.

PHPSU Charge Pump Output vs. Temperature

(CP = 00; V

= 3.0 V; I

SET

= 165.33

Philips Semiconductors

Product specification

SA8026

2.5GHz low voltage fractional-N dual frequency
synthesizer

1999 Nov 04

TYPICAL PERFORMANCE CHARACTERISTICS

(Continued)

SR01866

150

Icp (uA)

100

150

0.25 0.5 0.75

1.25 1.5 1.75

2.25 2.5 2.75

COMPLIANCE VOLTAGE (V)

SET

= 206.67

SET

= 165.33

SET

= 103.33

SET

= 51.67

SET

= 206.67

SET

= 165.33

SET

= 103.33

SET

= 51.67

Figure 21.

PHA Charge Pump Output vs. I

SET

(CP = 11; Temp = 25

SR01867

100

Icp (uA)

100

0.25 0.5 0.75

1.25 1.5 1.75

2.25 2.5 2.75

3.25 3.5

COMPLIANCE VOLTAGE (V)

+85

+25

Figure 22.

PHA Charge Pump Output vs. Temperature

(CP = 11; V

= 3.0 V; I

SET

= 165.33

SR01869

400

Icp (uA)

300

200

100

200

300

400

0.25

0.5

0.75

1.25

1.5 1.75

2.25

2.5

2.75

COMPLIANCE VOLTAGE (V)

SET

= 206.67

SET

= 165.33

SET

= 103.33

SET

= 51.67

SET

= 206.67

SET

= 165.33

SET

= 103.33

SET

= 51.67

Figure 23.

PHA Charge Pump Output vs. I

SET

(CP = 10; Temp = 25

SR01868

300

Icp (uA)

200

100

200

300

0.25 0.5 0.75

1.25

1.5 1.75

2.25 2.5 2.75

3.25 3.5

COMPLIANCE VOLTAGE (V)

+85

+25

Figure 24.

PHA Charge Pump Output vs. Temperature

(CP = 10; V

= 3.0 V; I

SET

= 165.33

SR01878

10.00

MINIMUM SIGNAL

INPUT

LEVEL

(dBm)

= 5.00 V

= 3.75 V

= 3.00 V

= 2.70 V

5.00

0.00

5.00

10.00

15.00

20.00

25.00

30.00

35.00

40.00

45.00

1300

1500

1700

1900

2100

2300

2500

2700

2900

3100

3300

FREQUENCY (MHz)

Figure 25.

Main Divider Input Sensitivity vs.

Frequency and Supply Voltage

(Temp = 25

SR01879

MINIMUM

SIGNAL

INPUT

LEVEL

(dBm)

0.00

FREQUENCY (MHz)

5.00

10.00

15.00

20.00

25.00

30.00

35.00

40.00

45.00

1300

1500

1700

1900

2100

2300

2500

2700

2900

3100

+85

+25

Figure 26.

Main Divider Input Sensitivity vs.

Frequency and Temperature

= 3.00 V)

Philips Semiconductors

Product specification

SA8026

2.5GHz low voltage fractional-N dual frequency
synthesizer

1999 Nov 04

TYPICAL PERFORMANCE CHARACTERISTICS

(Continued)

SR01880

MINIMUM

SIGNAL

POWER LEVEL

(dBm)

45.00

0.00

5.00

10.00

15.00

20.00

25.00

30.00

35.00

40.00

80 120 160 200 240 280 320 360 400 440 480 520 560

FREQUENCY (MHz)

= 5.00 V

= 3.75 V

= 3.00 V

= 2.70 V

Figure 27.

Auxiliary Divider Input Sensitivity vs.

Frequency and Supply Voltage

(Temp = 25

SR01881

MINIMUM

SIGNAL

POWER LEVEL

(dBm)

0.00

+85

+25

FREQUENCY (MHz)

5.00

10.00

15.00

20.00

25.00

30.00

35.00

40.00

45.00

40 80 120 160 200 240 280 320 360 400 440 480 520 560 600 640

Figure 28.

Auxiliary Divider Input Sensitivity vs.

Frequency and Temperature

(Supply = 3.00 V)

SR01890

MINIMUM

SIGNAL

POWER LEVEL

(dBm)

0.00

FREQUENCY (MHz)

= 5.00 V

= 3.75 V

= 3.00 V

= 2.70 V

Figure 29.

Reference Divider Input Sensitivity vs.

Frequency and Supply Voltage

(Temp = 25

SR01891

MINIMUM

SIGNAL

POWER LEVEL

(dBm)

FREQUENCY (MHz)

Temp = 40

Temp = +85

Temp = +25

Figure 30.

Reference Divider Input Sensitivity vs.

Frequency and Temperature

= 3.00 V)

SR01854

2.5

3.5

4.5

5.5

I T

(mA)

+85

+25

SUPPLY VOLTAGE (V)

Figure 31.

Current Supply Over V

2.5GHz low voltage fractionalN dual frequency
synthesizer

Philips Semiconductors

Product specification

SA8026

1999 Nov 04

Definitions

Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381

Date of release: 11-99

Document order number:

9397 750 06567

Philips

Semiconductors

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

[1]

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

Data sheet status

[1]

Please consult the most recently issued datasheet before initiating or completing a design.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SA8026

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