Document Outline
- GENERAL DESCRIPTION
- FEATURES
- APPLICATIONS
- QUICK REFERENCE DATA
- ORDERING INFORMATION
- PACKAGES
- TSSOP20 PIN DESCRIPTION
- HBCC24 PIN DESCRIPTION
- CHARACTERISTICS
- 1.0 FUNCTIONAL DESCRIPTION
- 2.0 SERIAL PROGRAMMING BUS
- TYPICAL PERFORMANCE CHARACTERISTICS
- TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
- TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
- TYPICAL PERFORMANCE CHARACTERISTICS
Philips
Semiconductors
SA8027
2.5 GHz low voltage, low power
RF fractional-N/IF integer
frequency synthesizer
Product data
Supersedes data of 2001 Jul 18
2001 Aug 21
INTEGRATED CIRCUITS
Philips Semiconductors
Product data
SA8027
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
2
2001 Aug 21
8532244 26947
GENERAL DESCRIPTION
The SA8027 BICMOS device integrates programmable dividers,
charge pumps and phase comparators to implement phase-locked
loops. The device is designed to operate from 3 NiCd cells, in
pocket phones, with low current and nominal 3 V supplies.
The synthesizer operates at VCO input frequencies up to 2.5 GHz.
The synthesizer has fully programmable main, auxiliary and
reference dividers. All divider ratios are supplied via a 3-wire serial
programming bus. The main divider is a fractional-N divider with
programmable integer ratios from 512 to 65535.
Separate power and ground pins are provided to the charge pumps
and digital circuits. The ground pins should be externally connected
to prevent large currents from flowing across the die and causing
damage. V
DDCP
must be equal to or greater than
V
DD
.
The charge pump current (gain) is fully programmable, while I
SET
is
set by an external resistance at the R
SET
pin (refer to section 1.5,
Main Output Charge Pumps and Fractional Compensation
Currents)
.
The phase/frequency detector charge pump outputs allow
for implementing a passive loop filter.
FEATURES
Low phase noise
Low power
Fully programmable main and auxiliary dividers
Programmable Normal & Integral charge pumps outputs
Fast Locking Adaptive mode design
Internal fractional spurious compensation
Hardware and software power down
Split supply for V
DD
and V
DDCP
Loop filter bandwidth programmability
APPLICATIONS
500 to 2500 MHz wireless equipment
Cellular phones (all standards)
WLAN
Portable battery-powered radio equipment.
SR01649
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
17
18
19
20
LOCK
TEST
V
DD
GND
RFin+
RFin
GND
CP
PHP
PHI
GND
CP
PON
STROBE
DATA
CLOCK
REFin+
REFin
R
SET
AUXin
V
DDCP
PHA
10
Figure 1.
TSSOP20 Pin Configuration
13
7
2
3
4
5
6
TOP VIEW
1
8
9
10
11
12
14
15
16
17
18
19
20
21
22
23
24
CLOCK
REFin+
REFin
SR02176
N/C
V
DDPre
GND
GND
Pre
RFin+
RFin
GND
CP
PHP
PHI
GND
PHA
AUXin
N/C
DA
T
A
STROBE
PON
LOCK
TEST
V
DD
CP
V
DDCP
R
SET
Figure 2.
HBCC24 Pin configuration
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
DD
Supply voltage
2.7
3.6
V
V
DDCP
Analog supply voltage
V
DDCP
w
V
DD
2.7
3.6
V
I
DDCP
+I
DD
Supply current
Main and Aux. on
7.7
mA
I
DDCP
+I
DD
Total supply current in power-down mode
1
A
f
VCO
Input frequency
500
2500
MHz
f
AUX
Input frequency
100
550
MHz
f
REF
Crystal reference input frequency
5
40
MHz
f
PC
Maximum phase comparator frequency
4
MHz
T
amb
Operating ambient temperature
40
+85
C
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
SA8027DH
TSSOP20
Plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
SA8027W
HBCC24
Plastic, heatsink bottom chip carrier; 24 terminals; body 4 x 4 x 0.65 mm (Note 1)
SOT564-1
NOTE:
1. The SA8027W will be released for production Q2, 2001.
Philips Semiconductors
Product data
SA8027
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
2001 Aug 21
3
V
DD
SR02357
CLOCK
DATA
STROBE
RF/MAINin+
RF/MAINin
REFin+
REFin
IF/AUXin
TEST
LOAD SIGNALS
ADDRESS DECODER
2BIT SHIFT
REGISTER
22BIT SHIFT
REGISTER
CONTROL
LATCH
LATCH
MAIN DIVIDER
SM
REFERENCE
DIVIDER
2 2 2 2
LATCH
AMP
AMP
15
16
6
5
19
18
17
12
2
LATCH
AUX DIVIDER
PHASE
DETECTOR
PHASE
DETECTOR
FRAC
COMP
PUMP
BIAS
PUMP
CURRENT
SETTING
13
V
DDCP
GND
4
SA
7, 10
3
GND
CP
R
SET
PHP
PHI
LOCK
PHA
14
8
9
1
11
PON
20
LOCK
SELECT
Figure 3.
Block Diagram (TSSOP20)
TSSOP20 PIN DESCRIPTION
SYMBOL
PIN
DESCRIPTION
LOCK
1
Lock detect output
TEST
2
Test (should be either grounded or
connected to V
DD
)
V
DD
3
Digital supply
GND
4
Digital ground
RFin+
5
RF input to main divider
RFin
6
RF input to main divider
GND
CP
7
Charge pump ground
PHP
8
Main normal charge pump
PHI
9
Main integral charge pump
GND
CP
10
Charge pump ground
SYMBOL
PIN
DESCRIPTION
PHA
11
Auxiliary charge pump output
AUXin
12
Input to auxiliary divider
V
DDCP
13
Charge pump supply voltage
R
SET
14
External resistor from this pin to ground
sets the charge pump current
REFin
15
Reference input
REFin+
16
Reference input
CLOCK
17
Programming bus clock input
DATA
18
Programming bus data input
STROBE
19
Programming bus enable input
PON
20
Power down control
Philips Semiconductors
Product data
SA8027
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
2001 Aug 21
4
V
DD
SR02358
CLOCK
DATA
STROBE
RF/MAINin+
RF/MAINin
REFin+
REFin
IF/AUXin
TEST
LOAD SIGNALS
ADDRESS DECODER
2BIT SHIFT
REGISTER
22BIT SHIFT
REGISTER
CONTROL
LATCH
LATCH
MAIN DIVIDER
SM
REFERENCE
DIVIDER
2 2 2 2
LATCH
AMP
AMP
16
17
5
4
20
19
18
11
23
LATCH
AUX DIVIDER
PHASE
DETECTOR
PHASE
DETECTOR
PUMP
BIAS
PUMP
CURRENT
SETTING
14
V
DDCP
GND
pre
3
SA
6, 9
24
GND
CP
R
SET
PHP
PHI
LOCK
PHA
15
7
8
22
10
PON
21
GND
2
V
DDpre
1
LOCK
SELECT
FRAC
COMP
Figure 4.
Block Diagram (HBCC24)
HBCC24 PIN DESCRIPTION
SYMBOL
PIN
DESCRIPTION
V
DDPre
1
Prescaler supply voltage
GND
2
Digital ground
GND
Pre
3
Prescaler ground
RFin+
4
RF input to main divider
RFin
5
RF input to main divider
GND
CP
6
Charge pump ground
PHP
7
Main normal charge pump
PHI
8
Main integral charge pump
GND
CP
9
Charge pump ground
PHA
10
Auxiliary charge pump output
AUXin
11
Input to auxiliary divider
N/C
12
Not connected
N/C
13
Not connected
SYMBOL
PIN
DESCRIPTION
V
DDCP
14
Charge pump supply voltage
R
SET
15
External resistor from this pin to ground
sets the charge pump current
REFin
16
Reference input
REFin+
17
Reference input
CLOCK
18
Programming bus clock input
DATA
19
Programming bus data input
STROBE
20
Programming bus enable input
PON
21
Power down control
LOCK
22
Lock detect output
TEST
23
Test (should be either grounded or
connected to V
DD
)
V
DD
24
Digital supply
Philips Semiconductors
Product data
SA8027
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
2001 Aug 21
5
Limiting values
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
V
DD
Digital supply voltage
0.3
+3.6
V
V
DDCP
Analog supply voltage
0.3
+3.6
V
(V
DDCP
V
DD
)
Difference in voltage between V
DDCP and
V
DD
(V
DDCP
V
DD
)
0.3
+0.9
V
Vi
n
All input pins
0.3
V
DD
+ 0.3
V
V
GND
Difference in voltage between GND
CP
and GND (these pins should be
connected together)
0.3
+0.3
V
T
stg
Storage temperature
55
+125
C
T
amb
Operating ambient temperature
40
+85
C
T
j
Maximum junction temperature
150
C
Thermal characteristics
SYMBOL
PARAMETER
VALUE
UNIT
R
th ja
Thermal resistance from junction to ambient in free air
135
K/W
Philips Semiconductors
Product data
SA8027
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
2001 Aug 21
6
CHARACTERISTICS
V
DDCP
= V
DD
= +3.0 V,
T
amb
= +25
C;
unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
V
DD
Digital supply voltage
2.7
3.6
V
V
DDCP
Analog supply voltage
V
DDCP
w
V
DD
2.7
3.6
V
I
Total
Synthesizer operational supply current
V
DD
= +3.0 V
(with main and aux on)
7.7
mA
I
Standby
Total supply current in power-down mode
logic levels 0 or V
DD
1
A
RFin main divider input
f
VCO
VCO input frequency
500
2500
MHz
V
RFin
AC-coupled input signal level
R
in
(external) = R
s
= 50
;
single-ended drive;
18
0
dBm
g
max. limit is indicative
@ 500 to 2500 MHz
80
632
mV
PP
Z
RFin
Input impedance (real part)
f
VCO
= 2.4 GHz
300
C
RFin
Typical pin input capacitance
f
VCO
= 2.4 GHz
1
pF
N
main
Main divider ratio
512
65535
f
PCmax
Maximum loop comparison frequency
indicative, not tested
4
MHz
AUX divider input
f
AUXin
Input frequency range
100
550
MHz
V
AC coupled input signal level
R
in
(external) = R
S
= 50
;
15
0
dBm
V
AUXin
AC-coupled input signal level
in
(
)
S
max. limit is indicative
112
632
mV
PP
Z
AUXin
Input impedance (real part)
f
VCO
= 500 MHz
3.9
k
C
AUXin
Typical pin input capacitance
f
VCO
= 500 MHz
0.5
pF
N
AUX
Auxiliary division ratio
128
16383
Reference divider input
f
REFin
Input frequency range from TCXO
5
40
MHz
V
REFin
AC-coupled input signal level
single-ended drive;
max. limit is indicative
360
1300
mV
PP
Z
REFin
Input impedance (real part)
f
REF
= 20 MHz
10
k
C
REFin
Typical pin input capacitance
f
REF
= 20 MHz
1
pF
R
REF
Reference division ratio
SA = SM = "000"
4
1023
Charge pump current setting resistor input
R
SET
External resistor from pin to ground
6
7.5
15
k
V
SET
Regulated voltage at pin
R
SET
= 7.5 k
1.22
V
Charge pump outputs; R
SET
= 7.5 k
I
CP
Charge pump current ratio to I
SET
1
Current gain = I
PH
/I
SET
15
+15
%
I
MATCH
Sink-to-source current matching
V
PH
= 1/2 V
DDCP
10
+10
%
I
ZOUT
Output current variation versus V
PH
2
V
PH
in compliance range
10
+10
%
I
LPH
Charge pump off leakage current
V
PH
= 1/2 V
DDCP
10
+10
nA
V
PH
Charge pump voltage compliance
0.6
V
DDCP
0.7
V
Philips Semiconductors
Product data
SA8027
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
2001 Aug 21
7
CHARACTERISTICS (continued)
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Phase noise (condition R
SET
= 7.5 k
, CP = 00)
Synthesizer's contribution to close-in phase noise
of 900 MHz RF signal at 1 kHz offset.
GSM
f
REF
= 13MHz, TCXO,
90
dBc/Hz
L
Synthesizer's contribution to close-in phase noise
of 1800 MHz RF signal at 1 kHz offset.
f
REF
= 13MHz, TCXO,
f
COMP
= 1MHz
indicative, not tested
83
dBc/Hz
L
(f)
Synthesizer's contribution to close-in phase noise
of 800 MHz RF signal at 1 kHz offset.
TDMA
f
REF
= 19.44MHz, TCXO,
85
dBc/Hz
Synthesizer's contribution to close-in phase noise
of 2100 MHz RF signal at 1 kHz offset.
f
REF
= 19.44MHz, TCXO,
f
COMP
= 240kHz
indicative, not tested
77
dBc/Hz
Interface logic input signal levels
V
IH
HIGH level input voltage
0.7*V
DD
V
DD
+0.3
V
V
IL
LOW level input voltage
0.3
0.3*V
DD
V
I
LEAK
Input leakage current
logic 1 or logic 0
0.5
+0.5
A
Lock detect output signal (in push/pull mode)
V
OL
LOW level output voltage
I
sink
= 2 mA
0.4
V
V
OH
HIGH level output voltage
I
source
= 2 mA
V
DD
0.4
V
NOTES:
1. I
SET
+
V
SET
R
SET
bias current for charge pumps
2. The relative output current variation is defined as:
D
I
OUT
I
OUT
+
2
(I
2
*
I
1
)
|I
2
)
I
1
|
; with I
1
@ V
1
+
0.6 V, I
2
@ V
2
+
V
DDCP
0.7 V (See Figure 5.)
I2
I1
I2
I1
V1
V2
CURRENT
V
PH
SR00602
I
ZOUT
VOLTAGE
Figure 5.
Relative Output Current Variation
Philips Semiconductors
Product data
SA8027
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
2001 Aug 21
8
1.0
FUNCTIONAL DESCRIPTION
1.1
Main Fractional-N divider
The RFin inputs drive a pre-amplifier to provide the clock to the first
divider stage. For single ended operation, the signal should be fed to
one of the inputs while the other one is AC grounded. The
pre-amplifier has a high input impedance, dominated by pin and pad
capacitance. The circuit operates with signal levels from 18 dBm to
0 dBm, and at frequencies as high as 2.5 GHz. The divider consists
of a fully programmable bipolar prescaler followed by a CMOS
counter. Total divide ratios range from 512 to 65535.
The fractional modulus is selected by programming FMOD in the
A word. There are 2 modulus to select from: when FMOD = 0,
modulo 8 is selected; when FMOD = 1, modulo 5 is selected.
At the completion of a main divider cycle, a main divider output
pulse is generated which will drive the main phase comparator. Also,
the fractional accumulator is incremented by the value of NF. The
accumulator works with modulo set by FMOD. When the
accumulator overflows, the overall division ratio N will be increased
by 1, to N + 1. The average division ratio over modulo main divider
cycles (either 5 or 8) will be
Nfrac
+
N
)
NF
f
MOD
The output of the main divider will be modulated with a fractional
phase ripple. The phase ripple is proportional to the contents of the
fractional accumulator and is nulled by the fractional compensation
charge pump. Thus, f
VCO
= f
comp
* N
)
NF
f
MOD
.
The reloading of a new main divider ratio is synchronized to the
state of the main divider to avoid introducing a phase disturbance.
1.2
Auxiliary divider
The AUXin input drives a pre-amplifier to provide the clock to the
first divider stage. The pre-amplifier has a high input impedance,
dominated by pin and pad capacitance. The circuit operates with
signal levels from 15 dBm to 0 dBm (112 to 632 mVpp), and at
frequencies as high as 550 MHz. The divider consists of a fully
programmable bipolar prescaler followed by a CMOS counter. Total
divide ratios range from 128 to 16383.
1.3
Reference divider
The reference divider consists of a divider with programmable
values between 4 and 1023 followed by a three bit binary counter.
The 3 bit SM (SA) register (see Figure 6) determines which one of
the 5 output pulses are selected as the main (auxiliary) phase
detector input, thus allowing the main PFD and auxiliary PFD to
operate at different frequencies.
1.4
Phase detector (see Figure 7)
The reference and main (aux) divider outputs are connected to a
phase/frequency detector that controls the charge pump. The pump
current is set by an external resistor in conjunction with control bits
CP0 and CP1 in the C-word (see Table 1). The dead zone (caused
by finite time taken to switch the current sources on or off) is
cancelled by forcing the pumps ON for a minimum time (
) at every
cycle (backlash time) providing improved linearity.
SR01415
DIVIDE BY R
/2
/2
/2
/2
REFERENCE
INPUT
SM="000"
SM="001"
SM="010"
SM="011"
SM="100"
SA="100"
SA="011"
SA="010"
SA="001"
SA="000"
TO
MAIN
PHASE
DETECTOR
TO
AUXILIARY
PHASE
DETECTOR
Figure 6.
Reference Divider
Philips Semiconductors
Product data
SA8027
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
2001 Aug 21
9
SR01451
R
X
P
N
REF DIVIDER
AUX/MAIN
DIVIDER
D
Q
CLK
"1"
R
D
R
CLK
"1"
X
Q
N
P
V
CC
I
PH
GND
PTYPE
CHARGE PUMP
NTYPE
CHARGE PUMP
R
f
REF
f
REF
I
PH
Figure 7.
Phase Detector Structure with Timing
Philips Semiconductors
Product data
SA8027
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
2001 Aug 21
10
1.5
Main Output Charge Pumps and Fractional
Compensation Currents (see Figure 8)
The main charge pumps on pins PHP and PHI are driven by the
main phase detector and the charge pump current values are
determined by the current at pin R
SET
in conjunction with bits CP0,
CP1 in the C-word (see Table 1). The main charge pumps will enter
speed up mode after the A-word is set and strobe goes High. When
strobe goes Low, charge pump will exit speed up mode. The
fractional compensation is derived from the current at R
SET
, the
contents of the fractional accumulator (FRD) and by the program
value of the FDAC. The timing for the fractional compensation is
derived from the main divider.
1.6
Principle of Fractional Compensation
The fractional compensation is designed into the circuit as a means
of reducing or eliminating fractional spurs that are caused by the
fractional phase ripple of the main divider. If I
COMP
is the
compensation current and I
PUMP
is the pump current, then for each
charge pump:
I
PUMP_TOTAL
= I
PUMP
+ I
COMP
.
The compensation is done by sourcing a small current, I
COMP
, see
Figure 9, that is proportional to the fractional error phase. For proper
fractional compensation, the area of the fractional compensation
current pulse must be equal to the area of the fractional charge
pump ripple. The width of the fractional compensation pulse is fixed
to 128 VCO cycles, the amplitude is proportional to the fractional
accumulator value and is adjusted by FDAC values (bits FC70 in
the B-word). The fractional compensation current is derived from the
main charge pump in that it follows all the current scaling through
external resistor setting, R
SET
, programming or speed-up operation.
For a given charge pump,
I
COMP
= ( I
PUMP
/ 128 ) * ( FDAC / 5*128) * FRD
FRD is the fractional accumulator value and is automatically
updated.
The theoretical values for FDAC are: 128 for FMOD = 1 (modulo 5)
and 80 for FMOD = 0 (modulo 8).
SR02359
REFERENCE R
MAIN M DIVIDE RATIO
CHARGE PUMP OUTPUT
ACCUMULATOR VALUE (FRD)
FRACTIONAL COMPENSATION
CURRENT (I
COMP
)
I
PUMPTOTAL
N
N
N+1
N
N+1
2
4
1
3
0
PULSE
WIDTH
MODULATION
PULSE LEVEL
MODULATION
mA
A
GRAPHS NOT TO SCALE.
NOTE: For a proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the charge pump output.
Figure 8.
Waveforms for NF = 2 Modulo 5
fraction =
2
/
5
SR01800
f
RF
MAIN DIVIDER
FRACTIONAL
ACCUMULATOR
f
REF
I
COMP
I
PUMP
LOOP FILTER
& VCO
Figure 9.
Current Injection Concept
Philips Semiconductors
Product data
SA8027
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
2001 Aug 21
11
1.7
Charge Pumps
The PHP and PHI charge pumps are driven by the main phase
detector, while the PHA charge pump is driven by the auxiliary
phase detector. The I
SET
value (refer to Table 1) is determined by
the external resistor attached to the R
SET
pin.
The charge pump, by default, will automatically go into speed-up
mode (which can deliver up to 15*I
SET
for PHP_SU, and 36*I
SET
for
PHI), based on the strobe pulse width following the A word, to
reduce switching speed for large tuning voltage steps (i.e., large
frequency steps). Figure 10 shows the recommended passive loop
filter configuration. Note: This charge pump architecture eliminates
the need for added active switches and reduces external component
count. Furthermore, the programmable charge pump gains provide
some programmability to the loop filter bandwidth.
The duration of speed-up mode is determined by the strobe pulse
width following the A word. Recommended optimal strobe width is
equal to the total loop filter capacitance charge time from state 1 to
state 2. The strobe width must not exceed this charge time. The
strobe width is controlled by the CPU (
number of clock cycles).
In addition, charge pumps will stay in speed-up mode continuously
while Tspu = 1 (in D word). The speed-up mode can also be
disabled by programming T
dis-spu
= 1 (in D word).
SR02356
VCO
C3
C2
R2
C1
R1
PHP[PHPSU]
PHI
Figure 10.
Typical passive 3-pole loop filter
Table 1. Main and auxiliary charge pump currents
CP1
CP0
I
PHA
I
PHP
I
PHPSU
I
PHI
0
0
1.5xl
SET
3xI
SET
15xl
SET
36xl
SET
0
1
0.5xl
SET
1xl
SET
5xl
SET
12xl
SET
1
0
1.5xl
SET
3xl
SET
15xl
SET
0
1
1
0.5xl
SET
1xl
SET
5xl
SET
0
NOTES:
1. I
SET
= V
SET
/R
SET
: bias current for charge pumps.
2. CP1 is used to disable the PHI pump, I
PHPSU
is the total current
at pin PHP during speed up condition.
1.8
Lock Detect
The output LOCK maintains a logic `1' when the auxiliary phase
detector (AND/ORed) with the main phase detector indicates a lock
condition. The lock condition for the main and auxiliary synthesizers
is defined as a phase difference of less than
"
1 period of the
frequency at the input REF
in+,
. One counter can fulfill the lock
condition when the other counter is powered down. Out of lock
(logic `0') is indicated when both counters are powered down.
1.9
Power-down mode
The power-down signal can be either hardware (PON) or software
(PD). The PON signal is exclusively ORed with the PD bits in
B-word. If PON = 0, then the part is powered up when PD = 1. PON
can be used to invert the polarity of the software bit PD. When the
synthesizer is reactivated after power-down, the main and reference
dividers are synchronized to avoid possibility of random phase
errors on power-up.
Philips Semiconductors
Product data
SA8027
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
2001 Aug 21
12
2.0
SERIAL PROGRAMMING BUS
The serial input is a 3-wire input (CLOCK, STROBE, DATA) to
program all counter divide ratios, fractional compensation DAC,
selection and enable bits. The programming data is structured into
24 bit words; each word includes 2 or 3 address bits. Figure 11
shows the timing diagram of the serial input. When the STROBE
goes active HIGH, the clock is disabled and the data in the shift
register remains unchanged. Depending on the address bits, the
data is latched into the selected working registers or temporary
registers. In order to fully program the synthesizer, 3 words must be
sent: C, B, and A, in that order. A typical programming sequence is
illustrated in Figure 12. Table 2 shows the format and the contents of
each word. The D word is used for testing purposes and should be
initially set to 0 for normal operation. When sending the B-word, data
bits FC70 for the fractional compensation DAC are not loaded
immediately. Instead they are stored in temporary registers. Only
when the A-word is loaded, these temporary registers are loaded
together with the main divider ratio.
2.1
Serial bus timing characteristics (see Figure 11)
V
DD
= V
DDCP
=+3.0 V; T
amb
= +25
C unless otherwise specified.
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Serial programming clock; CLK
t
r
Input rise time
10
40
ns
t
f
Input fall time
10
40
ns
T
cy
Clock period
100
ns
Enable programming; STROBE
t
START
Delay to rising clock edge
40
ns
t
W
Minimum inactive pulse width
1/f
COMP
ns
t
SU;E
Enable set-up time to next clock edge
20
ns
Register serial input data; DATA
t
SU;DAT
Input data to clock set-up time
20
ns
t
HD;DAT
Input data to clock hold time
20
ns
Application information
SR01417
CLK
DATA
STROBE
LSB
ADDRESS
t
SU;DAT
t
HD;DAT
t
f
t
w
t
r
t
SU;E
t
START
T
cy
MSB
0
Figure 11.
Serial Bus Timing Diagram
Philips Semiconductors
Product data
SA8027
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
2001 Aug 21
13
SR02360
POWERON
PROGRAM C WORD
SELECT SA, SM
SET CHARGE PUMP GAIN
SET AUX DIVIDER
PROGRAM B WORD
SELECT FDAC
SET POWER-UP OPTION
SET LOCK DETECT
SET REF DIVIDER
PROGRAM A WORD
SELECT MAIN DIVIDER
SET FRACTIONAL-N
SET FMOD
READY TO OPERATE
CHANGE
MAIN
FREQUENCY
CHANGE
FDAC
CHANGE
AUX
FREQUENCY
POWER
DOWN
POWER
UP
POWER
OFF
Y
Y
Y
N
N
N
N
N
PROGRAM C WORD
PROGRAM B WORD
PROGRAM B WORD
Y
PROGRAM D WORD
SET DEFAULT
Y
PROGRAM A WORD
Figure 12.
Typical programming sequence
Philips Semiconductors
Product data
SA8027
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
2001 Aug 21
14
Data format
Table 2. Format of programmed data
Last In
MSB
Serial Programming Format
First In LSB
p23
p22
p21
p20
../..
../..
p1
p0
Table 3. A word, length 24 bits
Last In
MSB
LSB
First In
Address
fmod
Fractional-N
Main Divider ratio
Spare
0
0
fmod
NF2
NF1
NF0
N15
N14
N13
N12
N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
N0
SK1
SK2
Default
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
1
0
0
0
0
0
0
A word address
Fixed to 00.
Fractional Modulus select
fmod = 0 is modulo 8; fmod = 1 is modulo 5.
Fractional-N Increment
Fractional-N Increment values 000 to 111 (0 to 7). NF is a 3-bit word.
N-Divider
N0..N15, Main divider values 512 to 65535 allowed for divider ratio.
Spare
SK1, SK2 must be set to 0.
Table 4. B word, length 24 bits
Address
Reference Divider
Lock
PD
FDAC (Fractional Compensation DAC)
0
1
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
L1
L0
Main
Aux
FC7
FC6
FC5
FC4
FC3
FC2
FC1
FC0
Default
0
0
0
1
0
1
0
0
0
1
0
0
1
1
0
1
0
1
0
0
0
0
B word address
Fixed to 01
REF-Divider
R0..R9, Reference divider values 4 to 1023 allowed for divider ratio. R <9:0>.
Lock detect output
L1 L0
0 0
Combined main, aux. lock detect signal present at the LOCK pin (push/pull).
0 1
Combined main, aux, lock detect signal present at the LOCK pin (open drain).
1 0
Main lock detect signal present at the LOCK pin (push/pull).
1 1
Auxiliary loop lock detect signal present at the LOCK pin (push/pull).
When auxiliary loop and main loop are in power down mode, the lock indicator is low.
Power down (PD)
PON pin is tied to GND
Main = 1: power-on to Main PLL. Main = 0: power-down to Main PLL.
Aux = 1: power-on to Aux PLL. Aux = 0: power-down to Aux PLL.
PON pin is tied to V
DD
Main = 0: power-on to Main PLL. Main = 1: power-down to Main PLL.
Aux = 0: power-on to Aux PLL. Aux = 1: power-down to Aux PLL.
Fractional Compensation
FC7..0 Fractional Compensation charge pump current DAC, values 0 to 255.
Table 5. C word, length 24 bits
Address
Auxiliary Divider
CP
SM
SA
1
0
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CP1
CP0
SM2
SM1
SM0
SA2
SA1
SA0
Default
0
0
0
0
0
1
1
1
0
0
1
0
1
0
1
1
0
0
0
0
0
0
C word address
Fixed to 10
A-Divider
A0..A13, Auxiliary divider values 128 to 16383 allowed for divider ratio.
Charge pump current Ratio
CP1, CP0: Charge pump current ratio, see Table 1.
Main comparison select
SM
comparison divider select for main phase detector.
Aux comparison select
SA
Comparison divider select for auxiliary phase detector.
Table 6. D word, length 24 bits
Address
Synthesizer Test Bits
1
1
0
T
dis-spu
Tspu
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D word address
Fixed to 110.
T
dis-spu
= 1
Speed-up mode disabled.
NOTE: All other test bits must be set to 0 for normal operation.
T
spu
= 1
Speed-up mode always on.
NOTE: All other test bits must be set to 0 for normal operation.
Philips Semiconductors
Product data
SA8027
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
2001 Aug 21
15
TYPICAL PERFORMANCE CHARACTERISTICS
SR02331
COMPLIANCE VOLTAGE(V)
Icp (uA)
3000
2000
1000
0
1000
2000
3000
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
I
SET
= 204
A
I
SET
= 164
A
I
SET
= 81
A
I
SET
= 164
A
I
SET
= 204
A
I
SET
= 81
A
Figure 13.
PHI Charge Pump Output vs. I
SET
(CP = 01_12x; Temp = 25
_
C)
SR02332
2000
1000
0
1000
2000
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
COMPLIANCE VOLTAGE (V)
Icp (uA)
3000
3000
40
C
+25
C
+85
C
Figure 14.
PHI Charge Pump Output vs. Temperature
(CP = 01_12x; V
DD
= 3.0 V; I
SET
= 164
m
A)
SR02333
8000
6000
4000
2000
0
2000
4000
6000
8000
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
I
SET
= 164
A
I
SET
= 204
A
I
SET
= 204
A
I
SET
= 164
A
I
SET
= 81
A
COMPLIANCE VOLTAGE (V)
Icp (uA)
I
SET
= 81
A
Figure 15.
PHI Charge Pump Output vs. I
SET
(CP = 00_36x; Temp = 25
_
C)
SR02334
8000
6000
4000
2000
0
2000
4000
6000
8000
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
Icp (uA)
COMPLIANCE VOLTAGE (V)
40
C
+25
C
+85
C
Figure 16.
PHI Charge Pump Output vs. Temperature
(CP = 00_36x; V
DD
= 3.0 V; I
SET
= 164
m
A)
SR02335
800
600
400
200
0
200
400
600
800
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
COMPLIANCE VOLTAGE
I
SET
= 204
A
I
SET
= 164
A
I
SET
= 81
A
I
SET
= 204
A
Icp (uA)
I
SET
= 164
A
I
SET
= 81
A
Figure 17.
PHP Charge Pump Output vs. I
SET
(CP = 10_3x; V
DD
= 3.0 V; Temp = 25
_
C)
SR02336
Icp (uA)
COMPLIANCE VOLTAGE (V)
600
400
200
0
200
400
600
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
800
800
40
C
+25
C
+85
C
Figure 18.
PHP Charge Pump Output vs. Temperature
(CP = 10_3x; V
DD
= 3.0 V; I
SET
= 164
m
A)
Philips Semiconductors
Product data
SA8027
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
2001 Aug 21
16
TYPICAL PERFORMANCE CHARACTERISTICS
(Continued)
SR02337
250
200
150
100
50
0
50
100
150
200
250
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
I
SET
= 204
A
I
SET
= 164
A
I
SET
= 81
A
I
SET
= 204
A
I
SET
= 164
A
I
SET
= 81
A
COMPLIANCE VOLTAGE (V)
Icp (uA)
Figure 19.
PHP Charge Pump Output vs. I
SET
(CP = 11_1x; V
DD
= 3.0 V; Temp = 25
_
C)
SR02338
Icp (uA)
COMPLIANCE VOLTAGE (V)
200
150
100
50
0
50
100
150
200
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
40
C
+25
C
+85
C
250
250
Figure 20.
PHP Charge Pump Output vs. Temperature
(CP = 11_1x; V
DD
= 3.0 V; I
SET
= 164
m
A)
SR02339
1500
1000
500
0
500
1000
1500
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
I
SET
= 204
A
I
SET
= 81
A
I
SET
= 204
A
I
SET
= 164
A
I
SET
= 81
A
COMPLIANCE VOLTAGE (V)
Icp (uA)
I
SET
= 164
A
Figure 21.
PHPSU Charge Pump Output vs. I
SET
(CP = 01_5x; V
DD
= 3.0 V; Temp = 25
_
C)
SR02340
Icp (uA)
COMPLIANCE VOLTAGE (V)
1000
500
0
500
1000
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
40
C
+25
C
+85
C
1500
1500
Figure 22.
PHPSU Charge Pump Output vs. Temperature
(CP = 01_5x; V
DD
= 3.0 V; I
SET
= 164
m
A)
SR02341
Icp (uA)
COMPLIANCE VOLTAGE (V)
4000
3000
2000
1000
0
1000
2000
3000
4000
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
I
SET
= 204
A
I
SET
= 81
A
I
SET
= 204
A
I
SET
= 164
A
I
SET
= 81
A
I
SET
= 164
A
Figure 23.
PHPSU Charge Pump Output vs. I
SET
(CP = 00_15x; V
DD
= 3.0 V; Temp = 25
_
C)
SR02342
Icp (uA)
COMPLIANCE VOLTAGE (V)
3000
2000
1000
0
1000
2000
3000
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
40
C
+25
C
+85
C
4000
4000
Figure 24.
PHPSU Charge Pump Output vs. Temperature
(CP = 00_15x; V
DD
= 3.0 V; I
SET
= 164
m
A)
Philips Semiconductors
Product data
SA8027
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
2001 Aug 21
17
TYPICAL PERFORMANCE CHARACTERISTICS
(Continued)
SR02343
Icp (uA)
COMPLIANCE VOLTAGE (V)
150
100
50
0
50
100
150
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
I
SET
= 204
A
I
SET
= 81
A
I
SET
= 204
A
I
SET
= 164
A
I
SET
= 81
A
I
SET
= 164
A
Figure 25.
PHA Charge Pump Output vs. I
SET
(CP = 11_0.5x; Temp = 25
_
C)
SR02344
Icp (uA)
COMPLIANCE VOLTAGE (V)
100
50
0
50
100
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
150
100
40
C
+25
C
+85
C
Figure 26.
PHA Charge Pump Output vs. Temperature
(CP = 11_0.5x; V
DD
= 3.0 V; I
SET
= 164
m
A)
SR02346
Icp (uA)
400
300
200
100
0
100
200
300
400
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
I
SET
= 204
A
I
SET
= 81
A
I
SET
= 204
A
I
SET
= 164
A
I
SET
= 81
A
I
SET
= 164
A
COMPLIANCE VOLTAGE (V)
Figure 27.
PHA Charge Pump Output vs. I
SET
(CP = 10_1.5x; V
DD
= 3.0 V; Temp = 25
_
C)
SR02345
Icp (uA)
COMPLIANCE VOLTAGE (V)
300
200
100
0
100
200
300
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
40
C
+25
C
+85
C
400
400
Figure 28.
PHA Charge Pump Output vs. Temperature
(CP = 10_1.5x; V
DD
= 3.0 V; I
SET
= 164
m
A)
SR02347
51
48
45
42
39
36
33
30
27
24
21
18
15
12
9
6
3
0
0
100
200
300
400
500
600
700
800
900
1000
1
100
1200
1300
1400
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
2.6V
3.0V
3.6V
INPUT FREQUENCY (MHz)
MINIMUM
SIGNAL
INPUT
LEVEL
(dBm)
Figure 29.
Main Divider Input Sensitivity vs.
Frequency and Supply Voltage
(Temp = 25
_
C; I
SET
= 164
A; NF = 0; MOD = 8; N = 853)
SR02348
MINIMUM
SIGNAL
INPUT
LEVEL
(dBm)
INPUT FREQUENCY (MHz)
51
48
45
42
39
36
33
30
27
24
21
18
15
12
9
6
3
0
0
100
200
300
400
500
600
700
800
900
1000
1
100
1200
1300
1400
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
40
C
+25
C
+85
C
Figure 30.
Main Divider Input Sensitivity vs.
Frequency and Temperature
(I
SET
= 164
A; NF = 0; MOD = 8; N = 853; V
DD
= 3.0 V)
Philips Semiconductors
Product data
SA8027
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
2001 Aug 21
18
TYPICAL PERFORMANCE CHARACTERISTICS
(Continued)
SR02349
MINIMUM
SIGNAL
INPUT
LEVEL
(dBm)
FREQUENCY (MHz)
42
39
36
33
30
27
24
21
18
15
12
9
6
3
0
0
50
100
150
200
250
300
350
400
450
500
550
600
650
700
750
800
850
900
950
2.6V
3.0V
3.6V
Figure 31.
Auxiliary Divider Input Sensitivity vs.
Frequency and Supply Voltage
(Temp = 25
_
C; I
SET
= 164
A; Divider Ratio = 213)
SR02350
MIMINUM
SIGNAL
INPUT
LEVEL
(dBm)
FREQUENCY (MHz)
42
39
36
33
30
27
24
21
18
15
12
9
6
3
0
0
50
100
150
200
250
300
350
400
450
500
550
600
650
700
750
800
850
900
950
40
C
+25
C
+85
C
Figure 32.
Auxiliary Divider Input Sensitivity vs.
Frequency and Temperature
(I
SET
= 164
A; Divider Ratio = 213; V
DD
= 3.0 V)
SR02351
MINIMUM
SIGNAL
INPUT
LEVEL
(dBm)
FREQUENCY (MHz)
30
27
24
21
18
15
12
9
6
3
0
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
2.6V
3.0V
3.6V
Figure 33.
Reference Divider Input Sensitivity vs.
Frequency and Supply Voltage
(Temp = 25
_
C; I
SET
= 164
A; Divider Ratio = 682)
SR02352
MINIMUM
SIGNAL
INPUT
LEVEL
(dBm)
FREQUENCY (MHz)
30
27
24
21
18
15
12
9
6
3
0
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
40
C
+25
C
+85
C
Figure 34.
Reference Divider Input Sensitivity vs.
Frequency and Temperature
(I
SET
= 164
A; Divider Ratio = 682; V
DD
= 3.0 V)
SR02353
T
O
T
A
L
CURRENT
(mA)
SUPPLY VOLTAGE (V)
6.00
6.50
7.00
7.50
8.00
8.50
9.00
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
40
C
+25
C
+85
C
Figure 35.
Total Supply Current vs. Temperature
(I
SET
= 164
A)
Philips Semiconductors
Product data
SA8027
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
2001 Aug 21
19
TSSOP20:
plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
Philips Semiconductors
Product data
SA8027
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
2001 Aug 21
20
HBCC24:
plastic, heatsink bottom chip carrier; 24 terminals; body 4 x 4 x 0.65 mm
SOT564-1
Philips Semiconductors
Product data
SA8027
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
2001 Aug 21
21
NOTES
Philips Semiconductors
Product data
SA8027
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
2001 Aug 21
22
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Contact information
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Koninklijke Philips Electronics N.V. 2001
All rights reserved. Printed in U.S.A.
Date of release: 09-01
Document order number:
9397 750 08745
Philips
Semiconductors
Data sheet status
[1]
Objective data
Preliminary data
Product data
Product
status
[2]
Development
Qualification
Production
Definitions
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
This data sheet contains data from the preliminary specification. Supplementary data will be
published at a later date. Philips Semiconductors reserves the right to change the specification
without notice, in order to improve the design and supply the best possible product.
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply.
Changes will be communicated according to the Customer Product/Process Change Notification
(CPCN) procedure SNW-SQ-650A.
Data sheet status
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
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