1998 Feb 05

Philips Semiconductors

Objective specification

Multimedia video data acquisition circuit

SAA5284

FEATURES

High performance multi-standard data slicer

Intercast

(Intel Corporation) compatible

Teletext (WST, Chinese teletext) (625 lines)

Teletext (US teletext, NABTS and MOJI) (525 lines)

Wide Screen Signalling (WSS), Video Programming
Signal (VPS)

Closed Caption (Europe, US)

Data broadcast, PDC (packet 30 and 31)

User programmable data format (programmable framing
code)

2 kbytes data cache on-chip to avoid data loss and
reduce host CPU overhead

Filtering of packets 30 and 31 WST/NABTS

Choice of clock frequencies, direct-in clock or crystal
oscillator

Parallel interface, Motorola, Intel and digital video bus

C-bus control

Data transport by digital video bus

Choice of programmable interrupt, DMA or polling
driven

Data type selectable video line by video line, with
Vertical Blanking Interval and Full Field mode

Single IC with few external components and small
footprint QFP44 package

Optimized for EMC.

GENERAL DESCRIPTION

The SAA5284 is a Vertical Blanking Interval (VBI) and Full
Field (FF) video data acquisition device tailored for
application on PC add-in cards, PC mother-boards, set-top
boxes and as a SAA5250 replacement. The IC in
combination with a range of software modules will acquire
most existing formats of broadcast VBI and FF data.

These associated software modules are available under
licence. Scope is provided for acquiring some as yet
unspecified formats. The SAA5284 incorporates all the
data slicing, parallel interface, data filtering and control
logic. It is controlled either by a parallel interface or
I

C-bus. It can output ASCII VBI data as pixels on the

digital video bus where no parallel port is available. It is
available in a QFP44 package.

QUICK REFERENCE DATA

Note

1. Selectable: 12, 13.5, 15 or 16 MHz.

ORDERING INFORMATION

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

supply voltage

4.5

5.0

5.5

supply current

sync(p-p)

sync voltage (peak-to-peak value)

0.1

0.3

0.6

i(CVBS)(p-p)

input voltage on pin CVBS0 and CVBS1
(peak-to-peak value)

0.7

1.0

1.4

xtal

crystal frequency; see note 1

12.0

MHz

amb

operating ambient temperature

+70

TYPE NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

SAA5284GP

QFP44

plastic quad flat package; 44 leads (lead length 2.35 mm);
body 14

2.2 mm

SOT205-1

1998 Feb 05

Philips Semiconductors

Objective specification

Multimedia video data acquisition circuit

SAA5284

MAIN FUNCTIONAL BLOCKS

1. Input clamp and sync separator

2. Analog-to-digital converter

3. Multi-standard data slicer and clock regenerator

4. Packet filtering; (8 and 4) Hamming correction

5. On-chip data cache

6. Line selectable data type

7. 12, 13.5, 15 and 16 MHz clock or oscillator options

8. FIFO access to data

9. Interrupt and DMA support

10. Multi-standard parallel interface

11. I

C-bus interface

12. Power-on reset.

Figure 1 shows a block diagram of the SAA5284.

BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

MGG740

ANALOG

SWITCH

SAA5284

MULTI-STANDARD

HOST INTERFACE

C-BUS

INTERFACE

400 kHz

SLAVE

FIFO

PACKET BUFFER AND

FRONT END CONTROL

REGISTERS

PACKET

FILTERING (e.g.

WST packets

30/31)

ANALOG

VIDEO TO

DATA BYTE

CONVERTER

(DATA

DEMODULATOR)

OSCILLATOR

AND TIMING

OSCOUT

OSCGND

OSCIN

PACKET BUFFER RAM

2 kbyte

(45 packets)

SDA

SCL

30 to 28

20 to 27

(1)

VDDA VSSA VDDX VDDD VSSD3

RESET

VPOIN0

HREF

VPOIN1

LLC

LLC2

(1)

DMACK

(1)

DMARQ

CVBS0

CVBS1

VSSD1

VSSD2

data path

control

IREF

BLACK

D7 to D0

(1)

A2 to A0

(1)

RDY

(1)

SEL1

SEL0

INT

CS1

DENB

CS0

(1) Multi-functional pins, see Chapter 7.

1998 Feb 05

Philips Semiconductors

Objective specification

Multimedia video data acquisition circuit

SAA5284

PINNING INFORMATION

7.1

Pinning

7.2

Pin description

Table 1

QFP44 package

The IC has a total of 44 pins; many of these are multi-functional due to the multiple host block modes of operation.

SYMBOL

PIN

I/O

DESCRIPTION

RESET

reset IC

HREF

video horizontal reference signal (digital video mode only)

SDA

I/O

serial data port for I

C-bus, open-drain

SCL

serial clock input for I

C-bus

DENB

data enable bar (for external buffers)

DDX

+5 V supply

OSCOUT

oscillator output

OSCIN

oscillator input

Fig.2 Pin configuration.

(1) Multi-functional pin.

handbook, full pagewidth

SAA5284

MGG739

(1)

RDY

(1)

INT

(1)

RESET

HREF

SDA

SCL

DENB

VDDX

OSCIN

OSCGND

SEL1

(1)

LLC2

LLC

DDD

SSD3

VPOIN1

VPOIN0

DMARQ

CS0

(1)

CS1

DMACK

(1)

I REF

CVBS1

CVBS0

DDA

SSA

SSD1

(1)

BLACK

SSD2

OSCOUT

SEL0

1998 Feb 05

Philips Semiconductors

Objective specification

Multimedia video data acquisition circuit

SAA5284

Note

1. These pins have two functions, depending on the interface mode.

OSCGND

oscillator ground

SEL0

parallel interface format select 0

SEL1

parallel interface format select 1

BLACK

I/O

video black level storage; connected to V

SSA

via 100 nF capacitor

REF

reference current input; connected to V

SSA

via 27 k

resistor

CVBS1

analog composite video input 1

CVBS0

analog composite video input 0

DDA

analog +5 V supply

SSA

analog ground supply

SSD1

digital ground supply 1

SSD2

digital ground supply 2

(1)

I/O

data bus 7/video data output 7

(1)

I/O

data bus 6/video data output 6

(1)

I/O

data bus 5/video data output 5

(1)

I/O

data bus 4/video data output 4

(1)

I/O

data bus 3/video data output 3

(1)

I/O

data bus 2/video data output 2

(1)

I/O

data bus 1/video data output 1

(1)

I/O

data bus 0/video data output 0

(1)

address input 0/video data input 7

(1)

address input 1/video data input 6

(1)

address input 2/video data input 5

INT

interrupt request

RDY

(1)

ready/DTACK (data acknowledge)/VBI, open-drain

(1)

Intel bus Write/Motorola bus R/W/video data input 4

(1)

Intel bus Read/Motorola bus LDS/video data input 3

CS0

chip select 0; active LOW

DMARQ

DMA request

DMACK

(1)

DMA acknowledge/video data input 2

VPOIN0

video data input 0

VPOIN1

video data input 1

SSD3

digital ground supply 3

DDD

digital +5 V supply

LLC

full rate digital video clock input

LLC2

half rate digital video clock input

CS1

chip select 1; active LOW

SYMBOL

PIN

I/O

DESCRIPTION

1998 Feb 05

Philips Semiconductors

Objective specification

Multimedia video data acquisition circuit

SAA5284

FUNCTIONAL DESCRIPTION

8.1

Power supply strategy

There are three separate +5 V (V

) connections to the IC:

1. V

DDA

supplies the critical noise-sensitive analog

front-end sections: ADC and sync separator, to reduce
interference from the rest of the front-end

2. V

DDX

supplies all sections which take standing DC

current

3. V

DDD

supplies the rest of the logic.

8.2

Clocking strategy

The master frequency reference for the IC is a
12, 13.5, 15 or 16 MHz crystal oscillator. The tolerance on
the clock frequency is 500

(1.5 kHz). Further

specifications of the crystal are given in Table 2.

If preferred, an external 12, 13.5, 15 or 16 MHz (

1.5 kHz)

frequency source may be connected to OSCIN instead of
the crystal.

8.3

Power-on reset

The RESET pin should be held HIGH for a minimum of two
clock cycles. The reset signal is passed through a Schmitt
trigger internally.

Direct addressed registers (i.e. those addressed using the
A0 to A2 pins) are set to 00H after power-up. All other
register bits are assumed to be in random states after
power-up.

8.4

Analog switch

8.5

Analog video-to-data byte converter

This section comprises a line and field sync separator, a
video clamp, an ADC and a custom adaptive digital filter
with DPLL based timing circuit.

The analog video-to-data byte converter is specifically
designed to overcome the most commonly found types of
distortion of a broadcast video signal. It is also fully
multi-standard. The data type to be demodulated is
programmable on a line-by-line basis using 4 register bits
per line for lines 2 to 23 (PAL numbering),
fields 1 and 2, and 4 further bits for all lines combined.

8.6

Packet filtering

If using a slow (e.g. 80C51) microcontroller, it is necessary
to reduce the amount of data acquired by SAA5284 before
downloading to the microcontroller to avoid it being
swamped by unwanted data. Packet filtering is available
for this purpose. A common use of this would be to acquire
only packet 8/30 in 625-line WST. The packet filter
includes optional (8, 4) Hamming correction.

8.7

Packet buffer

This is a 2 kbyte RAM which acts as a buffer for storing
received packets. The first 44 bytes are reserved for
control information. The rest of the RAM is divided into
44-byte rows (or packets), each holding the data received
on one incoming CVBS line. In the case of a WST packet
received, the data stored consists of a Magazine and
Row-Address Group (2 bytes), followed by the 40 bytes of
packet data. When data in other formats than WST is
received, this is stored in the packet buffer in the same
way. In each case, the data is preceded by two information
bytes which record on which line and field the packet was
received, and what the data type is.

8.8

FIFO

FIFO hardware is provided to manage the `read' address
for the host processor, i.e. data is read repeatedly from the
same 8-bit port, and appears byte-serially in the order of
reception. The read address can be reset to the start of the
packet buffer (the first 44-byte packet), back to the start of
the current packet, or incremented to the start of the next
packet.

Table 2

Crystal characteristics

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

series capacitance

18.5

parallel capacitance

4.9

resonant resistance

ageing

per year

adjustment tolerance

drift

1998 Feb 05

Philips Semiconductors

Objective specification

Multimedia video data acquisition circuit

SAA5284

8.9

Host interface

The SAA5284 has a multi-standard 8-bit I/O interface.
To reduce the amount of host I/O space used, the parallel
interface has only 3 address inputs (A0, A1 and A2).
An extended addressing (pointer) scheme and the data
FIFO are used to allow access to the full set of SAA5284
registers and the full span of the packet buffer.

As well as the 8 data I/O lines and 3 address lines, there
are the following control signals: RD (read LOW), WR
(write LOW), CS0 (chip select LOW), CS1(second chip
select LOW), INT (interrupt request), DMARQ (DMA
request), DMACK (DMA acknowledge) and RDY (ready).

In order to maintain compatibility with Motorola and Intel
type buses, two control signals SEL0 and SEL1 are
provided to configure the host interface. These signals
allow configuration of the host interface to work with the
Motorola or Intel style interfaces.

The host interface has a digital video mode. Digital video
mode may be used to allow the SAA5284 to pass decoded
VBI data into a system using the digital video bus.

8.10

Interrupt support

The host interface provides comprehensive support for
interrupt generation. The interrupt may be programmed to
occur when a particular number of packets of VBI data are
available in the cache RAM. The interrupts can be further
controlled to occur on a specific line in the TV frame.
The interrupts can also be self masking if required.

8.11

DMA support

Burst and demand mode DMA are supported. In burst
mode, the number of packets to transfer can be defined.
An interrupt can be generated when DMA is finished. This
can be self masking.

8.12

C-bus interface

The I

C-bus interface functions as a slave receiver or

transmitter at up to 400 kHz. The I

C-bus address is

selectable as 20H or 22H. All functionality is available
using the I

C-bus although with a slower data transfer

speed. It is possible to use the I

C-bus in all modes.

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

10 QUALITY & RELIABILITY

In accordance with

"SNW-FQ-611-E".

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

supply voltage (all supplies)

0.3

+6.5

I(max)

input voltage (any input)

0.3

+ 0.5

O(max)

output voltage (any output)

0.3

+ 0.5

DDD

DDA

DDX

supply voltage difference between V

DDD

, V

DDA

and V

DDX

0.25

IOK

DC input or output diode current

O(max)

output current (any output)

stg

storage temperature

+125

amb

operating ambient temperature

+70

1998 Feb 05

Philips Semiconductors

Objective specification

Multimedia video data acquisition circuit

SAA5284

11 CHARACTERISTICS

amb

20 to +70

C; V

= 4.5 to 5.5 V; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Power supply

DDn

supply voltage

4.5

5.0

5.5

DD(tot)

total supply current

DDD

digital supply current

DDA

analog supply current

Inputs CVBS0 and CVBS1

sync(p-p)

sync voltage
(peak-to-peak value)

0.1

0.3

0.6

burst(p-p)

colour burst voltage
(peak-to-peak value)

0.3

0.4

i(vid)(p-p)

video input voltage
(peak-to-peak value)

0.7

1.0

1.4

i(data)(p-p)

teletext data input voltage
(peak-to-peak value)

0.29

0.46

0.71

source

source impedance

250

i(sw)

input switching level of sync
separator

1.5

1.8

2.1

input impedance

2.5

5.0

input capacitance

Input I

REF

IREF

external resistor to V

SSA

Inputs RESET, HREF, SEL0, SEL1, A0, A1, A2, WR, RD, CS0, CS1, DMACK, VPOIN1, VPOIN0, LLC and LLC2

LOW-level input voltage

0.3

+0.8

HIGH-level input voltage

2.0

+ 0.5

input leakage current

= 0 to V

+10

input capacitance

Input SCL

LOW-level input voltage

0.5

+1.5

HIGH-level input voltage

3.0

+ 0.5

input leakage current

= 0 to V

+10

input capacitance

i(r)

input rise time

IL(min)

to V

IH(max)

; f

i(SCL)

= 100 kHz

1000

IL(min)

to V

IH(max)

; f

i(SCL)

= 400 kHz

300

i(f)

input fall time

IL(max)

to V

IH(min)

; f

i(SCL)

= 100 kHz

300

IL(max)

to V

IH(min)

; f

i(SCL)

= 400 kHz

300

i(SCL)

input clock frequency

400

kHz

load capacitance

400

1998 Feb 05

Philips Semiconductors

Objective specification

Multimedia video data acquisition circuit

SAA5284

Input/output SDA (open-drain)

LOW-level input voltage

0.5

+1.5

HIGH-level input voltage

3.0

+ 0.5

input leakage current

= 0 to V

+10

input capacitance

i(r)

input rise time

IL(min)

to V

IH(max)

; f

i(SCL)

= 100 kHz

1000

IL(min)

to V

IH(max)

; f

i(SCL)

= 400 kHz

300

i(f)

input fall time

IL(max

) to V

IH(min)

; f

i(SCL)

= 100 kHz

300

IL(max)

to V

IH(min)

; f

i(SCL)

= 400 kHz

300

LOW-level output voltage

= 3 mA

0.4

= 6 mA

0.6

o(f)

output fall time

between 3 and 1.5 V; I

= 3 mA

250

load capacitance

400

Input/output BLACK

BLACK

storage capacitance to V

SSA

100

Inputs/outputs D7 to D0

LOW-level input voltage

0.3

+0.8

HIGH-level input voltage

2.0

+ 0.5

input leakage current

= 0 to V

+10

input capacitance

LOW-level output voltage

= +1.6 mA

0.4

HIGH-level output voltage

0.2 mA

2.4

load capacitance

tbf

o(r)

output rise time into C

0.6 to 2.2 V

tbf

o(f)

output fall time into C

2.2 to 0.6 V

tbf

Outputs INT, DENB and DMARQ

LOW-level output voltage

= +1.6 mA

0.4

HIGH-level output voltage

0.2 mA

2.4

load capacitance

tbf

o(r)

output rise time into C

0.6 to 2.2 V

tbf

o(f)

output fall time into C

2.2 to 0.6 V

tbf

RDY (open-drain); note 1

LOW-level output voltage

= +1.6 mA

0.4

load capacitance

tbf

o(r)

output rise time into C

0.6 to 2.2 V

tbf

o(f)

output fall time into C

2.2 to 0.6 V

tbf

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1998 Feb 05

Philips Semiconductors

Objective specification

Multimedia video data acquisition circuit

SAA5284

Notes

1. ESD protection of this pin falls below the Philips General Quality Specification (GQS). Therefore it is recommended

that a diode is connected from pin RDY to V

DDD

2. The I

C-bus interface pins SDA and SCL may pull the data and clock lines below 3 V while the digital power supply

DDD

is in the range 0.4 to 0.8 V.

C-bus timings (see note 2 and Fig.8)

i(SCL)

SCL input clock frequency

i(SCL)

= 100 kHz

100

kHz

i(SCL)

= 400 kHz

400

kHz

LOW

SCL LOW time

i(SCL)

= 100 kHz

4.7

i(SCL)

= 400 kHz

1.3

HIGH

SCL HIGH time

i(SCL)

= 100 kHz

4.0

i(SCL)

= 400 kHz

0.6

SU;DAT

data set-up time

i(SCL)

= 100 kHz

250

i(SCL)

= 400 kHz

100

HD;DAT

data hold time

i(SCL)

= 100 kHz

i(SCL)

= 400 kHz

SU;STO

set-up time STOP condition

i(SCL)

= 100 kHz

4.7

i(SCL)

= 400 kHz

0.6

BUF

bus free time

i(SCL)

= 100 kHz

4.7

i(SCL)

= 400 kHz

1.3

HD;STA

hold time START condition

i(SCL)

= 100 kHz

4.0

i(SCL)

= 400 kHz

0.6

SU;STA

set-up time repeated START f

i(SCL)

= 100 kHz

4.7

i(SCL)

= 400 kHz

0.6

rise time (SDA and SCL)

i(SCL)

= 100 kHz

1000

i(SCL)

= 400 kHz

300

fall time (SDA and SCL)

i(SCL)

= 100 kHz

300

i(SCL)

= 400 kHz

300

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1998 Feb 05

Philips Semiconductors

Objective specification

Multimedia video data acquisition circuit

SAA5284

Fig.10 Application circuit diagram for ISA card.

(1) Option of 13.5, 15 and 16 MHz or direct feed from external clock.

(2) A diode to V

DDD

is recommended for ESD protection.

(3) Pin DMACK must be connected to V

DDD

if DMA is not used.

handbook, full pagewidth

MGG742

27 k

22
pF

100 nF

BLACK

IREF

VSSA VSSD3 VSSD1 VSSD2

VSSA = 0 V

VSSD = 0 V

supply decoupling

SEL1

SEL0

CS1

CVBS0

CVBS1

OSCIN

OSCOUT

OSCGND

SDA

SCL

HREF

LLC

LLC2

VPOIN1

VPOIN0

100 nF

CVBS0

CVBS1

100 nF

12 MHz

)

GND

ADDRESS

DECODER

e.g.

PLUS153

74 SERIES

LOGIC

VCC

22
pF

VSSA = 0 V

VDDA =

5 V

VDDA

VDDD

VDDX

VDDD =

5 V

VSSA = 0 V

n.c.

INT

RDY

(2)

DMARQ

DMACK

(3)

AEN

RESET

DENB

IRQx

I/O RDY

IOW

IOR

DACKx

RESET

n.c.

CS0

SAA5284

VSSD = 0 V

VDDD = 5 V

VDDA

VDDD

VSSA

VSSD

100

5 V

0 V

1998

Feb

Philips Semiconductors

Objective specification

Multimedia video data acquisition circuit

SAA5284

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handbook, full pagewidth

MGG744

27 k

22
pF

100 nF

BLACK

IREF

VSSA VSSD3 VSSD1 VSSD2

VSSA = 0 V

VSSD = 0 V

SEL1

SEL0

CS1

CVBS0

CVBS1

OSCIN

OSCOUT

OSCGND

SDA

supply decoupling

SCL

HREF

LLC

LLC2

VPOIN1

VPOIN0

100 nF

CVBS0

CVBS1

100 nF

12 MHz

)

22
pF

VSSA = 0 V

VDDA =

5 V

VDDA

VDDD

VDDX

VDDD =

5 V

VSSA = 0 V

5 k

VDDD

74HCT75

INT

RDY

DMARQ

DMACK

RESET

n.c.

VDDD

n.c.

DENB

SAA5284

XAD7

XAD6

XAD5

XAD4

XAD3

XAD2

XAD1

XAD0

DEBI PORT

XIRQ

RDY

WRN

RDN

RESET

SAA7145
SAA7146

115

116

117

118

CS0

ALE

114

124

123

125

126

129

130

131

132

VDDA

VDDD

VSSA

VSSD

100

5 V

0 V

Fig.11 Application circuit diagram for PCI application.

(1) Option of 13.5, 15 and 16 MHz or LLC2 from the SAA7111 if in 13.5 MHz mode.

1998 Feb 05

Philips Semiconductors

Objective specification

Multimedia video data acquisition circuit

SAA5284

15 SOLDERING

15.1

Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"IC Package Databook" (order code 9398 652 90011).

15.2

Reflow soldering

Reflow soldering techniques are suitable for all QFP
packages.

The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

"Quality

Reference Handbook" (order code 9397 750 00192).

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250

15.3

Wave soldering

Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

CAUTION

Wave soldering is NOT applicable for all QFP
packages with a pitch (e) equal or less than 0.5 mm.

If wave soldering cannot be avoided, for QFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:

A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.

The footprint must be at an angle of 45

to the board

direction and must incorporate solder thieves
downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260

C, and

maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150

C within

6 seconds. Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

15.4

Repairing soldered joints

Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300

C. When

using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320

1998 Feb 05

Philips Semiconductors

Objective specification

Multimedia video data acquisition circuit

SAA5284

16 DEFINITIONS

17 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

18 PURCHASE OF PHILIPS I

C COMPONENTS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I

C components conveys a license under the Philips' I

C patent to use the

components in the I

C system provided the system conforms to the I

C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

Internet: http://www.semiconductors.philips.com

Philips Semiconductors a worldwide company

SCA53

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

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Printed in The Netherlands

655102/00/02/pp24

Date of release: 1998 Feb 05

Document order number:

9397 750 02768

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SAA5284GP/M1

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SAA5284GP/M1