Document Outline

CONTENTS
1 FEATURES
2 APPLICATIONS
3 GENERAL DESCRIPTION
4 QUICK REFERENCE DATA
5 ORDERING INFORMATION
6 BLOCK DIAGRAM
7 PINNING
8 FUNCTIONAL DESCRIPTION
- 8.1 Analog input processing
- 8.2 Analog control circuits
- 8.3 Chrominance processing
- 8.4 Luminance processing
- 8.5 RGB matrix
- 8.6 VBI-data bypass
- 8.7 VPO-bus (digital outputs)
- 8.8 Reference signals HREF, VREF and CREF
- 8.9 Synchronization
- 8.10 Clock generation circuit
- 8.11 Power-on reset and CE input
- 8.12 RTCO output
- 8.13 The Line-21 text slicer
9 BOUNDARY-SCAN TEST
- 9.1 Device identification codes
- 9.2 Initialization of boundary-scan circuit
10 GAIN CHARTS
11 LIMITING VALUES
12 CHARACTERISTICS
13 TIMING DIAGRAMS
14 CLOCK SYSTEM
- 14.1 Clock generation circuit
- 14.2 Power-on control
15 OUTPUT FORMATS
16 APPLICATION INFORMATION
17 I2C-BUS DESCRIPTION
- 17.1 I2C-bus format
- 17.2 I2C-bus detail
18 FILTER CURVES
- 18.1 Anti-alias filter curve
- 18.2 TUF-block filter curve
- 18.3 Luminance filter curves
- 18.4 Chrominance filter curves
19 I2C-BUS START SET-UP
20 PACKAGE OUTLINES
- SOT314-2
21 SOLDERING
- 21.1 Introduction
- 21.2 Reflow soldering
- 21.3 Wave soldering
- 21.4 Repairing soldered joints
22 DEFINITIONS
23 LIFE SUPPORT APPLICATIONS
24 PURCHASE OF PHILIPS I2C COMPONENTS

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

CONTENTS

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

QUICK REFERENCE DATA

ORDERING INFORMATION

BLOCK DIAGRAM

PINNING

FUNCTIONAL DESCRIPTION

8.1

Analog input processing

8.2

Analog control circuits

8.2.1

Clamping

8.2.2

Gain control

8.3

Chrominance processing

8.4

Luminance processing

8.5

RGB matrix

8.6

VBI-data bypass

8.7

VPO-bus (digital outputs)

8.8

Reference signals HREF, VREF and CREF

8.9

Synchronization

8.10

Clock generation circuit

8.11

Power-on reset and CE input

8.12

RTCO output

8.13

The Line-21 text slicer

8.13.1

Suggestions for I2C-bus interface of the display
software reading line-21 data

BOUNDARY-SCAN TEST

9.1

Initialization of boundary-scan circuit

9.2

Device identification codes

GAIN CHARTS

LIMITING VALUES

CHARACTERISTICS

TIMING DIAGRAMS

CLOCK SYSTEM

14.1

Clock generation circuit

14.2

Power-on control

OUTPUT FORMATS

APPLICATION INFORMATION

16.1

Layout hints

C-BUS DESCRIPTION

17.1

C-bus format

17.2

C-bus detail

17.2.1

Subaddress 00

17.2.2

Subaddress 02

17.2.3

Subaddress 03

17.2.4

Subaddress 04

17.2.5

Subaddress 05

17.2.6

Subaddress 06

17.2.7

Subaddress 07

17.2.8

Subaddress 08

17.2.9

Subaddress 09

17.2.10

Subaddress 0A

17.2.11

Subaddress 0B

17.2.12

Subaddress 0C

17.2.13

Subaddress 0D

17.2.14

Subaddress 0E

17.2.15

Subaddress 10

17.2.16

Subaddress 11

17.2.17

Subaddress 12

17.2.18

Subaddress 13

17.2.19

Subaddress 15

17.2.20

Subaddress 16

17.2.21

Subaddress 17

17.2.22

Subaddress 1A (read-only register)

17.2.23

Subaddress 1B (read-only register)

17.2.24

Subaddress 1C (read-only register)

17.2.25

Subaddress 1F (read-only register)

FILTER CURVES

18.1

Anti-alias filter curve

18.2

TUF-block filter curve

18.3

Luminance filter curves

18.4

Chrominance filter curves

C-BUS START SET-UP

PACKAGE OUTLINES

SOLDERING

21.1

Introduction

21.2

Reflow soldering

21.3

Wave soldering

21.4

Repairing soldered joints

DEFINITIONS

LIFE SUPPORT APPLICATIONS

PURCHASE OF PHILIPS I

C COMPONENTS

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

FEATURES

�

Four analog inputs, internal analog source selectors,
e.g. 4

�

CVBS or 2

�

Y/C or (1

�

Y/C and 2

�

CVBS)

�

Two analog preprocessing channels

�

Fully programmable static gain for the main channels or
automatic gain control for the selected CVBS or Y/C
channel

�

Switchable white peak control

�

Two built-in analog anti-aliasing filters

�

Two 8-bit video CMOS analog-to-digital converters

�

On-chip clock generator

�

Line-locked system clock frequencies

�

Digital PLL for horizontal-sync processing and clock
generation

�

Requires only one crystal (24.576 MHz) for all standards

�

Horizontal and vertical sync detection

�

Automatic detection of 50 and 60 Hz field frequency,
and automatic switching between PAL and NTSC
standards

�

Luminance and chrominance signal processing for
PAL BGHI, PAL N, PAL M, NTSC M, NTSC N,
NTSC 4.43, NTSC-Japan and SECAM

�

User programmable luminance peaking or aperture
correction

�

Cross-colour reduction for NTSC by chrominance comb
filtering

�

PAL delay line for correcting PAL phase errors

�

Real time status information output (RTCO)

�

Brightness Contrast Saturation (BCS) control on-chip

�

The YUV (CCIR-601) bus supports a data rate of:

� 864

�

= 13.5 MHz for 625 line sources

� 858

�

= 13.5 MHz for 525 line sources.

�

Data output streams for 16, 12 or 8-bit width with the
following formats:

� YUV 4 : 1 : 1 (12-bit)

� YUV 4 : 2 : 2 (16-bit)

� YUV 4 : 2 : 2 (CCIR-656) (8-bit)

� RGB (5, 6, and 5) (16-bit) with dither

� RGB (8, 8, and 8) (24-bit) with special application.

�

Odd/even field identification by a non interlace CVBS
input signal

�

Fix level for RGB output format during horizontal
blanking

�

720 active samples per line on the YUV bus

�

One user programmable general purpose switch on an
output pin

�

Built-in line-21 text slicer

�

A 27 MHz Vertical Blanking Interval (VBI) data bypass
programmable by I

C-bus for INTERCAST applications

�

Power-on control

�

Two via I

C-bus switchable outputs for the digitized

CVBS or Y/C input signals AD1 (7 to 0) and AD2 (7 to 0)

�

Chip enable function (reset for the clock generator and
power save mode up from chip version 3)

�

Compatible with memory-based features (line-locked
clock)

�

Boundary scan test circuit complies with the
`IEEE Std. 1149.1

1990' (ID-Code = 0 F111 02 B)

�

C-bus controlled (full read-back ability by an external

controller)

�

Low power (

0.5 W), low voltage (3.3 V), small package

(LQFP64)

�

5 V tolerant digital I/O ports.

APPLICATIONS

�

Desktop/Notebook (PCMCIA) video

�

Multimedia

�

Digital television

�

Image processing

�

Video phone

�

Intercast.

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

GENERAL DESCRIPTION

The Enhanced Video Input Processor (EVIP) is a
combination of a two-channel analog preprocessing
circuit including source selection, anti-aliasing filter and
ADC, an automatic clamp and gain control, a Clock
Generation Circuit (CGC), a digital multi-standard
decoder (PAL BGHI, PAL M, PAL N, NTSC M,
NTSC-Japan NTSC N and SECAM), a
brightness/contrast/saturation control circuit, a colour
space matrix (see Fig.1) and a 27 MHz VBI-data bypass.

The pure 3.3 V CMOS circuit SAA7111A, analog
front-end and digital video decoder, is a highly integrated
circuit for desktop video applications. The decoder is
based on the principle of line-locked clock decoding and
is able to decode the colour of PAL, SECAM and NTSC
signals into CCIR-601 compatible colour component
values. The SAA7111A accepts as analog inputs CVBS
or S-video (Y/C) from TV or VTR sources. The circuit is
I

C-bus controlled. The SAA7111A then supports several

text features as Line 21 data slicing and a high-speed VBI
data bypass for Intercast.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

DDD

digital supply voltage

3.0

3.3

3.6

DDA

analog supply voltage

3.1

3.3

3.5

amb

operating ambient temperature

�

A+D

analog and digital power

0.5

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

SAA7111AHZ

LQFP64

plastic low profile quad flat package; 64 leads; body 10

�

1.4 mm

SOT314-2

SAA7111AH

QFP64

plastic quad flat package; 64 leads (lead length 1.6 mm);
body 14

�

2.7 mm

SOT393-1

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

PINNING

SYMBOL

PIN

I/O/P

DESCRIPTION

(L)QFP64

n.c.

Do not connect.

TDO

Test data output for boundary scan test; note 1.

TDI

Test data input for boundary scan test; note 1.

TMS

Test mode select input for boundary scan test or scan test; note 1.

SSA2

Ground for analog supply voltage channel 2.

AI22

Analog input 22.

DDA2

Positive supply voltage for analog channel 2 (+3.3 V).

AI21

Analog input 21.

SSA1

Ground for analog supply voltage channel 1.

AI12

Analog input 12.

DDA1

Positive supply voltage for analog channel 1 (+3.3 V).

AI11

Analog input 11.

SSS

Substrate ground connection.

AOUT

Analog test output; for testing the analog input channels.

DDA0

Positive supply voltage for internal Clock Generator Circuit (CGC) (+3.3 V).

SSA0

Ground for internal CGC.

VREF

Vertical reference output signal (I

C-bit COMPO = 0) or inverse composite blanking

signal (I

C-bit COMPO = 1) (enabled via I

C-bus bit OEHV).

DDD5

Digital supply voltage 5 (+3.3 V).

SSD5

Ground for digital supply voltage 5.

LLC

Line-locked system clock output (27 MHz).

LLC2

Line-locked clock

output (13.5 MHz).

CREF

Clock reference output: this is a clock qualifier signal distributed by the internal CGC
for a data rate of LLC2. Using CREF all interfaces on the VPO bus are able to
generate a bus timing with identical phase. If CCIR 656 format is selected
(OFTS0 = 1 and OFTS1 = 1) an inverse composite blanking signal (pixel qualifier) is
provided on this pin.

RES

Reset output (active LOW); sets the device into a defined state. All data outputs are
in high impedance state. The I

C-bus is reset (waiting for start condition).

Chip enable; connection to ground forces a reset, up from version 3 power save
function additionally available.

DDD4

Digital supply voltage input 4 (+3.3 V).

SSD4

Ground for digital supply voltage input 4.

Horizontal sync output signal (programmable); the positions of the positive and
negative slopes are programmable in 8 LLC increments over a complete line
(equals 64

�

s) via I

C-bus bytes HSB and HSS. Fine position adjustment in 2 LLC

increments can be performed via I

C-bus bits HDEL1 and HDEL0.

RTS1

Two functions output; controlled by I

C-bus bit RTSE1.

RTSE1 = 0: PAL line identifier (LOW = PAL line); indicates the inverted and
non-inverted R

Y component for PAL signals. RTSE1 = 1: H-PLL locked indicator;

a high state indicates that the internal horizontal PLL has locked.

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

RTS0

Two functions output; controlled by I

C-bus bit RTSE0.

RTSE0 = 0: odd/even field identification (HIGH = odd field). RTSE0 = 1: vertical
locked indicator; a HIGH state indicates that the internal Vertical Noise Limiter (VNL)
has locked.

Vertical sync signal (enabled via I

C-bus bit OEHV); this signal indicates the vertical

sync with respect to the YUV output. The HIGH period of this signal is approximately
six lines if the VNL function is active. The positive slope contains the phase
information for a deflection controller.

HREF

Horizontal reference output signal (enabled via I

C-bus bit OEHV); this signal is used

to indicate data on the digital YUV bus. The positive slope marks the beginning of a
new active line. The HIGH period of HREF is 720 Y samples long. HREF can be used
to synchronize data multiplexer/demultiplexer. HREF is also present during the
vertical blanking interval.

SSD3

Ground for digital supply voltage input 3.

DDD3

Digital supply voltage 3 (+3.3 V).

VPO
(15 to 10)

34 to 39

Digital VPO-bus (Video Port Out) signal; higher bits of the 16-bit VPO-bus or the
16-bit RGB-bus output signal. The output data rate, the format and multiplexing
scheme of the VPO-bus are controlled via I

C-bus bits OFTS0 and OFTS1. If I

C-bus

bit VIPB = 1 the six MSBs of the digitized input signal are connected to these outputs,
configured by the I

C-bus `MODE' bits (see Figs 33 to 40):

LUMA

VPO15 to VPO8, CHROMA

VPO7 to VPO0.

SSD2

Ground for digital supply voltage input 2.

DDD2

Digital supply voltage 2 (+3.3 V).

VPO
(9 to 0)

42 to 51

Digital VPO-bus output signal; lower bits of the 16-bit YUV-bus or the 16-bit RGB-bus
output signal. The output data rate, the format and multiplexing schema of the
VPO-bus are controlled via I

C-bus bits OFTS0 and OFTS1. If I

C-bus bit VIPB = 1

the digitized input signal are connected to these outputs, configured by the I

C-bus

`MODE' bits (see Figs 33 to 40): LUMA

VPO15 to VPO8,

CHROMA

VPO7 to VPO0.

FEI

Fast enable input signal (active LOW); this signal is used to control fast switching on
the digital YUV-bus. A HIGH at this input forces the IC to set its Y and UV outputs to
the high impedance state.

GPSW

General purpose switch output; the state of this signal is set via I

C-bus control and

the levels are TTL compatible.

XTAL

Second terminal of crystal oscillator; not connected if external clock signal is used.

XTALI

Input terminal for 24.576 MHz crystal oscillator or connection of external oscillator
with CMOS compatible square wave clock signal.

SSD1

Ground for digital supply voltage input 1.

DDD1

Digital supply voltage input 1 (+3.3 V).

TRST

Test reset input not (active LOW), for boundary scan test; notes 1, 2 and 3.

TCK

Test clock for boundary scan test; note 1.

RTCO

Real time control output: contains information about actual system clock frequency,
subcarrier frequency and phase and PAL sequence.

SYMBOL

PIN

I/O/P

DESCRIPTION

(L)QFP64

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

FUNCTIONAL DESCRIPTION

8.1

Analog input processing

The SAA7111A offers four analog signal inputs, two
analog main channels with source switch, clamp circuit,
analog amplifier, anti-alias filter and video CMOS ADC
(see Fig.5).

8.2

Analog control circuits

The anti-alias filters are adapted to the line-locked clock
frequency via a filter control circuit. During the vertical
blanking time, gain and clamping control are frozen.

8.2.1

LAMPING

The clamp control circuit controls the correct clamping of
the analog input signals. The coupling capacitor is also
used to store and filter the clamping voltage. An internal
digital clamp comparator generates the information with
respect to clamp-up or clamp-down. The clamping levels
for the two ADC channels are fixed for luminance (60) and
chrominance (128). Clamping time in normal use is set
with the HCL pulse at the back porch of the video signal.

8.2.2

AIN CONTROL

Signal (white) peak control limits the gain at signal
overshoots. The flow charts (see Figs 13 and 14) show
more details of the AGC. The influence of supply voltage
variation within the specified range is automatically
eliminated by clamp and automatic gain control.

The gain control circuit receives (via the I

C-bus) the static

gain levels for the two analog amplifiers or controls one of
these amplifiers automatically via a built-in automatic gain
control (AGC) as part of the Analog Input Control (AICO).

Fig.3

Analog line with clamp (HCL) and gain
range (HSY).

handbook, halfpage

HCL

MGL065

HSY

analog line blanking

TV line

255

GAIN

CLAMP

The AGC (automatic gain control for luminance) is used to
amplify a CVBS or Y signal to the required signal
amplitude, matched to the ADCs input voltage range.
The AGC active time is the sync bottom of the video signal.

8.3

Chrominance processing

The 8-bit chrominance signal is fed to the multiplication
inputs of a quadrature demodulator, where two subcarrier
signals from the local oscillator DTO1 are applied
(0 and 90

�

phase relationship to the demodulator axis).

The frequency is dependent on the present colour
standard. The output signals of the multipliers are
low-pass filtered (four programmable characteristics) to
achieve the desired bandwidth for the colour difference
signals (PAL and NTSC) or the 0 and 90

�

FM-signals

(SECAM).

The colour difference signals are fed to the
Brightness/Contrast/Saturation block (BCS), which
includes the following five functions:

�

AGC (Automatic Gain Control for chrominance
PAL and NTSC)

�

Chrominance amplitude matching (different gain factors
for R

Y and B

Y to achieve CCIR-601 levels

Cr and Cb for all standards)

�

Chrominance saturation control

�

Luminance contrast and brightness

�

Limiting YUV to the values 1 (min.) and 254 (max.) to
fulfil CCIR-601 requirements.

Fig.4 Automatic gain range.

handbook, halfpage

analog input level

controlled

ADC input level

maximum

minimum

range tbf

0 dB

MGG063

4.5 dB

7.5 dB

(1 V(p-p) 27/47

)

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

The SECAM-processing contains the following blocks:

�

Baseband `bell' filters to reconstruct the amplitude and
phase equalized 0 and 90

�

FM-signals

�

Phase demodulator and differentiator
(FM-demodulation)

�

De-emphasis filter to compensate the pre-emphasised
input signal, including frequency offset compensation
(DB or DR white carrier values are subtracted from the
signal, controlled by the SECAM-switch signal).

The burst processing block provides the feedback loop of
the chroma PLL and contains;

�

Burst gate accumulator

�

Colour identification and killer

�

Comparison nominal/actual burst amplitude (PAL/NTSC
standards only)

�

Loop filter chrominance gain control (PAL/NTSC
standards only)

�

Loop filter chrominance PLL (only active for PAL/NTSC
standards)

�

PAL/SECAM sequence detection, H/2-switch
generation

�

Increment generation for DTO1 with divider to generate
stable subcarrier for non-standard signals.

The chrominance comb filter block eliminates crosstalk
between the chrominance channels in accordance with the
PAL standard requirements. For NTSC colour standards
the chrominance comb filter can be used to eliminate
crosstalk from luminance to chrominance (cross-colour)
for vertical structures. The comb filter can be switched off
if desired. The embedded line delay is also used for
SECAM recombination (cross-over switches).

The resulting signals are fed to the variable Y-delay
compensation, RGB matrix, dithering circuit and output
interface, which contains the VPO output formatter and the
output control logic (see Fig.6).

8.4

Luminance processing

The 8-bit luminance signal, a digital CVBS format or a
luminance format (S-VHS, HI8), is fed through a
switchable prefilter. High frequency components are
emphasized to compensate for loss. The following
chrominance trap filter (f

= 4.43 or 3.58 MHz centre

frequency selectable) eliminates most of the colour carrier
signal, therefore, it must be bypassed for S-video
(S-VHS and HI8) signals.

The high frequency components of the luminance signal
can be peaked (control for sharpness improvement via
I

C-bus) in two band-pass filters with selectable transfer

characteristic. This signal is then added to the original
(unpeaked) signal. A switchable amplifier achieves
common DC amplification, because the DC gains are
different in both chrominance trap modes. The improved
luminance signal is fed to the BCS control located in the
chrominance processing block (see Fig.7).

8.5

RGB matrix

Y, Cr and Cb data are converted after interpolation into
RGB data in accordance with CCIR-601
recommendations. The realized matrix equations consider
the digital quantization:

R = Y + 1.371 Cr

G = Y

0.336 Cb

0.698 Cr

B = Y + 1.732 Cb.

After dithering (noise shaping) the RGB data is fed to the
output interface within the VPO-bus output formatter.

8.6

VBI-data bypass

For a 27 MHz VBI-data bypass the offset binary CVBS
signal is upsampled behind the ADCs. Upsampling of the
CVBS signal from 13.5 to 27 MHz is possible, because the
ADCs deliver high performance at 13.5 MHz sample clock.
Suppressing of the back folded CVBS frequency
components after upsampling is achieved by an
interpolation filter (see Fig.42).

The TUF block on the digital top level performs the
upsampling and interpolation for the bypassed CVBS
signal (see Fig.6).

For bypass details see Figs 8 to 10.

8.7

VPO-bus (digital outputs)

The 16-bit VPO-bus transfers digital data from the output
interfaces to a feature box or a field memory, a digital
colour space converter (SAA7192 DCSC), a video
enhancement and digital-to-analog processor
(SAA7165 VEDA2) or a colour graphics board
(Targa-format) as a graphical user interface.

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

The output data formats are controlled via the I

C-bus bits

OFTS0, OFTS1 and RGB888. Timing for the data stream
formats, YUV (4 : 1 : 1) (12-bit), YUV (4 : 2 : 2) (16-bit),
RGB (5, 6 and 5) (16-bit) and RGB (8, 8 and 8) (24-bit)
with an LLC2 data rate, is achieved by marking each
second positive rising edge of the clock LLC in conjunction
with CREF (clock reference) (except RGB (8, 8 and 8),
see special application in Fig.32). The higher output
signals VPO15 to VPO8 in the YUV format perform the
digital luminance signal. The lower output signals
VPO7 to VPO0 in the YUV format are the bits of the
multiplexed colour difference signals (B

Y) and (R

Y).

The arrangement of the RGB (5, 6 and 5) and
RGB (8, 8 and 8) data stream bits on the VPO-bus is given
in Table 6.

The data stream format YUV 4 : 2 : 2 (the 8 higher output
signals VPO15 to VPO8) in LLC data rate fulfils the
CCIR-656 standard with its own timing reference code at
the start and end of each video data block.

A pixel in the format tables is the time required to transfer
a full set of samples. If 16-bit 4 : 2 : 2 format is selected
two luminance samples are transmitted in comparison to
one (B

Y) and one (R

Y) sample within a pixel.

The time frames are controlled by the HREF signal.

Fast enable is achieved by setting input FEI to LOW.
The signal is used to control fast switching on the digital
VPO-bus. HIGH on this pin forces the VPO outputs to a
high-impedance state (see Figs 18 and 19). The I

C-bus

bit OEYC has to be set HIGH to use this function.

The digitized PAL, SECAM or NTSC signals AD1 (7 to 0)
and AD2 (7 to 0) are connected directly to the VPO-bus
via I

C-bus bit VIPB = 1 and MODE = 4, 5, 6 or 7.

AD1 (7 to 0)

VPO (15 to 8) and

AD2 (7 to 0)

VPO (7 to 0).

The selection of the analog input channels is controlled via
I

C-bus subaddress 02 MODE select.

The upsampled 8-bit offset binary CVBS signal (VBI-data
bypass) is multiplexed under control of the I

C-bus to the

digital VPO-bus (see Fig.8).

8.8

Reference signals HREF, VREF and CREF

�

HREF: The positive slope of the HREF output signal
indicates the beginning of a new active video line.
The high period is 720 luminance samples long and is
also present during the vertical blanking.
The description of timing and position from HREF is
illustrated in Figs 15, 16, 21 and 23.

�

VREF: The VREF output delivers a vertical reference
signal or an inverse composite blank signal controlled
via the I

C-bus [subaddress 11, inverse composite

blank (COMPO)]. Furthermore four different modes of
vertical reference signals are selectable via the I

C-bus

[subaddress 13, vertical reference output control
(VCTR1 and VCTR0)]. The description of VREF timing
and position is illustrated in Figs 15, 16, 24 and 25.

�

CREF: The CREF output delivers a clock/pixel qualifier
signal for external interfaces to synchronize to the
VPO-bus data stream.

Four different modes for the clock qualifier signal are
selectable via the I

C-bus [subaddress 13, clock

reference output control (CCTR1 and CCTR0)].
The description of CREF timing and position is
illustrated in Figs 16, 18, 20 and 21.

8.9

Synchronization

The prefiltered luminance signal is fed to the
synchronization stage. Its bandwidth is reduced to 1 MHz
in a low-pass filter. The sync pulses are sliced and fed to
the phase detectors where they are compared with the
sub-divided clock frequency. The resulting output signal is
applied to the loop filter to accumulate all phase
deviations. Internal signals (e. g. HCL and HSY) are
generated in accordance with analog front-end
requirements. The output signals HS, VS, and PLIN are
locked to the timing reference, guaranteed between the
input signal and the HREF signal, as further improvements
to the circuit may change the total processing delay. It is
therefore not recommended to use them for applications
which require absolute timing accuracy on the input
signals. The loop filter signal drives an oscillator to
generate the line frequency control signal LFCO
(see Fig.7).

8.10

Clock generation circuit

The internal CGC generates all clock signals required for
the video input processor. The internal signal LFCO is a
digital-to-analog converted signal provided by the
horizontal PLL. It is the multiple of the line frequency

Internally the LFCO signal is multiplied by a factor of 2 or 4
in the PLL circuit (including phase detector, loop filtering,
VCO and frequency divider) to obtain the LLC and LLC2
output clock signals. The rectangular output clocks have
a 50% duty factor (see Fig.26).

6.75MHz

429
432

----------

�

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

8.11

Power-on reset and CE input

A missing clock, insufficient digital or analog V

DDA0

supply

voltages (below 2.7 V) will initiate the reset sequence; all
outputs are forced to 3-state. The indicator output RES is
LOW for approximately 128LLC after the internal reset and
can be applied to reset other circuits of the digital TV
system.

It is possible to force a reset by pulling the chip enable
(CE) to ground. After the rising edge of CE and sufficient
power supply voltage, the outputs LLC, LLC2, CREF,
RTCO, RTS0, RTS1, GPSW and SDA return from 3-state
to active, while HREF, VREF, HS and VS remain in 3-state
and have to be activated via I

C-bus programming

(see Table 5).

8.12

RTCO output

The real time control and status output signal contains
serial information about the actual system clock
(increment of the HPLL), subcarrier frequency [increment
and phase (via reset) of the FSC-PLL] and PAL sequence
bit. The signal can be used for various applications in
external circuits, e.g. in a digital encoder to achieve clean
encoding (see Fig.20).

8.13

The Line-21 text slicer

The text slicer block detects and acquires Line-21 Closed
Captioning data from a 525-line CVBS signal. Extended
data services on Line-21 Field 2 are also supported.
If valid data is detected the two data bytes are stored in two
I

C-bus registers. A parity check is also performed and the

result is stored in the MSB of the corresponding byte.
A third I

C-bus register is provided for data valid and data

ready flags. The two bits F1VAL and F2VAL indicate that
the input signal carries valid Closed Captioning data in the
corresponding fields. The data ready bits F1RDY and
F2RDY have to be evaluated if asynchronous I

C-bus

reading is used.

8.13.1

UGGESTIONS FOR

C-

BUS INTERFACE OF THE

DISPLAY SOFTWARE READING LINE

-21

DATA

There are two methods by which the software can acquire
the data:

1. Synchronous reading once per frame (or once per

field); It can use either the rising edge (Line-21 Field 1)
or both edges (Line-21 Field 1 or 2) of the ODD signal
(pin RTSO) to initiate an I

C-bus read transfer of the

three registers 1A, 1B and 1C.

2. Asynchronous reading; It can poll either the F1RDY bit

(Line-21 Field 1) or both F1RDY/F2RDY bits (Line-21
Field 1 or 2). After valid data has been read the
corresponding F*RDY bit is set to LOW until new data
has arrived. The polling frequency has to be slightly
higher than the frame or field frequency, respectively.

1998

May

Philips Semiconductors

Product specification

Enhanced V

ideo Input Processor (EVIP)

SAA71

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AI22

AI21

FUSE (1 : 0)

AI12

AI11

FUSE (1 : 0)

AOSL (1 : 0)

HOLDG

ANALOG
CONTROL

GAI10-GAI18

SSS

n.c.

VBSL

MGC655

CHR

LUM

VERTICAL

BLANKING

CONTROL

SOURCE

SWITCH

CLAMP

CIRCUIT

ANALOG

AMPLIFIER

ANTI-ALIAS

FILTER

BYPASS
SWITCH

SOURCE

SWITCH

CLAMP

CIRCUIT

ANALOG

AMPLIFIER

ANTI-ALIAS

FILTER

BYPASS

SWITCH

ADC2

ADC1

TEST

AND

SELECTOR

CLAMP

CONTROL

GAIN

CONTROL

CROSS

MULTIPLEXER

ANTI-ALIAS

CONTROL

DDA1

SSA2

AOUT

MODE

CONTROL

MODE 0

MODE 1
MODE 2

GAI20-GAI28

GUDL0-GUDL2

GAFIX

WPOFF

HSY

VBLNK
SVREF

HCL

AD1BYP

AD2BYP

BUFFER

DAC9

HLNRS
UPTCV

DDA2

SSA1

GLIMB
GLIMT
WIPA
SLTCA

Fig.5 Analog input processing.

1998

May

Philips Semiconductors

Product specification

Enhanced V

ideo Input Processor (EVIP)

SAA71

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Fig.6 Chrominance circuit.

ewidth

CHR

LUM

CODE

AD1BYP

AD2BYP

BRIG

CONT

SATN

HUEC

DCCF

fH/2 switch signal

MGG062

DDD1-5

SSD1-5

57,41,33,
25,18

56,40,32,26,19

34 to 39

42 to 51

QUADRATURE

DEMODULATOR

COMB

FILTERS

SECAM

RECOMBINATION

FORMATTER

OUTPUT

AND

INTERFACE

ACCUMULATOR

BURST GATE

LOW-PASS

LOOP FILTER

SUBCARRIER

INCREMENT

GENERATION

AND

DIVIDER

SUBCARRIER
GENERATION

FCTC

CSTD 1

RGB MATRIX

interpolation

dithering

SECAM

PROCESSING

DIT

CBR

CHBW0
CHBW1

CSTD 0

INCS

RES

TCK

TDI

POWER-ON

CONTROL

TEST

CONTROL

BLOCK

TDO

TRST

TMS

LUM

RTCO

n.c.

CLOCKS

sequential
UV signals

RGB

FEI

HREF

VPO
(9 : 0)

VPO
(15 : 10)

VBI DATA BYPASS

TUF

PHASE

DEMODULATOR

AMPLITUDE

DETECTOR

OFTS0
OFTS1
RGB888
OEYC
OEHV
FECO
VRLN
VSTA (8 : 0)
VSTO (8 : 0)

GPSW
RTSE1
RTSE0
VIPB
VLOF
COLO
COMPO

LEVEL

ADJUSTMENT,

BRIGHTNESS,

CONTRAST,

AND

SATURATION

CONTROL

GAIN

CONTROL

AND Y-DELAY

COMPENSATION

1998

May

Philips Semiconductors

Product specification

Enhanced V

ideo Input Processor (EVIP)

SAA71

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CREF

LLC

XTALI

XTAL

VREF

RTS0

SDA

SCL

IICSA

GPSW

I C BUS CONTROL

CLOCKS

SYNCHRONIZATION CIRCUIT

PREF

BYPS

APER0
APER1
VBLB

AUFD

HSB
HSS

FSEL

VTRC

STTC

FIDT

VNOI0
VNOI1
VTRC

VTRC

RTS1

MGC654

LLC2

HLCK

DDA0

SSA0

16
24

20
21

DAC6

AND

WEIGHTING

ADDING

BAND-PASS

VARIABLE

FILTER

CHROMINANCE

TRAP

PREFILTER

AMPLIFIER

MATCHING

CLOCK

LINE-LOCKED

GENERATOR

LOOP FILTER

DETECTOR

PHASE

COARSE

DETECTOR

PHASE

FINE

SYNC SLICER

SYNC

PREFILTER

LINE 21

TEXT

SLICER

CLOCK

CRYSTAL

GENERATOR

TIME

DISCRETE

OSCILLATOR 2

INTERFACE

I C-BUS

PROCESSOR

VERTICAL

COUNTER

GENERATION

CLOCK

CIRCUIT

LUMINANCE CIRCUIT

BPSS0
BPSS1
PREF

LUM

VBLB

CLOCK CIRCUIT

INCS

STAGE

HPLL

VTRC
EXFIL

BYTE1
BYTE2

STATUS

Fig.7 Luminance and sync processing.

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

BOUNDARY-SCAN TEST

The SAA7111A has built in logic and 5 dedicated pins to
support boundary-scan testing which allows board testing
without special hardware (nails). The SAA7111A follows
the

`IEEE Std. 1149.1 - Standard Test Access Port and

Boundary-Scan Architecture' set by the Joint Test Action
Group (JTAG) chaired by Philips.

The 5 special pins are Test Mode Select (TMS), Test
Clock (TCK), Test Reset (TRST), Test Data Input (TDI)
and Test Data Output (TDO).

The BST functions BYPASS, EXTEST, INTEST,
SAMPLE, CLAMP and IDCODE are all supported
(see Table 1). Details about the JTAG BST-TEST can be
found in the specification "

EEE Std. 1149.1". A file

containing the detailed Boundary-Scan Description
Language (BSDL) description of the SAA7111A is
available on request.

9.1

Initialization of boundary-scan circuit

The Test Access Port (TAP) controller of an IC should be
in the reset state (TEST_LOGIC_RESET) when the IC is
in functional mode. This reset state also forces the
instruction register into a functional instruction such as
IDCODE or BYPASS.

To solve the power-up reset, the standard specifies that
the TAP controller will be forced asynchronously to the
TEST_LOGIC_RESET state by setting the TRST pin
LOW.

9.2

Device identification codes

A Device Identification Register (DIR) is specified in

`IEEE

Std. 1149.1-1990 - IEEE Standard Test Access Port and
Boundary-Scan Architecture' (IEEE Std. 1149.1b-1994).
It is a 32-bit register which contains fields for the
specification of the IC manufacturer, the IC part number
and the IC version number. Its biggest advantage is the
possibility to check for the correct ICs mounted after
production and determination of the version number of
ICs during field service.

When the IDCODE instruction is loaded into the BST
instruction register, the identification register will be
connected between TDI and TDO of the IC.
The identification register will load a component specific
code during the CAPTURE_DATA_REGISTER state of
the TAP controller and this code can subsequently be
shifted out. At board level this code can be used to verify
component manufacturer, type and version number.
The device identification register contains 32-bits,
numbered 31 to 0, where bit 31 is the Most Significant Bit
(MSB) (nearest to TDI) and bit 0 is the Least Significant
Bit (LSB) (nearest to TDO); see Fig.11.

Table 1

BST instructions supported by the SAA7111A

INSTRUCTION

DESCRIPTION

BYPASS

This mandatory instruction provides a minimum length serial path (1 bit) between TDI and TDO
when no test operation of the component is required.

EXTEST

This mandatory instruction allows testing of off-chip circuitry and board level interconnections.

SAMPLE

This mandatory instruction can be used to take a sample of the inputs during normal operation of
the component. It can also be used to preload data values into the latched outputs of the
boundary-scan register.

CLAMP

This optional instruction is useful for testing when not all ICs have BST. This instruction addresses
the bypass register while the boundary-scan register is in external test mode.

IDCODE

This optional instruction will provide information on the components manufacturer, part number and
version number.

INTEST

This optional instruction allows testing of the internal logic (no support for customers available).

USER1

This private instruction allows testing by the manufacturer (no support for customers available).

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

11 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134); all ground pins connected together and all supply
pins connected together.

Note

1. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k

resistor.

12 CHARACTERISTICS

DDD

= 3.0 to 3.6 V; V

DDA

= 3.1 to 3.5 V; T

amb

= 25

�

C; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

DDD

digital supply voltage

0.5

+4.6

DDA

analog supply voltage

0.5

+4.6

i(A)

input voltage at analog inputs

0.5

DDA

+ 0.5

(4.6 max.)

o(A)

output voltage at analog output

0.5

DDA

+ 0.5

i(D)

input voltage at digital inputs and outputs

outputs in 3-state

0.5

+5.5

o(D)

output voltage at digital outputs

outputs active

0.5

DDD

+ 0.5

voltage difference between V

SSAall

and V

SSall

100

stg

storage temperature

+150

�

amb

operating ambient temperature

�

amb(bias)

operating ambient temperature under bias

+80

�

esd

electrostatic discharge all pins

note 1

2000

+2000

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies

DDD

digital supply voltage

3.0

3.3

3.6

DDD

digital supply current

digital power

0.21

DDA

analog supply voltage

3.1

3.3

3.5

DDA

analog supply current

AOSL = [1:0] = 00b;
AOUT not connected

analog power

0.17

A+D

analog and digital power

0.38

analog and digital power in
power-down mode

CE connected to ground
(since version 3)

0.02

Analog part

clamp

clamping current

= 0.9 V DC

�

3.5

�

i(p-p)

input voltage
(peak-to-peak value)

for normal video levels
[1 V (p-p)];

3 dB

termination 27/47

and

AC coupling required;
coupling capacitor = 22 nF

0.3

0.7

1.2

input impedance

clamping current off

200

input capacitance

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

channel crosstalk

= 5 MHz

Analog-to-digital converters

bandwidth

3 dB

MHz

diff

differential phase
(amplifier plus anti-alias
filter = bypass)

deg

diff

differential gain
(amplifier plus anti-alias
filter = bypass)

clkADC

ADC clock frequency

12.8

14.3

MHz

DLE

DC differential linearity
error

0.7

LSB

ILE

DC integral linearity error

LSB

Digital inputs

IL(SCL,SDA)

LOW level input voltage
pins SDA and SCL

0.5

+0.3V

DDD

HIGH level input voltage
pins SDA and SCL

0.7V

DDD

+ 0.5

IL(xtal)

LOW level CMOS input
voltage pin XTALI

0.3

+0.8

IH(xtal)

HIGH level CMOS input
voltage pin XTALI

2.0

DDD

+ 0.3

ILn

LOW level input voltage all
other inputs

0.3

+0.8

IHn

HIGH level input voltage
all other inputs

2.0

5.5

input leakage current

�

input capacitance

outputs at 3-state

i(n)

input capacitance all other
inputs

Digital outputs

OL(SCL,SDA)

LOW level output voltage
pins SDA and SCL

SDA/SCL at 3 mA (6 mA)
sink current

0.4 (0.6)

LOW level output voltage

DDD

= max; I

= 2 mA

0.4

HIGH level output voltage

DDD

= min, I

2 mA

2.4

DDD

+ 0.5

OL(clk)

LOW level output voltage
for clocks

0.5

+0.6

OH(clk)

HIGH level output voltage
for clocks

2.4

DDD

+ 0.5

output leakage current

at 3-state mode

�

FEI input timing

SU;DAT

input data set-up time

HD;DAT

input data hold time

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

Data and control output timing; note 1

output load capacitance

OHD;DAT

output hold time

= 15 pF

propagation delay

= 25 pF

PDZ

propagation delay to
3-state

Clock output timing (LLC and LLC2); note 2

L(LLC)

output load capacitance

cycle time

LLC

LLC2

LLC

duty factors for t

LLCH

LLC

and t

LLC2H

LLC2

= 25 pF

rise time LLC, LLC2

fall time LLC, LLC2

delay time LLC output to
LLC2 output

at 1.5 V;
LLC/LLC2 = 25 pF

Data qualifier output timing (CREF)

OHD;CREF

output hold time

= 15 pF

PD;CREF

propagation delay from
positive edge of LLC

= 25 pF

Clock input timing (XTALI)

XTALI

duty factor for t

XTALIH

XTALI

nominal frequency

Horizontal PLL

nominal line frequency

50 Hz field

15625

60 Hz field

15734

permissible static deviation

5.7

Subcarrier PLL

SCn

nominal subcarrier
frequency

PAL BGHI

4433619

NTSC M; NTSC-Japan

3579545

PAL M

3575612

PAL N

3582056

lock-in range

�

400

Crystal oscillator

nominal frequency

3rd harmonic; note 3

24.576

MHz

f/f

permissible nominal
frequency deviation

�

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

Notes

1. The levels must be measured with load circuits; 1.2 k

at 3 V (TTL load); C

= 50 pF.

2. The effects of rise and fall times are included in the calculation of t

OHD;DAT

, t

and t

PDZ

. Timings and levels refer to

drawings and conditions illustrated in Figs 15 and 16.

3. Order number: Philips 4322 143 05291.

Table 2

Processing delay

Note

1. Digital processing delay (LLC CLOCKS) for VBI data is defined in Fig.23 `Horizontal timing diagram'.

Crystal oscillator

nominal frequency

3rd harmonic; note 3

24.576

MHz

f/f

permissible nominal
frequency deviation

�

Tf/f

permissible nominal
frequency deviation with
temperature

�

RYSTAL SPECIFICATION

(X1)

amb(X1)

operating ambient
temperature

�

load capacitance

series resonance resistor

motional capacitance

1.5

�

20%

parallel capacitance

3.5

�

20%

FUNCTION

TYPICAL ANALOG DELAY

AI22

ADCIN (AOUT) (ns)

DIGITAL DELAY

ADCIN

VPO (LLC CLOCKS)

[YDEL(2 to 0) = 000]; note 1

Without amplifier or anti-alias filter

179

With amplifier, without anti-alias filter

With amplifier and anti-alias filter

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

Fig.19 FEI timing diagram (FEI sampling at CREF = LOW) for OFTS = 0, 1 or 2).

Timing is compatible with SAA7110; I

C-bus bit FECO = 0.

handbook, full pagewidth

LLC

CREF

HREF

VPO

SU;DAT

HD;DAT

to 3-state

MGC657

from 3-state

OHD;DAT

PDZ

FEI

Fig.20 Real time control output.

(1) Set to zero for one transmission, if a phase reset of the f

DTO is applied via I

C-bus bit CDTO. RTCO sequence is generated in LLC/4.

The HPLL increment represents the actual LFCO frequency (f

LFCO

�

4 = f

LLC

); 16 LSB from 20, upper four bits are fixed to 0100b.

Where: f

XTAL

= 24.576 MHz, word length DTO2 = 20 bits.

The f

increment represents the actual subcarrier frequency (related to the actual clock); 23 LSB from 24, MSB is 0b.

Where: word length DTO1 = 24 bits.

LFCO

INCR

HPLL

XTAL

�

word length DTO2

-------------------------------------------------

INCR

FSCPLL

XTAL

�

word length DTO1

-------------------------------------------------------

INCR

HPLL

----------------------------

�

handbook, full pagewidth

TIME SLOT:

BIT NO.:

transmitted once per line

11 10

SEQUENCE

RESERVED

INCRFSCPLL

MGC649

RESERVED

128

HIGH

LOW

INCRHPLL

RESERVED

DTO RESET

(1)

50 Hz fields: 235
60 Hz fields: 232

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

Fig.25 Vertical timing diagram for 60 Hz [nominal input signal VNL in normal mode (VNOI = 00b)].

(1) ODD is switched to output RTS0 via I

C-bus bit RTSE0 = 0.

(2) Line numbers in parenthesis refer to CCIR line counting.

(3) Additional VREF positions can be achieved via I

C-bus bits VCTR1 and VCTR0 (see Fig.9).

The luminance peaking and the chrominance trap are bypassed during VREF = 0 if I

C-bus bit VBLB is set to logic 1.

The chrominance delay line (chrominance-comb filter for NTSC, phase error correcting for PAL) is disabled during VREF = 0.

handbook, full pagewidth

(266)

(267)

(268)

(269)

(270)

(271)

(272)

(273)

(274)

(4)

(5)

(6)

(7)

(8)

(9)

(10)

(11)

(20)

(3)

HREF

(b) 2nd field

(a) 1st field

input CVBS

(2)

(1)

(525)

(21)

(22)

(283)

(284)

(265)

(264)

(263)

(262)

VRLN = 1

(3)

VRLN = 0

(3)

VRLN = 1

(3)

VRLN = 0

(3)

525

524

523

522

263

264

265

266

267

268

269

270

271

280

281

262

261

260

259

(285)

282

(2)

MGG070

520 x 2/LLC

RTS0 (ODD)

(1)

81 x 2/LLC

VREF

HREF

input CVBS

RTS0 (ODD)

(1)

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

Table 5

Power-on control sequence

15 OUTPUT FORMATS

Table 6

Output formats of the VPO bus (note 1)

INTERNAL POWER-ON CONTROL

SEQUENCE

PIN OUTPUT STATUS

FUNCTION

Directly after power-on
asynchronous reset

VPO15 to VPO0, RTCO, RTS0, RTS1,
GPSW, HREF, VREF, HS, VS, LLC,
LLC2 and CREF are in high-impedance
state

direct switching to high impedance for
20 to 200 ms

Synchronous reset sequence

LLC, LLC2, CREF, RTCO, RTS0,
RTS1, GPSW and SDA become active;
VPO15 to VPO0, HREF, VREF, HS and
VS are held in high-impedance state

internal reset sequence

Status after power-on control
sequence

VPO15 to VPO0, HREF, VREF, HS and
VS are held in high-impedance state

after power-on (reset sequence) a
complete I

C-bus transmission is

required

BUS

SIGNAL

411 (12-BIT)

422

(16-BIT)

(2)

CCIR-656 (8-BIT)

(3)

RGB (16-BIT)

(4)

RGB (24-BIT)

(4)

VPO15

VPO14

VPO13

VPO12

VPO11

VPO10

VPO9

VPO8

VPO7

VPO6

VPO5

VPO4

VPO3

VPO2

VPO1

VPO0

Pixel
order Y

note 5

note 6

Pixel
order UV

Data rates

LLC2

LLC

LLC2

C-bus

control
signals

OFTS0 = 0

OFTS0 = 1

OFTS0 = 0

OFTS1 = 1

OFTS1 = 0

OFTS1 = 1

OFTS1 = 0

RGB888 = X

RGB888 = 0

RGB888 = 1

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

Notes to Table 5

1. VPO bus allows connection to 5 V video data bus systems.

2. Values in accordance with CCIR 601.

3. Before and after the video data, video timing codes are inserted in accordance with CCIR 656.

a) VPO15 to VPO8 = VPO7 to VPO0 = CCIR 656 data if I

C-bus bit TCLO = 0

b) VPO15 to VPO8 = CCIR 656 data, VPO7 to VPO0 = 3-state if I

C-bus bit TCLO = 1.

4. During HREF = LOW RGB levels are set to 16 (10 hex). RGB 16-bit is achieved by dropping the LSBs of the 8-bit

signals (after dithering if desired).

5. CREF = 0 (see Fig.17).

6. CREF = 1 (see Fig.17).

Fig.28 VPO output signal range with default BCS settings.

Equations for modification to the YUV levels via BCS control I

C-bus bytes BRIG, CONT and SATN.

Luminance:

Chrominance:

It should be noted that the resulting levels are limited to 1 to 254 in accordance with CCIR-601/656 standard.

OUT

Int

CONT

------------------

128

�

(

)

�

BRIG

OUT

Int

SATN

-----------------

Cr Cb

128

�

(

)

�

128

CCIR Rec. 602 digital levels.

Y output range.

U output range (Cb).

V output range (Cr).

handbook, full pagewidth

LUMINANCE 100%

255

235

128

white

black

U-COMPONENT

255

240

212

128

blue 100%

blue 75%

yellow 75%

yellow 100%

colourless

V-COMPONENT

255

240

128

red 100%

red 75%

cyan 75%

cyan 100%

colourless

MGC634

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

16 APPLICATION INFORMATION

Fig.31 Application diagram.

handbook, full pagewidth

Q1(24.576 MHz)

VPO(15 : 0)

SCL

DDD

AI22

FEI

SDA

RTCO

AOUT

GPSW

RTS0

RTS1

RES

CREF

LLC2

LLC

HREF

SSA

DDA

SSA

VREF

SAA7111A

22 nF

100 nF

C11

C12

C13

C14

C15

1 k

n.c.

SSA2

SSS

SS1

SS2

SS3

SS4

SS5

IICSA

SSA1

SSA0

DDA0

DDA1

DDA2

DD1

DD2

DD3

DD4

DD5

TMS

TDI

TDO

TCK

TRST

C17

�

C16

1 nF

10 pF 10 pF

C18

1 k

XTAL

XTALI

MGG071

SSA

BST

n.c.

100 nF

22 nF

SSA

AI21

22 nF

SSA

AI12

22 nF

SSA

AI11

R10

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

Fig.32 Application diagram for RGB 24-bit output format.

C-bus control bits:

OFTS(1 : 0) = 00 (subaddress 10H, bits D7 and D6).

RGB888 = 1 (subaddress 12H, bit D3).

handbook, full pagewidth

OEN

e.g.

74HCT574

HREF

VSS

CLK

R (2 : 0)

R (7 : 0)

VDD

G (1 : 0)

G (7 : 0)

B (2 : 0)

B (7 : 0)

LLC2N

MGG073

LLC2

e.g. 74HCT240

B (7 : 3)

VPO (4 : 0)

VPO

(7 : 0)

SAA7111A

VPO (15 : 11)

R (7 : 3)

G (7 : 5)

G (4 : 2)

VPO (10 : 8)

VPO (7 : 5)

VREF

RTCO

RTS1

RTS0

GPSW

AOUT

LLC

CREF

RES

VPO

(15 : 8)

16.1

Layout hints

Use separate ground planes for analog and digital ground.
Connect these planes at one point directly under the
device, by using a zero

resistor. Use separate supply

lines for analog and digital supply. Place the supply
decoupling capacitors close to the supply pins.

Place the coupling (clamp) capacitors close to the analog
input pins. Place the termination resistors close to the
coupling capacitors. Care should be exercised concerning
the hidden layout capacitors around the crystal
application. To avoid reflection effects use serial resistors
in the clock, sync and data lines.

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

17 I

C-BUS DESCRIPTION

17.1

C-bus format

Table 7

Write procedure

Table 8

Read procedure (combined format)

Table 9

Description of I

C-bus format

Notes

1. If more than one byte DATA is transmitted then the auto-increment of the subaddress is performed.

2. During slave transmitter mode the SCL-LOW period may be extended by pulling SCL to LOW (in accordance with

the I

C-bus specification).

3. The I

C-bus subaddress 00 has to be initialized with 0 before being read.

SLAVE ADDRESS W

ACK-s

SUBADDRESS

ACK-s

DATA (N BYTES)

ACK-s

SLAVE ADDRESS W

ACK-s

SUBADDRESS

ACK-s

SLAVE ADDRESS R

ACK-s

DATA (N BYTES)

ACK-m

CODE

DESCRIPTION

START condition

repeated START condition

Slave address W

0100 1000b (IICSA = LOW) or 0100 1010b (IICSA = HIGH)

Slave address R

0100 1001b (IICSA = LOW) or 0100 1011b (IICSA = HIGH)

ACK-s

acknowledge generated by the slave

ACK-m

acknowledge generated by the master

Subaddress

subaddress byte; see Table 10

Data

data byte; see Table 10; note 1

STOP condition

X = LSB slave
address

read/write control bit; X = 0, order to write (the circuit is slave receiver); X = 1, order to read
(the circuit is slave transmitter)

Slave address

read = 49H or 4BH; note 2

write = 48H or 4AH

IICSA = 0 or 1

Subaddresses

00H chip version

read and write; note 3

01H reserved

02h to 05H front-end part

read and write

06H to 13H decoder part

read and write

14H reserved

15H to 17H decoder part

read and write

18H to 19H reserved

1AH to 1CH Line-21 text slicer part

read only

1DH to 1EH reserved

1FH status byte

read only

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

Table 10 I

C-bus receiver/transmitter overview

Note

1. All unused control bits must be programmed with logic 0.

SLAVE ADDRESS

READ

WRITE

IICSA

49H

4BH

48H

4AH

0
1

SUB-

ADDR

Chip version

ID07

ID06

ID05

ID04

ID03

ID02

ID01

ID00

Reserved

(1)

Analog input contr 1

FUSE1

FUSE0

GUDL2

GUDL1

GUDL0

MODE2

MODE1

MODE0

Analog input contr 2

(1)

HLNRS

VBSL

WPOFF

HOLDG

GAFIX

GAI28

GAI18

Analog input contr 3

GAI17

GAI16

GAI15

GAI14

GAI13

GAI12

GAI11

GAI10

Analog input contr 4

GAI27

GAI26

GAI25

GAI24

GAI23

GAI22

GAI21

GAI20

Horizontal sync start

HSB7

HSB6

HSB5

HSB4

HSB3

HSB2

HSB1

HSB0

Horizontal sync stop

HSS7

HSS6

HSS5

HSS4

HSS3

HSS2

HSS1

HSS0

Sync control

AUFD

FSEL

EXFIL

(1)

VTRC

HPLL

VNOI1

VNOI0

Luminance control

BYPS

PREF

BPSS1

BPSS0

VBLB

UPTCV

APER1

APER0

Luminance
brightness

BRIG7

BRIG6

BRIG5

BRIG4

BRIG3

BRIG2

BRIG1

BRIG0

Luminance contrast

CONT7

CONT6

CONT5

CONT4

CONT3

CONT2

CONT1

CONT0

Chroma saturation

SATN7

SATN6

SATN5

SATN4

SATN3

SATN2

SATN1

SATN0

Chroma Hue control

HUEC7

HUEC6

HUEC5

HUEC4

HUEC3

HUEC2

HUEC1

HUEC0

Chroma control

CDTO

CSTD2

CSTD1

CSTD0

DCCF

FCTC

CHBW1

CHBW0

Reserved

(1)

Format/delay control

OFTS1

OFTS0

HDEL1

HDEL0

VRLN

YDEL2

YDEL1

YDEL0

Output control 1

GPSW

CM99

FECO

COMPO

OEYC

OEHV

VIPB

COLO

Output control 2

RTSE1

RTSE0

TCLO

CBR

RGB888

DIT

AOSL1

AOSL0

Output control 3

VCTR1

VCTR0

CCTR1

CCTR0

BCHI1

BCHI0

BCLO1

BCLO0

Reserved

(1)

V_GATE1_START

VSTA7

VSTA6

VSTA5

VSTA4

VSTA3

VSTA2

VSTA1

VSTA0

V_GATE1_STOP

VSTO7

VSTO6

VSTO5

VSTO4

VSTO3

VSTO2

VSTO1

VSTO0

V_GATE1_MSB

(1)

VSTO8

VSTA8

Reserved

18-19

(1)

Text slicer status

(1)

F2VAL

F2RDY

F1VAL

F1RDY

Decoded bytes of
the text slicer

BYTE16 BYTE15 BYTE14

BYTE13

BYTE12

BYTE11

BYTE10

BYTE26 BYTE25 BYTE24

BYTE23

BYTE22

BYTE21

BYTE20

Reserved

1D-1E

(1)

Status byte

STTC

HLCK

FIDT

GLIMT

GLIMB

WIPA

SLTCA

CODE

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

17.2

C-bus detail

The I

C-bus receiver slave address is 48H/49H. Subaddresses 0F, 14, 18, 19, 1D and 1E are reserved; subaddress 01

is reserved for chip version.

17.2.1

UBADDRESS

Table 11 Chip version SA00; note 1

Note

1. X = reserved.

17.2.2

UBADDRESS

Table 12 Analog control 1 SA02; note 1

Notes

1. Mode select (see Figs 33 to 40).

2. For modes 0 to 3 use BYPS(SA09,D7) = 0 (chrominance trap active), for modes 4 to 7 use BYPS = 1 (chrominance

trap bypassed).

Table 13 Analog control 1 SA 02, D5 to D3 (see Fig.14)

FUNCTION

LOGIC LEVELS

ID07

ID06

ID05

ID04

ID03

ID02

ID01

ID00

Chip version

FUNCTION

(2)

CONTROL BITS D2 TO D0

MODE 2

MODE 1

MODE 0

Mode 0 : CVBS (automatic gain)

Mode 1 : CVBS (automatic gain)

Mode 2 : CVBS (automatic gain)

Mode 3 : CVBS (automatic gain)

Mode 4 : Y (automatic gain) + C (gain channel 2 fixed to GAI2 level)

Mode 5 : Y (automatic gain) + C (gain channel 2 fixed to GAI2 level)

Mode 6 : Y (automatic gain) + C (gain channel 2 adapted to Y gain)

Mode 7 : Y (automatic gain) + C (gain channel 2 adapted to Y gain)

DECIMAL VALUE

UPDATE HYSTERESIS FOR 9-BIT GAIN

CONTROL BITS D5 TO D3

GUDL 2

GUDL 1

GUDL 0

0....

off

....7

�

7 LSB

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

Fig.39 Mode 6 Y (automatic gain) + C

(gain channel 2 adapted to Y gain).

handbook, halfpage

MGC643

AI22
AI21

AI12
AI11

CHROMA

LUMA

AD2

AD1

Fig.40 Mode 7 Y (automatic gain) + C

(gain channel 2 adapted to Y gain).

handbook, halfpage

MGC644

AI22
AI21

AI12
AI11

CHROMA

LUMA

AD2

AD1

17.2.3

UBADDRESS

Table 15 Analog control 2 (AICO2) SA03

FUNCTION

BIT NAME

LOGIC LEVEL

CONTROL BIT

Static gain control channel 1 (GAI18) (see SA04)

Sign bit of gain control

GAI18

see Table 16

Static gain control channel 2 (GAI28) (see SA05)

Sign bit of gain control

GAI28

see Table 17

Gain control fix (GAFIX)

Automatic gain controlled by MODE 1 and MODE 0

GAFIX

Gain control is user programmable via GAI1 + GAI2

GAFIX

Automatic gain control integration (HOLDG)

AGC active

HOLDG

AGC integration hold (freeze)

HOLDG

White peak off (WPOFF)

White peak control active

WPOFF

White peak off

WPOFF

Vertical blanking select (VBSL)

Long vertical blanking

VBSL

Short vertical blanking

VBSL

HL not reference select (HLNRS)

Normal clamping by HL not

HLNRS

Reference select by HL not

HLNRS

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

17.2.4

UBADDRESS

Table 16 Gain control analog (AIC03); static gain control channel 1 GAI1 SA 04, D7 to D0

17.2.5

UBADDRESS

Table 17 Gain control analog (AIC04); static gain control channel 2 GAI2 SA 05, D7 to D0

17.2.6

UBADDRESS

Table 18 Horizontal sync begin SA 06, D7 to D0

DECIMAL

VALUE

GAIN

(dB)

SIGN

BIT

CONTROL BITS D7 TO D0

GAI18

GAI17

GAI16

GAI15

GAI14

GAI13

GAI12

GAI11

GAI10

0....

5.98

....255

256....

....511

5.98

DECIMAL

VALUE

GAIN

(dB)

SIGN BIT

(SA 03, D1)

CONTROL BITS D7 to D0

GAI28

GAI27

GAI26

GAI25

GAI24

GAI23

GAI22

GAI21

GAI20

0....

5.98

....255

256....

....511

5.98

DELAY TIME

(STEP SIZE = 8/LLC)

CONTROL BITS D7 to D0

HSB7

HSB6

HSB5

HSB4

HSB3

HSB2

HSB1

HSB0

128...

108

forbidden (outside available central counter range)

107...

...108 (50Hz)

...107 (60Hz)

109...127 (50Hz)

forbidden (outside available central counter range)

108...127 (60Hz)

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

17.2.7

UBADDRESS

Table 19 Horizontal sync stop SA 07, D7 to D0

17.2.8

UBADDRESS

Table 20 Sync control SA 08, D7 to D5, D3 to D0

DELAY TIME

(STEP SIZE = 8/LLC)

CONTROL BITS D7 to D0

HSS7

HSS6

HSS5

HSS4

HSS3

HSS2

HSS1

HSS0

128...

108

forbidden (outside available central counter range)

107...

...108 (50Hz)

...107 (60Hz)

109...127 (50Hz)

forbidden (outside available central counter range)

108...127 (60Hz)

FUNCTION

BIT NAME

LOGIC LEVEL

CONTROL BIT

Vertical noise reduction (VNOI)

Normal mode

VNOI1

VNOI0

Searching mode

VNOI1

VNOI0

Free running mode

VNOI1

VNOI0

Vertical noise reduction bypassed

VNOI1

VNOI0

Horizontal PLL (HPLL)

PLL closed

HPLL

PLL open, horizontal frequency fixed

HPLL

TV/VTR mode select (VTRC)

TV mode
(recommended for poor quality TV signals only)

VTRC

VTR mode (recommended as default setting)

VTRC

Extended loop filter (EXFIL)

Word width of the loop filter (LF2) amplification = 16-bit

EXFIL

Word width of the loop filter (LF2) amplification = 14-bit

EXFIL

Field selection (FSEL)

50 Hz, 625 lines

FSEL

60 Hz, 525 lines

FSEL

Automatic field detection (AUFD)

Field state directly controlled via FSEL

AUFD

Automatic field detection

AUFD

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

17.2.9

UBADDRESS

Table 21 Luminance control SA 09, D7 to D0

Note

1. Not to be used with bypassed chrominance trap.

FUNCTION

BIT NAME

LOGIC LEVEL

CONTROL BIT

Aperture factor (APER)

Aperture factor = 0

APER1

APER0

Aperture factor = 0.25

APER1

APER0

Aperture factor = 0.5

APER1

APER0

Aperture factor = 1.0

APER1

APER0

Update time interval for AGC value (UPTCV)

Horizontal update (once per line)

UPTCV

Vertical update (once per field)

UPTCV

Vertical blanking luminance bypass (VBLB)

Active luminance processing

VBLB

Luminance bypass during vertical blanking

VBLB

Aperture band pass (centre frequency) (BPSS)

Centre frequency = 4.1 MHz

BPSS1

BPSS0

Centre frequency = 3.8 MHz; note 1

BPSS1

BPSS0

Centre frequency = 2.6 MHz; note 1

BPSS1

BPSS0

Centre frequency = 2.9 MHz; note 1

BPSS1

BPSS0

Prefilter active (PREF)

Bypassed

PREF

Active

PREF

Chrominance trap bypass (BYPS)

Chrominance trap active; default for CVBS mode

BYPS

Chrominance trap bypassed; default for S-Video mode

BYPS

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

17.2.10 S

UBADDRESS

Table 22 Luminance brightness control BRIG7 to BRIG0 SA 0A

17.2.11 S

UBADDRESS

Table 23 Luminance contrast control CONT7 to CONT0 SA 0B

17.2.12 S

UBADDRESS

Table 24 Chrominance saturation control SATN7 to SATN0 SA 0C

17.2.13 S

UBADDRESS

Table 25 Chrominance hue control HUEC7 to HUEC0 SA 0D

OFFSET

CONTROL BITS D7 to D0

BRIG7

BRIG6

BRIG5

BRIG4

BRIG3

BRIG2

BRIG1

BRIG0

255 (bright)

128 (CCIR level)

0 (dark)

GAIN

CONTROL BITS D7 to D0

CONT7

CONT6

CONT5

CONT4

CONT3

CONT2

CONT1

CONT0

1.999 (maximum)

1.109 (CCIR level)

1.0

0 (luminance off)

1 (inverse luminance)

2 (inverse luminance)

GAIN

CONTROL BITS D7 to D0

SATN7

SATN6

SATN5

SATN4

SATN3

SATN2

SATN1

SATN0

1.999 (maximum)

1.0 (CCIR level)

0 (colour off)

1 (inverse

chrominance)

2 (inverse

chrominance)

HUE PHASE (DEG)

CONTROL BITS D7 to D0

HUEC7

HUEC6

HUEC5

HUEC4

HUEC3

HUEC2

HUEC1

HUEC0

+178.6....

....0....

....

180

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

17.2.14 S

UBADDRESS

Table 26 Chrominance control SA 0E

FUNCTION

BIT NAME

LOGIC

LEVEL

CONTROL

BIT

Chroma bandwidth (CHBW0 and CHBW1)

Small bandwidth (

620 kHz)

CHBW1

CHBW0

Nominal bandwidth (

800 kHz)

CHBW1

CHBW0

Medium bandwidth (

920 kHz)

CHBW1

CHBW0

Wide bandwidth (

1000 kHz)

CHBW1

CHBW0

Fast colour time constant (FCTC)

Nominal time constant

FCTC

Fast time constant

FCTC

Disable chrominance comb filter (DCCF)

Chrominance comb filter on (during VREF = 1) (see Figs 24 and 25)

DCCF

Chrominance comb filter off

DCCF

Colour standard (CSTD0 to CSTD2); logic levels 100, 110 and 111 are reserved, do not use

Colour standard control automatic switching between PAL BGHI and
NTSC M (NTSC-Japan with special level adjustment; luminance
brightness subaddress 0A = 95H, luminance contrast
subaddress 0BH = 48H)

CSTD2

CSTD1

CSTD0

Colour standard control automatic switching between NTSC 4.43 (50 Hz)
and PAL 4.43 (60 Hz)

CSTD2

CSTD1

CSTD0

Colour standard control automatic switching between PAL N and
NTSC 4.43 (60 Hz)

CSTD2

CSTD1

CSTD0

Colour standard control automatic switching between NTSC N and
PAL M

CSTD2

CSTD1

CSTD0

Colour standard control automatic switching between SECAM and
PAL 4.43 (60 Hz)

CSTD2

CSTD1

CSTD0

Clear DTO (CDTO)

Disabled

CDTO

Every time CDTO is set, the internal subcarrier DTO phase is reset to 0

�

and the RTCO output generates a logic 0 at time slot 68 (see RTCO
description Fig.20). So an identical subcarrier phase can be generated by
an external device (e.g. an encoder).

CDTO

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

17.2.15 S

UBADDRESS

Table 27 Format/delay control SA 10

Table 28 VREF pulse position and length VRLN SA 10 (D3)

Notes

1. Additional VREF positions can be achieved via I

C-bus bits VCTR1 and VCTR0 (see Fig.9).

2. The numbers given in parenthesis refer to CCIR line counting.

Table 29 Fine position of HS HDEL0 and HDEL1 SA 10

Table 30 Output format selection OFTS0 and OFTS1 SA 10

LUMINANCE DELAY COMPENSATION

(STEPS IN 2/LLC)

CONTROL BITS D2 to D0

YDEL2

YDEL1

YDEL0

4...

...0...

...3

VRLN

VREF at 60 Hz 525 LINES

(1)

VREF at 50 Hz 625 LINES

(1)

Length

240

242

286

288

Line number

first

last

first

last

first

last

first

last

Field 1

(2)

19 (22)

258 (261)

18 (21)

259 (262)

309

310

Field 2

(2)

282 (285)

521 (524)

281 (284)

522 (525)

337

622

336

623

FINE POSITION OF HS WITH A STEP SIZE

OF 2/LLC

CONTROL BITS D5 and D4

HDEL1

HDEL0

FORMATS

CONTROL BITS D7 and D6

OFTS1

OFTS0

RGB (5, 6 and 5), RGB (8, 8 and 8)
(dependent on control bit RGB888); see
Table 32

YUV 422 16 bits

YUV 411 12 bits

YUV CCIR-656 8 bits

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

17.2.16 S

UBADDRESS

Table 31 Output control 1 SA 11

FUNCTION

BIT NAME

LOGIC LEVEL

CONTROL BIT

Colour on (COLO)

Automatic colour killer

COLO

Colour forced on

COLO

Decoder VIP bypassed (VIPB)

DMSD data to YUV output

VIPB

ADC data to YUV output; dependent on mode settings

VIPB

Output enable horizontal/vertical sync (OEHV)

HS, HREF, VREF and VS high-impedance inputs

OEHV

Outputs HS, HREF, VREF and VS active

OEHV

Output enable YUV data (OEYC)

VPO-bus high-impedance inputs

OEYC

Output VPO-bus active

OEYC

Inverse composite blank (COMPO)

VREF is vertical reference

COMPO

VREF is inverse composite blank

COMPO

FEI control (FECO)

FEI sampling at CREF = LOW
(SAA7110 compatible); (see Fig.19)

FECO

FEI sampling at CREF = HIGH

FECO

Compatibility to SAA7199 (CM99)

Default value

CM99

To be set if SAA7199 (digital encoder) is used for
re-encoding in conjunction with RTCO

CM99

General purpose switch (GPSW)

Switches directly pin 64 GPSW

GPSW

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

17.2.17 S

UBADDRESS

Table 32 Output control 2 SA 12, D7 to D6, D4 to D0

FUNCTION

BIT NAME

LOGIC LEVEL

CONTROL BIT

Analog test select (AOSL)

AOUT connected to internal test point 1

AOSL1

AOSL0

AOUT connected to input AD1

AOSL1

AOSL0

AOUT connected to input AD2

AOSL1

AOSL0

AOUT connected to internal test point 2

AOSL1

AOSL0

Dithering (noise shaping) control (DIT)

Dithering off

DIT

Dithering on

DIT

RGB output format selection (RGB888)

RGB (5, 6 and 5)

RGB888

RGB (8, 8 and 8)

RGB888

Chrominance interpolation filter function (CBR)

Cubic interpolation (default)

CBR

Linear interpolation (lower bandwidth)

CBR

3-state control VPO7 to VPO0 (TCLO)

VPO7 to VPO0 depends on OEYC, FEI only (default)
(see Figs 18, 19 and 22)

TCLO

VPO7 to VPO0 in 3-state [and OFTS (1 : 0) = 3]
(see Tables 3 and 6)

TCLO

Real time outputs mode select (RTSE0)

ODD switched to output pin 40

RTSE0

VL switched to output pin 40

RTSE0

Real time outputs mode select (RTSE1)

PLIN switched to output pin 39

RTSE1

HL switched to output pin 39

RTSE1

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

17.2.18 S

UBADDRESS

Table 33 Output control 3 SA 13

FUNCTION

BIT NAME

LOGIC LEVEL

CONTROL BIT

Bypass control LOW for VPO7 to VPO0

No bypass

BCLO1

BCLO0

Permanent bypass

BCLO1

BCLO0

Bypass controlled by V_GATE

BCLO1

BCLO0

Bypass controlled by delayed V_GATE

BCLO1

BCLO0

Bypass control HIGH for VPO15 to VPO8

No bypass

BCHI1

BCHI0

Permanent bypass

BCHI1

BCHI0

Bypass controlled by V_GATE

BCHI1

BCHI0

Bypass controlled by delayed V_GATE

BCHI1

BCHI0

Clock Reference Output Control

CREF is independent of VREF

CCTR1

CCTR0

CREF is LOW if VREF = 0

CCTR1

CCTR0

CREF is HIGH if VREF = 0

CCTR1

CCTR0

CREF always = 1

CCTR1

CCTR0

Vertical Reference Output Control (VREF)

Internal VREF

VCTR1

VCTR0

VREF_CCIR

VCTR1

VCTR0

Programmable V_GATE

VCTR1

VCTR0

Delayed programmable V_GATE

VCTR1

VCTR0

1998

May

Philips Semiconductors

Product specification

Enhanced V

ideo Input Processor (EVIP)

SAA71

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17.2.19 S

UBADDRESS

Table 34 Start of decoded data on VPO-port SA 15; note 1

Notes

1. Start of decoded data on VPO-port (end of bypassed region; start of VREF if selected by VCTR1 and VCTR0; see Figs 8 and 10).

2. Line numbers in brackets refer to CCIR line counting.

FIELD

FRAME

LINE

(2)

COUNTING

DECIMA

L VALUE

MSB

(SA 17,

D0)

CONTROL BITS D7 to D0

VSTA8

VSTA7

VSTA6

VSTA5

VSTA4

VSTA3

VSTA2

VSTA1

VSTA0

50 Hz

1st

312

2nd

314

1st

0....

2nd

315

1st

312

....310

2nd

625

60 Hz

1st

1 (4)

262

2nd

264 (267)

1st

2 (5)

0....

2nd

265 (268)

1st

262 (265)

....260

2nd

525 (3)

1998

May

Philips Semiconductors

Product specification

Enhanced V

ideo Input Processor (EVIP)

SAA71

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17.2.20 S

UBADDRESS

ABLE

35 S

TOP OF DECODED DATA ON

VPO-

PORT

SA 16;

NOTE

OTES

1. S

TOP OF DECODED DATA ON

VPO-

PORT

(

BEGIN OF BYPASSED REGION

;

STOP OF

VREF

IF SELECTED BY

VCTR1

AND

VCTR0;

SEE

IGS

AND

10).

2. L

INE NUMBERS IN BRACKETS REFER TO

CCIR

LINE COUNTING

17.2.21 S

UBADDRESS

Table 36 Sign bits of the VBI-data stream control

FIELD

FRAME

LINE

(2)

COUNTING

DECIMAL

VALUE

MSB

(SA 17, D0)

CONTROL BITS D7 to D0

VSTO8

VSTO7

VSTO6

VSTO5

VSTO4

VSTO3

VSTO2

VSTO1

VSTO0

50 Hz

1st

312

2nd

314

1st

0....

2nd

315

1st

312

....310

2nd

625

60 Hz

1st

1 (4)

262

2nd

264 (267)

1st

2 (5)

0....

2nd

265 (268)

1st

262 (265)

....260

2nd

525 (3)

FUNCTION

BIT NAME

LOGIC LEVEL

CONTROL BIT

VBI-data stream start (VSTA8); see SA 15

Sign bit VBI-data stream start

VSTA8

see Table 34

VBI-data stream stop (VSTO8); see SA 16

Sign bit VBI-data stream stop

VSTO8

see Table 35

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

17.2.22 S

UBADDRESS

1A (

READ

ONLY REGISTER

)

Table 37 Line-21 text slicer status SA 1A, D3 to D0

17.2.23 S

UBADDRESS

1B (

READ

ONLY REGISTER

)

Table 38 First decoded data byte of the text slicer SA 1B

17.2.24 S

UBADDRESS

1C (

READ

ONLY REGISTER

)

Table 39 Second decoded data byte of the text slicer SA 1C

17.2.25 S

UBADDRESS

1F (

READ

ONLY REGISTER

)

Table 40 Status byte SA 1F

C-BUS

STATUS BIT

NAME

FUNCTION

STATUS BIT

F1RDY

new data on field 1 has been acquired (for asynchronous reading); active HIGH

F1VAL

line-21 of field 1 carries valid data; active HIGH

F2RDY

new data on field 2 has been acquired (for asynchronous reading); active HIGH

F2VAL

line-21 of field 2 carries valid data; active HIGH

C-BUS

TEXT DATA

BITS

FUNCTION

DATA BITS

BYTE1 (6 to 0)

data bit 6 to 0 of first data byte

D6 to D0

parity error flag bit; bit goes HIGH when a parity error has occurred

C-BUS

TEXT DATA

BITS

FUNCTION

DATA BITS

BYTE2 (6 to 0)

data bit 6 to 0 of second data byte

D6 to D0

parity error flag bit; bit goes HIGH when a parity error has occurred

C-BUS

STATUS BIT

NAME

FUNCTION

STATUS BIT

CODE

colour signal in accordance with selected standard has been detected; active
HIGH

SLTCA

slow time constant active in WIPA-mode; active HIGH

WIPA

white peak loop is activated; active HIGH

GLIMB

gain value for active luminance channel is limited [min (bottom)]; active HIGH

GLIMT

gain value for active luminance channel is limited [max (top)]; active HIGH

FIDT

identification bit for detected field frequency; LOW = 50 Hz, HIGH = 60 Hz

HLCK

status bit for locked horizontal frequency; LOW = locked, HIGH = unlocked

STTC

status bit for horizontal phase loop; LOW = TV time-constant,
HIGH = VTR time-constant

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

Table 41 I

C-bus start set-up values

Note

1. All X values must be set to LOW.

SUB

(HEX)

FUNCTION

NAME

(1)

VALUES (BIN)

(HEX)

START

chip version

ID07 to ID00; see Table 9

read only

reserved

analog input control 1

FUSE1 and FUSE0, GUDL2 to GUDL0,
MODE2 to MODE0

analog input control 2

X, HLNRS, VBSL, WPOFF, HOLDG,
GAFIX, GAI28 and GAI18

analog input control 3

GAI17 to GAI10

analog input control 4

GAI27 to GAI20

horizontal sync start

HSB7 to HSB0

horizontal sync stop

HSS7 to HSS0

sync control

AUFD, FSEL, EXFIL, X, VTRC, HPLL,
VNOI1 and VNOI0

luminance control

BYPS, PREF, BPSS1 and BPSS0, VBLB,
UPTCV, APER1 and APER0

luminance brightness

BRIG7 to BRIG0

luminance contrast

CONT7 to CONT0

chrominance saturation SATN7 to SATN0

chroma hue control

HUEC7 to HUEC0

chrominance control

CDTO, CSTD2 to CSTD0, DCCF, FCTC,
CHBW1 and CHBW0

reserved

format/delay control

OFTS1 and OFTS0, HDEL1 and HDEL0,
VRLN, YDEL2 to YDEL0

output control 1

GPSW, CM99, FECO, COMPO, OEYC,
OEHV, VIPB, and COLO

output control 2

RTSE1 and RTSE0, TCLO, CBR,
RGB888 DIT, AOSL1 and AOSL0

output control 3

CCTR1 and CCTR0, BCHI1 and BCHI0,
BCLO1 and BCLO0, VCTR1 and VCTR0

reserved

VBI-data stream start

VSTA7 to VSTA0

VBI-data stream stop

VSTO7 to VSTO0

MSBs for VBI control

X, X, X, X, X, X, VSTO8, and VSTA8

18-19

reserved

text slicer status

0, 0, 0, 0, F2VAL, F2RDY,
F1VAL, and F1RDY

read only register

decoded bytes of the
text slicer

P1, BYTE1 (6 to 0)

P2, BYTE2 (6 to 0)

1D-1E reserved

status byte

STTC, HLCK, FIDT, GLIMT, GLIMB,
WIPA, SLTCA and CODE

read only register

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

21 SOLDERING

21.1

Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"IC Package Databook" (order code 9398 652 90011).

21.2

Reflow soldering

Reflow soldering techniques are suitable for all LQFP and
QFP packages.

The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

"Quality

Reference Handbook" (order code 9397 750 00192).

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250

�

21.3

Wave soldering

Wave soldering is not recommended for LQFP and QFP
packages. This is because of the likelihood of solder
bridging due to closely-spaced leads and the possibility of
incomplete solder penetration in multi-lead devices.

CAUTION

Wave soldering is NOT applicable for all LQFP and
QFP packages with a pitch (e) equal or less than
0.5 mm.

If wave soldering cannot be avoided, for LQFP and
QFP packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:

�

A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.

�

The footprint must be at an angle of 45

�

to the board

direction and must incorporate solder thieves
downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260

�

C, and

maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150

�

C within

6 seconds. Typical dwell time is 4 seconds at 250

�

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

21.4

Repairing soldered joints

Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300

�

C. When

using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320

�

1998 May 15

Philips Semiconductors

Product specification

Enhanced Video Input Processor (EVIP)

SAA7111A

22 DEFINITIONS

23 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

24 PURCHASE OF PHILIPS I

C COMPONENTS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I

C components conveys a license under the Philips' I

C patent to use the

components in the I

C system provided the system conforms to the I

C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

Internet: http://www.semiconductors.philips.com

Philips Semiconductors � a worldwide company

� Philips Electronics N.V. 1998

SCA60

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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Printed in The Netherlands

655102/1200/04/pp72

Date of release: 1998 May 15

Document order number:

9397 750 03118

Электронный компонент: SAA7111AH/03

Document Outline