1998 May 15

Philips Semiconductors

Product specification

Video Input Processor (VIP)

SAA7111

CONTENTS

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

QUICK REFERENCE DATA

ORDERING INFORMATION

BLOCK DIAGRAM

PINNING

FUNCTIONAL DESCRIPTION

8.1

Analog input processing

8.2

Analog control circuits

8.2.1

Clamping

8.2.2

Gain control

8.3

Chrominance processing

8.4

Luminance processing

8.5

RGB matrix

8.6

VPO-bus (digital outputs)

8.7

Synchronization

8.8

Clock generation circuit

8.9

Power-on reset and CE input

8.10

RTCO output

8.11

The Line-21 text slicer

8.11.1

Suggestions for I

C-bus interface of the display

software reading line-21 data

GAIN CHARTS

LIMITING VALUES

CHARACTERISTICS

TIMING DIAGRAMS

CLOCK SYSTEM

13.1

Clock generation circuit

13.2

Power-on control

OUTPUT FORMATS

APPLICATION INFORMATION

15.1

Layout hints

C-BUS DESCRIPTION

16.1

C-bus format

16.2

C-bus detail

16.2.1

Subaddress 00

16.2.2

Subaddress 02

16.2.3

Subaddress 03

16.2.4

Subaddress 04

16.2.5

Subaddress 05

16.2.6

Subaddress 06

16.2.7

Subaddress 07

16.2.8

Subaddress 08

16.2.9

Subaddress 09

16.2.10

Subaddress 0A

16.2.11

Subaddress 0B

16.2.12

Subaddress 0C

16.2.13

Subaddress 0D

16.2.14

Subaddress 0E

16.2.15

Subaddress 10

16.2.16

Subaddress 11

16.2.17

Subaddress 12

16.2.18

Subaddress 1A (read-only register)

16.2.19

Subaddress 1B (read-only register)

16.2.20

Subaddress 1C (read-only register)

16.2.21

Subaddress 1F (read-only register)

FILTER CURVES

17.1

Anti-alias filter curve

17.2

Luminance filter curves

17.3

Chrominance filter curves

C START SET-UP

PACKAGE OUTLINE

SOLDERING

20.1

Introduction

20.2

Reflow soldering

20.3

Wave soldering

20.3.1

PLCC

20.3.2

QFP

20.3.3

Method (PLCC and QFP)

20.4

Repairing soldered joints

DEFINITIONS

LIFE SUPPORT APPLICATIONS

PURCHASE OF PHILIPS I

C COMPONENTS

1998 May 15

Philips Semiconductors

Product specification

Video Input Processor (VIP)

SAA7111

FEATURES

�

Four analog inputs, internal analog source selectors,
e.g. 4

�

CVBS or 2

�

Y/C or (1

�

Y/C and 2

�

CVBS)

�

Two analog preprocessing channels

�

Fully programmable static gain for the main channels or
automatic gain control for the selected CVBS or Y/C
channel

�

Switchable white peak control

�

Two built-in analog anti-aliasing filters

�

Two 8-bit video CMOS analog-to-digital converters
(ADCs)

�

On-chip clock generator

�

Line-locked system clock frequencies

�

Digital PLL for H-sync processing and clock generation

�

Requires only one crystal (24.576 MHz) for all standards

�

Horizontal and vertical sync detection

�

Automatic detection of 50/60 Hz field frequency and
automatic switching between standards PAL and NTSC

�

Luminance and chrominance signal processing for
PAL BGHI, PAL N, PAL M, NTSC M, NTSC N and
NTSC 4.43

�

User programmable luminance peaking or aperture
correction

�

Cross-colour reduction for NTSC by chrominance comb
filtering

�

PAL delay line for correcting PAL phase errors

�

Real time status information output (RTCO)

�

Brightness Contrast Saturation (BCS) control on-chip

�

The YUV (CCIR-601) bus supports a data rate of:

� 864

�

= 13.5 MHz for 625 line sources

� 858

�

= 13.5 MHz for 525 line sources.

�

Data output streams for 16, 12 or 8-bit width with the
following formats:

� 411 YUV (12-bit)

� 422 YUV (16-bit)

� 422 YUV [CCIR-656] (8-bit)

� 565 RGB (16-bit) with dither

� 888 RGB (24-bit) with special application.

�

720 active samples per line on the YUV bus

�

One user programmable general purpose switch on an
output pin

�

Built in line-21 text slicer

�

Power-on control

�

Two switchable outputs for the digitized CVBS or Y/C
input signals AD1 (7 to 0) and AD2 (7 to 0) via the
I

C-bus

�

Chip enable function (reset for the clock generator)

�

Compatible with memory-based features (line-locked
clock)

�

Boundary scan test circuit complies with the
IEEE Std. 1149.1

1990 (ID-Code = 0 7111 02 B)

�

C-bus controlled (full read-back ability by an external

controller).

APPLICATIONS

�

Desktop video

�

Multimedia

�

Digital television

�

Image processing

�

Video phone.

GENERAL DESCRIPTION

The Video Input Processor (VIP) is a combination of a
two-channel analog preprocessing circuit including source
selection, anti-aliasing filter and ADC, an automatic clamp
and gain control, a Clock Generation Circuit (CGC), a
digital multi-standard decoder (PAL BGHI, PAL M, PAL N,
NTSC M and NTSC N), a brightness/contrast/saturation
control circuit and a colour space matrix (see Fig.1).

The CMOS circuit SAA7111, analog front-end and digital
video decoder, is a highly integrated circuit for desktop
video applications. The decoder is based on the principle
of line-locked clock decoding and is able to decode the
colour of PAL and NTSC signals into CCIR-601
compatible colour component values. The SAA7111
accepts as analog inputs CVBS or S-video (Y/C) from
TV or VTR sources. The circuit is I

C-bus controlled.

1998 May 15

Philips Semiconductors

Product specification

Video Input Processor (VIP)

SAA7111

BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

SDA

XTAL

XTALI

RES

IICSA

TRST

TDI

CLOCK

INTERFACE

I C-BUS

SYNCHRONIZATION

CIRCUIT

LUMINANCE

CIRCUIT

SAA7111

CHROMINANCE

CIRCUIT

I C-BUS

CONTROL

CLOCKS

(31) 42

ANALOG

PROCESSING

AND

ANALOG-TO-

DIGITAL

CONVERSION

AI11
AI12

AI21

AI22

21 (12)

19 (10)

17 (8)

15 (6)

AD2

AD1

ANALOG

CONTROL

CON

FORMATTER

OUTPUT

CONTROL

AND

BRIGHTNESS

CONTRAST

SATURATION

BYPASS

GENERATION

CIRCUIT

POWER-ON

CONTROL

(30)
41

(27)
38

(17)
26

(29)
40

(28)
39

(60)
3

(15)
24

(16)
25

(24)
33

RTS0

(55) 66

(54) 65

(21) 30

(22) 31

(20) 29

LLC2

CREF

(52) 63

45 to 50
53 to 62

(34 to 39)
(42 to 51)

(53) 64

FEI

HREF

VPO
(0 : 15)

GPSW

(63) 6

(62) 5

(61) 4

(23) 32

n.c.

7,8,9 (64)

n.c.

10,36,
37

22 (13)

AOUT

23 (14)

RTCO

MGC653

RTS1

LLC

SSA0

DDA0

SS1-5

DD1-5

(57,41,33,25,18)
68,52,44,34,27

(56,40,32,26,19)
67,51,43,35,28

SSA1-2

DDA1-2

18,14 (9,5)

20,16 (11,7)

Y/CVBS

C/CVBS

TCK

2 (59)

13 (4)

1 (58)

11 (2)

12 (3)

TMS

TDO

VREF

YUV-to-RGB

CONVERSION

AND

PROCESSING

LFCO

TEST

CONTROL

BLOCK

FOR

BOUNDARY
SCAN TEST

AND

SCAN TEST

SCL

The pin numbers given in parenthesis refer to the 64-pin package.

1998 May 15

Philips Semiconductors

Product specification

Video Input Processor (VIP)

SAA7111

PINNING

SYMBOL

PINS

I/O

DESCRIPTION

PLCC68

QFP64

TRST

Test reset input not (active LOW), for boundary scan test;
notes 1, 2, 3 and 4.

TCK

Test clock input for boundary scan test; note 3.

RTCO

Real time control output: contains information about actual system
clock frequency, subcarrier frequency and phase and PAL sequence.

IICSA

C-bus slave address select input; 0

48H for write, 49H for read,

4AH for write, 4BH for read.

SDA

I/O

C-bus serial data input/output.

SCL

I/O

C-bus serial clock input/output.

n.c.

Not connected.

n.c.

Not connected.

n.c.

Not connected.

n.c.

Not connected.

TDO

Test data output for boundary scan test; note 3.

TDI

Test data input for boundary scan test; note 3.

TMS

Test mode select input for boundary scan test or scan test; note 3.

SSA2

GND

Ground for analog supply voltage channel 2.

AI22

Analog input 22.

DDA2

Positive supply voltage (+5 V) for analog channel 2.

AI21

Analog input 21.

SSA1

GND

Ground for analog supply voltage channel 1.

AI12

Analog input 12.

DDA1

Positive supply voltage (+5 V) for analog channel 1.

AI11

Analog input 11.

SSS

GND

Substrate (connected to analog ground).

AOUT

Analog test output; for testing the analog input channels.

DDA0

Positive supply voltage (+5 V) for internal CGC.

SSA0

GND

Ground for internal CGC.

VREF

Vertical reference output signal (I

C-bit COMPO = 0) or inverse

composite blank signal (I

C-bit COMPO = 1) (enabled via I

C-bit

OEHV).

DD5

Positive digital supply voltage 5 (+5 V).

SS5

GND

Digital ground for positive supply voltage 5.

LLC

Line-locked system clock output (27 MHz).

LLC2

Line-locked clock

output (13.5 MHz).

CREF

Clock reference output: this is a clock qualifier signal distributed by
the CGC for a data rate of LLC2. Using CREF all interfaces on the
VPO-bus are able to generate a bus timing with identical phase.
If CCIR-656 format is selected (OFTS0 = 1 and OFTS1 = 1) an
inverse composite blank signal (pixel qualifier) is provided on this pin.

1998 May 15

Philips Semiconductors

Product specification

Video Input Processor (VIP)

SAA7111

RES

Reset output (active LOW); sets the device into a defined state.
All data outputs are in high impedance state. The I

C-bus is reset

(waiting for start condition) note 4.

Chip enable; connection to ground forces a reset.

DD4

Positive digital supply voltage 4 (+5 V).

SS4

GND

Digital ground for positive supply voltage 4.

n.c.

Not connected.

n.c.

Not connected.

Horizontal sync output signal (programmable); the positions of the
positive and negative slopes are programmable in 8 LLC increments
over a complete line (equals 64

�

s) via I

C-bus bytes HSB and HSS.

Fine position adjustment in 2 LLC increments can be performed via
I

C-bits HDEL1 and HDEL0.

RTS1

Two functions output; controlled by I

C-bit RTSE1.

RTSE1 = 0: PAL line identifier (LOW = PAL line); indicates the
inverted and non-inverted R

Y component for PAL signals.

RTSE1 = 1: H-PLL locked indicator; a high state indicates that the
internal horizontal PLL has locked.

RTS0

Two functions output; controlled by I

C-bit RTSE0.

RTSE0 = 0: odd/even field identification (HIGH = odd field).
RTSE0 = 1: vertical locked indicator; a HIGH state indicates that the
internal VNL has locked.

Vertical sync output signal (enabled via I

C-bit OEHV); this signal

indicates the vertical sync with respect to the YUV output. The HIGH
period of this signal is approximately six lines if the vertical noise
limiter (VNL) function is active. The positive slope contains the phase
information for a deflection controller.

HREF

Horizontal reference output signal (enabled via I

C-bit OEHV); this

signal is used to indicate data on the digital YUV bus. The positive
slope marks the beginning of a new active line. The HIGH period of
HREF is 720 Y samples long. HREF can be used to synchronize data
multiplexer/demultiplexers. HREF is also present during the vertical
blanking interval.

SS3

GND

Digital ground for positive supply voltage 3.

DD3

Positive digital supply voltage 3 (+5 V).

VPO (15 to 10)

45 to 50

34 to 39

Digital VPO-bus (Video Port Out) output signal; higher bits of the
16-bit YUV-bus or the 16-bit RGB-bus output signal. The output data
rate, the format and multiplexing scheme of the VPO-bus are
controlled via I

C-bits OFTS0 and OFTS1. With I

C-bit VIPB = 1 the

six MSBs of the digitized input signal (AD1 [7 to 2]) are connected to
these outputs.

SS2

GND

Digital ground for positive supply voltage 2.

DD2

Positive digital supply voltage 2 (+5 V).

SYMBOL

PINS

I/O

DESCRIPTION

PLCC68

QFP64

1998 May 15

Philips Semiconductors

Product specification

Video Input Processor (VIP)

SAA7111

Notes

1. For board design without boundary scan implementation (pin compatibility with the SAA7110) connect the TRST pin

to ground.

2. This pin provides easy initialization of BST circuit. TRST can be used to force the TAP (Test Access Port) controller

to the Test-Logic-Reset state (normal operation) at once.

3. In accordance with the

IEEE1149.1 standard the pads TCK, TDI, TMS and TRST are input pads with an internal

pull-up transistor and TDO a 3-state output pad.

4. All pin names that carry an `overscore' have been renamed due to Philips pin name conventions. In previous data

sheet versions these pins were marked by the suffix `N', e.g. TRST = TRSTN.

VPO (9 to 0)

53 to 62

42 to 51

Digital VPO-bus output signal; lower bits of the 16-bit YUV-bus or the
16-bit RGB-bus output signal. The output data rate, the format and
multiplexing schema of the VPO-bus are controlled via I

C-bits

OFTS0 and OFTS1. With I

C-bit VIPB = 1 the digitized input signals

(AD1 [1 and 0] and AD2 [7 to 0]) are connected to these outputs.

FEI

Fast enable input signal (active LOW); this signal is used to control
fast switching on the digital YUV-bus. A HIGH at this input forces the
IC to set its Y and UV outputs to the high impedance state; note 4.

GPSW

General purpose switch output; the state of this signal is set via
I

C-bus control and the levels are TTL compatible.

XTAL

Second output terminal of crystal oscillator; not connected if external
clock signal is used.

XTALI

Input terminal for 24.576 MHz crystal oscillator or connection of
external oscillator with CMOS compatible square wave clock signal.

SS1

GND

Digital ground for positive supply voltage 1.

DD1

Positive digital supply voltage 1 (+5 V).

SYMBOL

PINS

I/O

DESCRIPTION

PLCC68

QFP64

1998 May 15

Philips Semiconductors

Product specification

Video Input Processor (VIP)

SAA7111

FUNCTIONAL DESCRIPTION

8.1

Analog input processing

The SAA7111 offers four analog signal inputs, two analog
main channels with clamp circuit, analog amplifier,
anti-alias filter and video CMOS ADC (see Fig.6).

8.2

Analog control circuits

The anti-alias filters are adapted to the line-locked clock
frequency with help from a filter control. During the vertical
blanking, time gain and clamping control are frozen.

8.2.1

LAMPING

The clamp control circuit controls the correct clamping of
the analog input signals. The coupling capacitor is also
used to store and filter the clamping voltage. An internal
digital clamp comparator generates the information with
respect to clamp-up or clamp-down. The clamping levels
for the two ADC channels are fixed for luminance (60) and
chrominance (128). Clamping time in normal use is set
with the HCL pulse at the back porch of the video signal.

8.2.2

AIN CONTROL

Signal (white) peak control limits the gain at signal
overshoots. The flow charts (see Figs 10 and 11) show
more details of the AGC. The influence of supply voltage
variation within the specified range is automatically
eliminated by clamp and automatic gain control.

The gain control circuit receives (via the I

C-bus) the static

gain levels for the two analog amplifiers or controls one of
these amplifiers automatically via a built-in automatic gain

Fig.4

Analog line with clamp (HCL) and gain
range (HSY).

handbook, halfpage

HCL

MGC661

HSY

analog line blanking

TV line

225

GAIN

CLAMP

control (AGC) as part of the Analog Input Control (AICO).
The AGC (automatic gain control for luminance) is used to
amplify a CVBS or Y signal to the required signal
amplitude, matched to the ADCs input voltage range.
The AGC active time is the sync bottom of the video signal.

8.3

Chrominance processing

The 8-bit chrominance signal is fed to the multiplication
inputs of a quadrature demodulator, where two subcarrier
signals from the local oscillator DTO1 are applied
(0 and 90

�

phase relationship to the demodulator axis).

The frequency is dependent on the present colour
standard. The output signals of the multipliers are
low-pass filtered (four programmable characteristics) to
achieve the desired bandwidth for the colour difference
signals.

The colour difference signals are fed to the
Brightness/Contrast/Saturation block (BCS), which
includes the following five functions;

1. AGC (automatic gain control for chrominance)

2. Chroma amplitude matching [different gain factors for

Y) and (B

Y) to achieve CCIR-601 levels

Cr and Cb]

3. Chroma saturation control

4. Luminance contrast and brightness

5. Limiting YUV to the values 1 (min.) and 254 (max.) to

fulfil CCIR-601 requirements.

Fig.5 Automatic gain range.

handbook, halfpage

analog input level

controlled

ADC input level

maximum

minimum

range 10 dB

0 dB

MGC660

4 dB

6 dB

(1 V(p-p) 75

)

1998 May 15

Philips Semiconductors

Product specification

Video Input Processor (VIP)

SAA7111

The burst processing block provides the feedback loop of
the chroma PLL and contains;

Burst gate accumulator

Colour identification and killer

Comparison nominal/actual burst amplitude

Loop filter chroma gain control

Loop filter chroma PLL

PAL sequence generation

Increment generation for DTO1 with divider to generate
stable subcarrier for non-standard signals.

The chroma comb filter block eliminates crosstalk between
the chrominance channels in accordance with the PAL
standard requirements. For NTSC colour standards the
chroma comb filter can be used to eliminate crosstalk from
luminance to chrominance (cross-colour) for vertical
structures. The comb filter can be switched off if desired.

The resulting signals are fed to the variable Y-delay
compensation, RGB matrix, dithering circuit and output
interface, which contains the VPO output formatter and the
output control logic (see Fig.7).

8.4

Luminance processing

The 8-bit luminance signal, a digital CVBS format or a
luminance format (S-VHS, HI8), is fed through a
switchable prefilter. High frequency components are
emphasized to compensate for loss. The following
chrominance trap filter (f

= 4.43 or 3.58 MHz centre

frequency selectable) eliminates most of the colour carrier
signal, therefore, it must be bypassed for S-video
(S-VHS, HI8) signals.

The high frequency components of the luminance signal
can be peaked (control for sharpness improvement via
I

C-bus) in two band-pass filters with selectable transfer

characteristic. This signal is then added to the original
(unpeaked) signal. A switchable amplifier achieves
common DC amplification, because the DC gains are
different in both chrominance trap modes. The improved
luminance signal is fed to the BCS control located in the
chrominance processing block (see Fig.8).

8.5

RGB matrix

Y, Cr and Cb-data are converted after interpolation into
RGB data in accordance with CCIR-601 recommendation.
The realized matrix equations consider the digital
quantization:

R = Y + 1.371 Cr

G = Y

0.336 Cb

0.698 Cr

B = Y + 1.732 Cb.

After dithering (noise shaping) the RGB data is fed to the
output interface within the VPO-bus output formatter.

8.6

VPO-bus (digital outputs)

The 16-bit VPO-bus transfers digital data from the output
interfaces to a feature box or a field memory, a digital
colour space converter (SAA7192 DCSC), a video
enhancement and digital-to-analog processor
(SAA7165 VEDA2) or a colour graphics board
(Targa-format) as a graphical user interface.

The output data formats are controlled via the I

C-bus bits

OFTS0, OFTS1 and RGB888. Timing for the data stream
formats, 411 YUV (12-bit), 422 YUV (16-bit),
565 RGB (16-bit) and 888 RGB (24-bit) with an LLC2 data
rate, is achieved by marking each second positive rising
edge of the clock LLC in conjunction with CREF (clock
reference) (except RGB 888, see special application in
Fig.27). The higher output signals VPO15 to VPO8 in the
YUV format perform the digital luminance signal.
The lower output signals VPO7 to VPO0 in the YUV format
are the bits of the multiplexed colour difference signals
(B

Y) and (R

Y). The arrangement of the RGB 565 and

RGB 888 data stream bits on the VPO-bus is given in
Table 5.

The data stream format 422 YUV (the 8 higher output
signals VPO15 to VPO8) in LLC data rate fulfils the
CCIR-656 standard with its own timing reference code at
the start and end of each video data block.

A pixel in the format tables is the time required to transfer
a full set of samples. In the event of a 4 : 2 : 2 format two
luminance samples are transmitted in comparison to one
(B

Y) and one (R

Y) sample within a pixel. The time

frames are controlled by the HREF signal.

1998 May 15

Philips Semiconductors

Product specification

Video Input Processor (VIP)

SAA7111

Fast enable is achieved by setting input FEI to LOW.
The signal is used to control fast switching on the digital
VPO-bus. HIGH on this pin forces the YUV outputs to a
high-impedance state (see Figs 15 and 17).

The digitized analog PAL or NTSC signals AD1 (7 to 0)
and AD2 (7 to 0) are connected directly to the VPO-bus
via I

C-bit VIPB = 1.

AD1 (7 to 0)

VPO (15 to 8) and

AD2 (7 to 0)

VPO (7 to 0)

The selection of the analog input channels are controlled
via I

C-bus subaddress 02 MODE select.

8.7

Synchronization

The prefiltered luminance signal is fed to the
synchronization stage. Its bandwidth is reduced to 1 MHz
in a low-pass filter. The sync pulses are sliced and fed to
the phase detectors where they are compared with the
sub-divided clock frequency. The resulting output signal is
applied to the loop filter to accumulate all phase
deviations. Internal signals (e.g. HCL and HSY) are
generated in accordance with analog front-end
requirements. The output signals HS, VS, and PLIN are
locked to the timing reference, guaranteed between the
input signal and the HREF signal, as further improvements
to the circuit may change the total processing delay. It is
therefore not recommended to use them for applications
which require absolute timing accuracy on the input
signals. The loop filter signal drives an oscillator to
generate the line frequency control signal LFCO
(see Fig.8).

8.8

Clock generation circuit

The internal CGC generates all clock signals required for
the video input processor. The internal signal LFCO is a
digital-to-analog converted signal provided by the
horizontal PLL. It is the multiple of the line frequency
(6.75 MHz = 432

�

). Internally the LFCO signal is

multiplied by a factor of 2 or 4 in the PLL circuit (including
phase detector, loop filtering, VCO and frequency divider)
to obtain the LLC and LLC2 output clock signals.
The rectangular output clocks have a 50% duty factor
(see Fig.22).

8.9

Power-on reset and CE input

A missing clock, insufficient digital or analog V

DDA0

supply

voltages (below 3.5 V) will initiate the reset sequence; all
outputs are forced to 3-state. The indicator output RES is
LOW for approximately 128 LLC after the internal reset
and can be applied to reset other circuits of the digital TV
system.

It is possible to force a reset by pulling the CE
(chip enable) to ground. After the rising edge of CE and
sufficient power supply voltage, the outputs LLC, LLC2,
CREF, RTCO, RTS0, RTS1, GPSW and SDA return from
3-state to active, while HREF, VREF, HS and VS remain in
3-state and have to be activated via I

C-bus programming

(see Table 4).

8.10

RTCO output

The real time control and status output signal contains
serial information about the actual system clock
(increment of the HPLL), subcarrier frequency [increment
and phase (via reset) of the FSC-PLL] and PAL sequence
bit. The signal can be used for various applications in
external circuits, e.g. in a digital encoder to achieve clean
encoding (see Fig.16).

8.11

The Line-21 text slicer

The text slicer block detects and acquires Line-21 closed
captioning data from a 525-line CVBS signal. Extended
data services on Line-21 Field 2 are also supported.
If valid data is detected the two data bytes are stored in two
I

C-bus registers. A parity check is also performed and the

result is stored in the MSB of the corresponding byte.
A third I

C-bus register is provided for data valid and data

ready flags. The two bits F1VAL and F2VAL indicate that
the input signal carries valid Closed Captioning data on the
corresponding fields. The data ready bits F1RDY and
F2RDY have to be evaluated if asynchronous I

C-bus

reading is used.

8.11.1

UGGESTIONS FOR

C-

BUS INTERFACE OF THE

DISPLAY SOFTWARE READING LINE

-21

DATA

There are two methods by which the software can acquire
the data;

1. Synchronous reading once per frame (or once per

field): It can use either the rising edge (Line-21 Field 1)
or both edges (Line-21 Field 1 or 2) of the ODD signal
(pin RTSO) to initiate an I

C-bus read transfer of the

three registers 1A, 1B and 1C

2. Asynchronous reading: It can poll either the F1RDY bit

(Line-21 Field 1) or both F1RDY/F2RDY bits (Line-21
Field 1 or 2). After valid data has been read the
corresponding F*RDY bit is set to LOW until new data
has arrived. The polling frequency has to be slightly
higher than the frame or field frequency, respectively.

1998

May

Philips Semiconductors

Product specification

ideo Input Processor (VIP)

SAA71

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handbook, full pagewidth

AI22

AI21

FUSE (1 : 0)

AI12

AI11

FUSE (1 : 0)

AOSL (1 : 0)

HOLDG

ANALOG
CONTROL

GAI10-GAI18

SSS

n.c.

VBSL

MGC655

CHR

LUM

VERTICAL

BLANKING

CONTROL

SOURCE

SWITCH

CLAMP

CIRCUIT

ANALOG

AMPLIFIER

ANTI-ALIAS

FILTER

BYPASS
SWITCH

SOURCE

SWITCH

CLAMP

CIRCUIT

ANALOG

AMPLIFIER

ANTI-ALIAS

FILTER

BYPASS

SWITCH

ADC2

ADC1

TEST

AND

SELECTOR

CLAMP

CONTROL

GAIN

CONTROL

CROSS

MULTIPLEXER

ANTI-ALIAS

CONTROL

DDA1

SSA2

AOUT

MODE

CONTROL

MODE 0

MODE 1
MODE 2

GAI20-GAI28

GUDL0-GUDL2

GAFIX

WPOFF

HSY

VBLNK
SVREF

HCL

AD1BYP

AD2BYP

BUFFER

DAC9

HLNRS
UPTCV

DDA2

SSA1

GLIMB
GLIMT
WIPA
SLTCA

Fig.6 Analog input processing.

The pin numbers given in parenthesis refer to the 64-pin package.

1998

May

Philips Semiconductors

Product specification

ideo Input Processor (VIP)

SAA71

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CHR

LUM

CODE

AD1BYP

AD2BYP

BRIG
CONT
SATN

HUEC

DCCF

MGC645

DD1-5

SS1-5

(57,41,33,
25,18)

68,52,44,
34,27

(56,40,32,26,19)
67,51,43,35,28

(31) 42

(60) 3

(34 to 39),

45 to 50

(42 to 51),

53 to 62

(52) 63

QUADRATURE

DEMODULATOR

COMB

FILTERS

FORMATTER

OUTPUT

AND

INTERFACE

ACCUMULATOR

BURST GATE

LOW-PASS

LOOP FILTER

SUBCARRIER

INCREMENT

GENERATION

SUBCARRIER
GENERATION

DIVIDER

FCTC

CSTD 1

RGB MATRIX

interpolation

dithering

DIT CBR

CHBW0
CHBW1

CSTD 0

INCS

RES

TCK

TDI

2 (59)

12 (3)

32 (23)

CONTROL

POWER-ON

CONTROL

TEST

BLOCK

TDO

TRST

11 (2)

1 (58)

TMS

13 (4)

LUM

RTCO

n.c.

10 (1)

CLOCKS

RGB

FEI

HREF

VPO
(9 : 0)

VPO
(15 : 10)

AND

PHASE

DEMOD.

AMPLITUDE

DETECTOR

OFTS0
OFTS1
RGB888
OEYC
OEHV
FECO
VRLN

GPSW
RTSE1
RTSE0
VIPB
VLOF
COLO
COMPO

BRIGHTNESS,

CONTRAST,

AND

SATURATION

CONTROL

GAIN

CONTROL

AND Y-DELAY

COMPENSATION

Fig.7 Chrominance circuit.

The pin numbers given in parenthesis refer to the 64-pin package.

1998

May

Philips Semiconductors

Product specification

ideo Input Processor (VIP)

SAA71

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CREF

LLC

XTALI

XTAL

VREF

RTS0

SDA

SCL

IICSA

GPSW

I C BUS CONTROL

CLOCKS

SYNCHRONIZATION CIRCUIT

PREF

BYPS

APER0
APER1
VBLB

AUFD

HSB
HSS

FSEL

VTRC

STTC

FIDT

VNOI0
VNOI1
VTRC

VTRC

RTS1

MGC654

LLC2

HLCK

DDA0

SSA0

16
24

20
21

DAC6

AND

WEIGHTING

ADDING

BAND-PASS

VARIABLE

FILTER

CHROMINANCE

TRAP

PREFILTER

AMPLIFIER

MATCHING

CLOCK

LINE-LOCKED

GENERATOR

LOOP FILTER

DETECTOR

PHASE

COARSE

DETECTOR

PHASE

FINE

SYNC SLICER

SYNC

PREFILTER

LINE 21

TEXT

SLICER

CLOCK

CRYSTAL

GENERATOR

TIME

DISCRETE

OSCILLATOR 2

INTERFACE

I C-BUS

PROCESSOR

VERTICAL

COUNTER

GENERATION

CLOCK

CIRCUIT

LUMINANCE CIRCUIT

BPSS0
BPSS1
PREF

LUM

VBLB

CLOCK CIRCUIT

INCS

STAGE

HPLL

VTRC
EXFIL

BYTE1
BYTE2

STATUS

Fig.8 Luminance and sync processing.

The pin numbers given in parenthesis refer to the 64-pin package.

1998 May 15

Philips Semiconductors

Product specification

Video Input Processor (VIP)

SAA7111

10 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Note

1. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k

resistor.

11 CHARACTERISTICS

DDD

= 4.5 to 5.5 V; V

DDA

= 4.75 to 5.25 V; T

amb

= 25

�

C; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

DDD

digital supply voltage

0.5

+6.5

DDA

analog supply voltage

0.5

+6.5

diff

voltage difference between V

SSAall

and

SSall

100

stg

storage temperature

+150

�

amb

operating ambient temperature

�

amb(bias)

operating ambient temperature under bias

+80

�

ESD

electrostatic discharge all pins

note 1

2000

+2000

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies

DDD

digital supply voltage

4.5

5.0

5.5

DDD

digital supply current

100

130

160

digital power

0.45

0.65

0.88

DDA

analog supply voltage

4.75

5.0

5.25

DDA

analog supply current

analog power

0.32

0.35

0.38

A+D

analog and digital power

0.77

1.0

1.26

Analog part

clamp

clamping current

= 1.25 V DC

�

i(p-p)

input voltage (peak-to-peak
value), AC coupling required

coupling
capacitor = 10 nF; note 1

0.55

1.0

1.5

input impedance

clamping current off

200

input capacitance

channel crosstalk

= 5 MHz

Analog-to-digital converters

bandwidth

3 dB

MHz

diff

differential phase (amplifier
plus anti-alias filter = bypass)

deg

diff

differential gain (amplifier plus
anti-alias filter = bypass)

ADC

ADC clock frequency

MHz

DLE

DC differential linearity error

0.5

LSB

ILE

DC integral linearity error

LSB

1998 May 15

Philips Semiconductors

Product specification

Video Input Processor (VIP)

SAA7111

Digital inputs

LOW-level input voltage pins
SDA and SCL

0.5

+1.5

HIGH-level input voltage pins
SDA and SCL

0.7V

DDD

+ 0.5

IL(xtalI)

LOW-level CMOS input
voltage pin XTALI

0.3V

DDD

IH(xtalI)

HIGH-level CMOS input
voltage pin XTALI

0.7V

DDD

ILn

LOW-level input voltage all
other inputs

0.5

+0.8

IHn

HIGH-level input voltage all
other inputs

2.0

DDD

+ 0.5

input leakage current

�

i(I/O)

input capacitance

inputs and outputs at
high-impedance

i(n)

input capacitance all other
inputs

Digital outputs

LOW-level output voltage pins
SDA and SCL

SDA/SCL at 3 mA sink
current

0.4

LOW-level output voltage

note 2

0.6

HIGH-level output voltage

note 2

2.4

DDD

OL(clk)

LOW-level output voltage for
clocks

0.5

+0.6

OH(clk)

HIGH-level output voltage for
clocks

2.6

DDD

+ 0.5

FEI input timing

SU;DAT

input data set-up time

HD;DAT

input data hold time

Data and control output timing

output load capacitance

OHD;DAT

output hold time

= 15 pF

propagation delay

= 40 pF

PDZ

propagation delay to 3-state

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1998 May 15

Philips Semiconductors

Product specification

Video Input Processor (VIP)

SAA7111

Clock output timing (LLC and LLC2)

L(LLC)

output load capacitance

cycle time

LLC

LLC2

LLC

duty factors for t

LLCH

LLC

and

LLC2H

LLC2

= 40 pF

rise time

= 0.6 to 2.6 V

fall time

= 2.6 to 0.6 V

dLLC2

delay time LLC output to LLC2
output

= 1.5 V;

LLC/LLC2 = 40 pF

Data qualifier output timing (CREF)

OHD;CREF

output hold time

= 15 pF

PD;CREF

propagation delay from
positive edge of LLC

= 40 pF

Clock input timing (XTALI)

XTALI

duty factor for t

XTALIH

XTALI

nominal frequency

Horizontal PLL

nominal line frequency

50 Hz field

15625

60 Hz field

15734

permissible static deviation

5.7

Subcarrier PLL

SCn

nominal subcarrier frequency

PAL BGHI and NTSC 443

4433619

NTSC M

3579545

PAL M

3575612

PAL N

3582056

SCH

SCHn

lock-in range

�

400

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1998 May 15

Philips Semiconductors

Product specification

Video Input Processor (VIP)

SAA7111

Notes

1. The levels must be measured with load circuits; 1.2 k

at 3 V (TTL load); C

= 50 pF.

2. The effects of rise and fall times are included in the calculation of t

OHD;DAT

, t

and t

PDZ

. Timings and levels refer to

drawings and conditions illustrated in Figs 12 and 13.

Table 1

Processing delay

Crystal oscillator

nominal frequency

3rd harmonic

24.576

MHz

f/f

permissible nominal
frequency deviation

�

f/f

(T)

permissible nominal
frequency deviation with
temperature

�

RYSTAL SPECIFICATION

(X1)

ambX1

operating ambient
temperature

�

load capacitance

series resonance resistor

motional capacitance

1.5

�

20%

parallel capacitance

3.5

�

20%

FUNCTION

TYPICAL ANALOG DELAY

AI22

ADCIN (AOUT) (ns)

DIGITAL DELAY

ADCIN

VPO (LLC-CLOCKS)

[YDEL(2 to 0) = 000]

Without amplifier or anti-alias filter

139

With amplifier, without anti-alias filter

With amplifier plus anti-alias filter

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1998 May 15

Philips Semiconductors

Product specification

Video Input Processor (VIP)

SAA7111

Fig.16 Real time control output.

(1) Set to zero for one transmission, if a phase reset of the f

- DTO is applied via I

C-bit CDTO. RTCO sequence is generated in LLC/4.

The HPLL increment represents the actual LFCO frequency (f

LFCO

�

4 = f

LLC

); 16 LSB from 20, upper four bits are fixed to 0100b

Where: f

XTAL

= 24.576 MHz, word length DTO2 = 20 bits.

The f

increment represents the actual subcarrier frequency (related to the actual clock); 23 LSB from 24, MSB is 0b.

Where: word length DTO1 = 24 bits.

LFCO

INCR

HPLL

XTAL

�

word length DTO2

-------------------------------------------------

INCR

FSCPLL

XTAL

�

word length DTO1

-------------------------------------------------------

INCR

HPLL

----------------------------

�

handbook, full pagewidth

TIME SLOT:

BIT NO.:

transmitted once per line

11 10

SEQUENCE

RESERVED

INCRFSCPLL

MGC649

RESERVED

128

HIGH

LOW

INCRHPLL

RESERVED

DTO RESET

(1)

50 Hz fields: 235
60 Hz fields: 232

Fig.17 FEI timing diagram (FEI sampling at CREF = LOW).

Timing is compatible with SAA7110; I

C-bit FECO = 0.

handbook, full pagewidth

LLC

CREF

HREF

VPO

SU;DAT

HD;DAT

to 3-state

MGC657

from 3-state

OHD;DAT

PDZ

FEI

1998 May 15

Philips Semiconductors

Product specification

Video Input Processor (VIP)

SAA7111

Table 4

Power-on control sequence

14 OUTPUT FORMATS

Table 5

Output formats

Notes

1. Values in accordance with CCIR-601.

2. Before and after the video data, video timing codes are inserted in accordance with CCIR-656.

3. Values not defined during HREF = LOW.

4. CREF = 0 (see Fig.14).

5. CREF = 1 (see Fig.14).

INTERNAL POWER-ON

CONTROL SEQUENCE

PIN OUTPUT STATUS

FUNCTION

Directly after power-on
asynchronous reset

VPO15 to VPO0, RTCO, RTS0, RTS1,
GPSW, HREF, VREF, HS, VS, LLC, LLC2
and CREF are in high-impedance state

direct switching to high impedance for
20 to 200 ms

Synchronous reset
sequence

LLC, LLC2, CREF, RTCO, RTS0, RTS1,
GPSW and SDA become active;
VPO15 to VPO0, HREF, VREF, HS and VS
are held in high-impedance state

internal reset sequence

Status after power-on
control sequence

VPO15 to VPO0, HREF, VREF, HS and VS
are held in high-impedance state

after power-on (reset sequence) a complete
I

C-bus transmission is required

BUS SIGNAL

411 (12-BIT)

422 (16-BIT)

(1)

CCIR-656 (8-BIT)

(2)

RGB (16-BIT)

(3)

RGB (24-BIT)

(3)

VPO15

VPO14

VPO13

VPO12

VPO11

VPO10

VPO9

VPO8

VPO7

VPO6

VPO5

VPO4

VPO3

VPO2

VPO1

VPO0

Pixel order Y

note 4

note 5

Pixel order UV

Data rates

LLC2

LLC

LLC2

LLC

C-bus

control signals

OFTS0 = 0

OFTS0 = 1

OFTS0 = 0

OFTS1 = 1

OFTS1 = 0

OFTS1 = 1

OFTS1 = 0

RGB888 = X

RGB888 = 0

RGB888 = 1

1998 May 15

Philips Semiconductors

Product specification

Video Input Processor (VIP)

SAA7111

Fig.24 VPO output signal range with default BCS settings.

Equations for modification to the YUV levels via BCS control I

C bytes BRIG, CONT and SATN.

Luminance:

Chrominance:

It should be noted that the resulting levels are limited to 1 to 254 in accordance with CCIR-601/656 standard.

OUT

Int

CONT

------------------

128

�

(

)

�

BRIG

OUT

Int

SATN

-----------------

Cr Cb

128

�

(

)

�

128

handbook, full pagewidth

LUMINANCE 100%

255

235

128

white

black

U-COMPONENT

255

240

212

128

blue 100%

blue 75%

yellow 75%

yellow 100%

colourless

V-COMPONENT

255

240

128

red 100%

red 75%

cyan 75%

cyan 100%

colourless

MGC634

a. Y output range.

b. U output range (Cb).

c. V output range (Cr).

CCIR Rec. 602 digital levels.

Fig.25 Oscillator application.

handbook, full pagewidth

XTAL

XTALI

65 (54)

66 (55)

MGC635

XTAL

L = 10

�

20%

C =
10 pF

C =
1 nF

quartz (3rd harmonic)
24.576 MHz

XTALI

65 (54)

66 (55)

SAA7111

The pin numbers given in parenthesis refer to the 64-pin package.

a. With quartz crystal.

b. With external clock.

1998 May 15

Philips Semiconductors

Product specification

Video Input Processor (VIP)

SAA7111

15 APPLICATION INFORMATION

handbook, full pagewidth

Q1(24.576 MHz)

VPO(15 : 0)

SCL

DDD

AI22

FEI

SDA

RTCO

AOUT

GPSW

RTS0

RTS1

RES

CREF

LLC2

LLC

HREF

SSA

DDA

SSA

VREF

SAA7111

10 nF

100 nF

C11

C12

C13

C14

C15

1 k

n.c.

SSA2

SS1

SS2

SS3

SS4

SS5

IICSA

SSA1

SSA0

DDA0

DDA1

DDA2

DD1

DD2

DD3

DD4

DD5

TMS

TDI

TDO

TCK

TRST

n.c.

C17

�

C16

1 nF

10 pF 10 pF

C18

1 k

(18)

(25)

(33)

(41)

(57)

(3)

(7)

(11)

(15)

(34) 45

(35) 46

(36) 47

(37) 48

(38) 49

(39) 50

(42) 53

(43) 54

(44) 55

(45) 56

(46) 57

(47) 58

(48) 59

(31) 42

(27) 38

(30) 41

(60) 3

(14) 23

(53) 64

(28) 39

(29) 40

(20) 29

(21) 30

(22) 31

(23) 32

(17) 26

36 37

(64)

(58)

(59)

(61)

(19)

(26)

(32)

(40)

(56)

(13)

(5)

(9)

(16)

(2)

(4)

15 (6)

6 (63)

5 (62)

63 (52)

33 (24)

66 (55)

65 (54)

XTAL

XTALI

n.c.

MGC651

SSA

BST

n.c.

(49) 60

(50) 61

(51) 62

100 nF

10 nF

SSA

AI21

10 nF

SSA

17 (8)

AI12

10 nF

SSA

19 (10)

AI11

21 (12)

Fig.26 Application diagram.

The pin numbers given in parenthesis refer to the QFP64 package.

1998 May 15

Philips Semiconductors

Product specification

Video Input Processor (VIP)

SAA7111

Fig.27 Application diagram for RGB 24-bit output format.

The pin numbers given in parenthesis refer to the QFP64 package.

C-bus control bits:

OFTS(1 : 0) = 00 (subaddress 10h, bits D7 and D6).

RGB888 = 1 (subaddress 12h, bit D3).

handbook, full pagewidth

OEN

e.g.

74HCT574

(44) 55

(45) 56

(46) 57

(47) 58

(48) 59

(49) 60

(50) 61

(51) 62

(31) 42

HREF

(17) 26

(27) 38

(30) 41

(60) 3

(28) 39

(29) 40

(53) 64

(14) 23

(20) 29

(21) 30

(32) 31

(23) 32

VSS

CLK

R (2 : 0)

R (7 : 0)

VDD

G (1 : 0)

G (7 : 0)

B (2 : 0)

B (7 : 0)

LLC2N

MGD137

LLC2

e.g. 74F240

B (7 : 3)

VPO (4 : 0)

VPO

(7 : 0)

SAA7111

VPO (15 : 11)

R (7 : 3)

G (7 : 5)

G (4 : 2)

VPO (10 : 8)

VPO (7 : 5)

VREF

RTCO

RTS1

RTS0

GPSW

AOUT

LLC

CREF

RES

(34) 45

(35) 46

(36) 47

(37) 48

(38) 49

(39) 50

(42) 53

(43) 54

VPO

(15 : 8)

15.1

Layout hints

Use separate ground planes for analog and digital ground.
Connect these planes at one point directly under the
device, by using a zero

resistor. Use separate supply

lines for analog and digital supply. Place the supply
decoupling capacitors nearby the supply pins.

Place the coupling (clamp) capacitors close to the analog
input pins. Place the termination resistors close to the
coupling capacitors. Care should be exercised concerning
the hidden layout capacitors around the crystal
application. To avoid reflection effects use serial resistors
in the clock, sync and data lines.

1998 May 15

Philips Semiconductors

Product specification

Video Input Processor (VIP)

SAA7111

16 I

C-BUS DESCRIPTION

16.1

C-bus format

Table 6

Write procedure

Table 7

Read procedure (combined format)

Table 8

Description of I

C-bus format

Notes

1. If more than one byte DATA is transmitted then the auto-increment of the subaddress is performed.

2. During slave transmitter mode the SCL-LOW period may be extended by pulling SCL to LOW (in accordance with

the I

C-bus specification).

3. The I

C-bus subaddress 00 has to be initialized with 0 before being read.

SLAVE ADDRESS W

ACK(s)

SUBADDRESS

ACK(s)

DATA (N BYTES)

ACK(s)

SLAVE ADDRESS W

ACK(s)

SUBADDRESS

ACK(s)

SLAVE ADDRESS R

ACK(s)

DATA (N BYTES)

ACK(m)

CODE

DESCRIPTION

START condition

repeated START condition

Slave address W

0100 1000b (IICSA = LOW) or 0100 1010b (IICSA = HIGH)

Slave address R

0100 1001b (IICSA = LOW) or 0100 1011b (IICSA = HIGH)

ACK(s)

acknowledge generated by the slave

ACK(m)

acknowledge generated by the master

Subaddress

subaddress byte; see Table 9

Data

data byte, see; note 1 and Table 9

STOP condition

X = LSB slave
address

read/write control bit; X = 0, order to write (the circuit is slave receiver); X = 1, order to read
(the circuit is slave transmitter)

Slave address

read = 49H or 4BH; note 2

write = 48H or 4AH

IICSA = 0 or 1

Subaddress

00H chip version

read and write; note 3

01H reserved

02H to 05H front-end part

read and write

06H to 12H decoder part

read and write

13H to 19H reserved

1AH to 1CH Line-21 text slicer part

read only

1DH to 1EH reserved

1FH status byte

read only

1998 May 15

Philips Semiconductors

Product specification

Video Input Processor (VIP)

SAA7111

Table 9

C-bus receiver/transmitter overview

Note

1. All unused control bits must be programmed with 0.

16.2

C-bus detail

The I

C-bus receiver slave address is 48H/49H. Subaddresses 0F, 1D, 1E and 13 to 19 are reserved; subaddress 01 is

reserved for chip version.

SLAVE ADDRESS

READ

WRITE

IICSA

49H and 4BH

48H and 4AH

0 and 1

SUB-

ADDR.

Chip version

ID07

ID06

ID05

ID04

ID03

ID02

ID01

ID00

Reserved

(1)

Analog input control 1

FUSE1

FUSE0

GUDL2

GUDL1

GUDL0

MODE2

MODE1

MODE0

Analog input control 2

(1)

HLNRS

VBSL

WPOFF

HOLDG

GAFIX

GAI28

GAI18

Analog input control 3

GAI17

GAI16

GAI15

GAI14

GAI13

GAI12

GAI11

GAI10

Analog input control 4

GAI27

GAI26

GAI25

GAI24

GAI23

GAI22

GAI21

GAI20

Horizontal sync start

HSB7

HSB6

HSB5

HSB4

HSB3

HSB2

HSB1

HSB0

Horizontal sync stop

HSS7

HSS6

HSS5

HSS4

HSS3

HSS2

HSS1

HSS0

Sync control

AUFD

FSEL

EXFIL

(1)

VTRC

HPLL

VNOI1

VNOI0

Luminance control

BYPS

PREF

BPSS1

BPSS0

VBLB

UPTCV

APER1

APER0

Luminance brightness

BRIG7

BRIG6

BRIG5

BRIG4

BRIG3

BRIG2

BRIG1

BRIG0

Luminance contrast

CONT7

CONT6

CONT5

CONT4

CONT3

CONT2

CONT1

CONT0

Chroma saturation

SATN7

SATN6

SATN5

SATN4

SATN3

SATN2

SATN1

SATN0

Chroma Hue control

HUEC7

HUEC6

HUEC5

HUEC4

HUEC3

HUEC2

HUEC1

HUEC0

Chroma control

CDTO

CM99

CSTD1

CSTD0

DCCF

FCTC

CHBW1

CHBW0

Reserved

(1)

Format/delay control

OFTS1

OFTS0

HDEL1

HDEL0

VRLN

YDEL2

YDEL1

YDEL0

Output control 1

GPSW

(1)

FECO

COMPO

OEYC

OEHV

VIPB

COLO

Output control 2

RTSE1

RTSE0

(1)

CBR

RGB888

DIT

AOSL1

AOSL0

Reserved

13-19

(1)

Text slicer status

(1)

F2VAL

F2RDY

F1VAL

F1RDY

Decoded bytes of the
text slicer

BYTE16 BYTE15 BYTE14

BYTE13

BYTE12

BYTE11

BYTE10

BYTE26 BYTE25 BYTE24

BYTE23

BYTE22

BYTE21

BYTE20

Reserved

1D-1E

(1)

Status byte

STTC

HLCK

FIDT

GLIMT

GLIMB

WIPA

SLTCA

CODE

1998 May 15

Philips Semiconductors

Product specification

Video Input Processor (VIP)

SAA7111

16.2.1

UBADDRESS

Table 10 Chip version SA 00, D7 to D0

Note

1. The I

C-bus subaddress 00 has to be initialized with 0 prior to reading it.

16.2.2

UBADDRESS

Table 11 Analog control 1 (mode select; see Figs 28 to 35) SA 02, D2 to D0; note 1

Note

1. For modes 0 to 3 use BYPS (SA 09, D7) = 0 (chrominance trap active) and for modes 4 to 7 use BYPS = 1

(chrominance trap bypassed).

Table 12 Analog control 1 SA 02, D5 to D3 (see Fig.11)

Table 13 Analog control 1 SA 02, D7 and D6

FUNCTION

CONTROL BITS

ID07

ID06

ID05

ID04

ID03

ID02

ID01

ID00

Chip version in read mode

(1)

chip version number

reserved for chip name

FUNCTION

CONTROL BITS D2 TO D0

MODE 2

MODE 1

MODE 0

Mode 0: CVBS (automatic gain)

Mode 1: CVBS (automatic gain)

Mode 2: CVBS (automatic gain)

Mode 3: CVBS (automatic gain)

Mode 4: Y (automatic gain) + C (gain channel 2 fixed to GAI2 level)

Mode 5: Y (automatic gain) + C (gain channel 2 fixed to GAI2 level)

Mode 6: Y (automatic gain) + C (gain channel 2 adapted to Y gain)

Mode 7: Y (automatic gain) + C (gain channel 2 adapted to Y gain)

DECIMAL VALUE

UPDATE HYSTERESIS FOR 9-BIT GAIN

CONTROL BITS D5 TO D3

GUDL 2

GUDL 1

GUDL 0

0....

off

....7

�

7 LSB

ANALOG FUNCTION SELECT FUSE

CONTROL BITS D7 AND D6

FUSE 1

FUSE 0

Amplifier plus anti-alias filter bypassed

Amplifier active

Amplifier plus anti-alias filter active

1998 May 15

Philips Semiconductors

Product specification

Video Input Processor (VIP)

SAA7111

16.2.3

UBADDRESS

Table 14 Analog control 2 (AICO2)

16.2.4

UBADDRESS

Table 15 Gain control analog (AIC03); static gain control channel 1 GAI1 SA 04, D7 to D0

FUNCTION

BIT NAME

LOGIC LEVEL

CONTROL BIT

Static gain control channel 1 (GAI18)

Sign bit of gain control

GAI18

see Table 15

Static gain control channel 2 (GAI28)

Sign bit of gain control

GAI28

see Table 16

Gain control fix (GAFIX)

Automatic gain controlled by MODE 1 and MODE 0

GAFIX

Gain control is user programmable via GAI1 + GAI2

GAFIX

Automatic gain control integration (HOLDG)

AGC active

HOLDG

AGC integration hold (freeze)

HOLDG

White peak off (WPOFF)

White peak control active

WPOFF

White peak off

WPOFF

Vertical blanking select (VBSL)

Long vertical blanking

VBSL

Short vertical blanking

VBSL

HL not reference select (HLNRS)

Normal clamping by HL not

HLNRS

Reference select by HL not

HLNRS

DECIMAL

VALUE

GAIN (dB)

SIGN

BIT

CONTROL BITS D7 TO D0

GAI18

GAI17

GAI16

GAI15

GAI14

GAI13

GAI12

GAI11

GAI10

0....

5.98

....255

256....

....511

5.98

1998 May 15

Philips Semiconductors

Product specification

Video Input Processor (VIP)

SAA7111

16.2.5

UBADDRESS

Table 16 Gain control analog (AIC04); static gain control channel 2 GAI2 SA 05

16.2.6

UBADDRESS

Table 17 Horizontal sync begin SA 06, D7 to D0

16.2.7

UBADDRESS

Table 18 Horizontal sync stop SA 07

\DECIMAL

VALUE

GAIN

(dB)

SIGN BIT

(SA 03, D1)

CONTROL BITS D7 to D0

GAI28

GAI27

GAI26

GAI25

GAI24

GAI23

GAI22

GAI21

GAI20

0....

5.98

....255

256....

....511

5.98

DELAY TIME

(STEP SIZE = 8/LLC)

CONTROL BITS D7 to D0

HSB7

HSB6

HSB5

HSB4

HSB3

HSB2

HSB1

HSB0

128...

108

forbidden (outside available central counter range)

107...

...108 (50 Hz)

...107 (60 Hz)

109...127 (50 Hz)

forbidden (outside available central counter range)

108...127 (60 Hz)

DELAY TIME

(STEP SIZE = 8/LLC)

CONTROL BITS D7 to D0

HSS7

HSS6

HSS5

HSS4

HSS3

HSS2

HSS1

HSS0

128...

108

forbidden (outside available central counter range)

107...

...108 (50 Hz)

...107 (60 Hz)

109...127 (50 Hz)

forbidden (outside available central counter range)

108...127 (60 Hz)

1998 May 15

Philips Semiconductors

Product specification

Video Input Processor (VIP)

SAA7111

16.2.9

UBADDRESS

Table 20 Luminance control

Note

1. Not to be used with bypassed chrominance trap.

FUNCTION

BIT NAME

LOGIC LEVEL

CONTROL BIT

Aperture factor (APER)

Aperture factor = 0

APER1

APER0

Aperture factor = 0.25

APER1

APER0

Aperture factor = 0.5

APER1

APER0

Aperture factor = 1.0

APER1

APER0

Update time interval for AGC value (UPTCV)

Horizontal update (once per line)

UPTCV

Vertical update (once per field)

UPTCV

Vertical blanking luminance bypass (VBLB

Active luminance processing

VBLB

Luminance bypass during vertical blanking

VBLB

Aperture band-pass (centre frequency) (BPSS) D5 and D4

Centre frequency = 4.1 MHz

BPSS1

BPSS0

Centre frequency = 3.8 MHz; note 1

BPSS1

BPSS0

Centre frequency = 2.6 MHz; note 1

BPSS1

BPSS0

Centre frequency = 2.9 MHz; note 1

BPSS1

BPSS0

Prefilter active (PREF)

Bypassed

PREF

Active

PREF

Chrominance trap bypass (BYPS)

Chrominance trap active; default for CVBS mode

BYPS

Chrominance trap bypassed; default for S-Video mode

BYPS

1998 May 15

Philips Semiconductors

Product specification

Video Input Processor (VIP)

SAA7111

16.2.10 S

UBADDRESS

Table 21 Luminance brightness control BRIG7 to BRIG0 SA 0A

16.2.11 S

UBADDRESS

Table 22 Luminance contrast control CONT7 to CONT0 SA 0B

16.2.12 S

UBADDRESS

Table 23 Chrominance saturation control SATN7 to SATN0 SA 0C

16.2.13 S

UBADDRESS

Table 24 Chrominance hue control HUEC7 to HUEC0 SA 0D

OFFSET

CONTROL BITS D7 to D0

BRIG7

BRIG6

BRIG5

BRIG4

BRIG3

BRIG2

BRIG1

BRIG0

255 (bright)

128 (CCIR level)

0 (dark)

GAIN

CONTROL BITS D7 to D0

CONT7

CONT6

CONT5

CONT4

CONT3

CONT2

CONT1

CONT0

1.999 (maximum)

1.109 (CCIR level)

1.0

0 (luminance off)

1 (inverse luminance)

2 (inverse luminance)

GAIN

CONTROL BITS D7 to D0

SATN7

SATN6

SATN5

SATN4

SATN3

SATN2

SATN1

SATN0

1.999 (maximum)

1.0 (CCIR level)

0 (colour off)

1 (inverse chroma)

2 (inverse chroma)

HUE PHASE (DEG)

CONTROL BITS D7 to D0

HUEC7

HUEC6

HUEC5

HUEC4

HUEC3

HUEC2

HUEC1

HUEC0

+178.6....

....0....

....

180

1998 May 15

Philips Semiconductors

Product specification

Video Input Processor (VIP)

SAA7111

16.2.14 S

UBADDRESS

Table 25 Chrominance control SA 0E

FUNCTION

BIT NAME

LOGIC LEVEL

CONTROL BIT

Chroma bandwidth (CHBW0 and CHBW1)

Small bandwidth (

620 kHz)

CHBW1

CHBW0

Nominal bandwidth (

800 kHz)

CHBW1

CHBW0

Medium bandwidth (

920 kHz)

CHBW1

CHBW0

Wide bandwidth (

1000 kHz)

CHBW1

CHBW0

Fast colour time constant (FCTC)

Nominal time constant

FCTC

Fast time constant

FCTC

Disable chroma comb filter (DCCF)

Chroma comb filter on (during VREF = 1)
(see Figures 20 and 21)

DCCF

Chroma comb filter off

DCCF

Colour standard (CSTD0 and CSTD1)

Colour standard control automatic switching between
PAL BGHI and NTSC M

CSTD1

CSTD0

Colour standard control automatic switching between
NTSC 4.43 (50 Hz) and PAL 4.43 (60 Hz)

CSTD1

CSTD0

Colour standard control automatic switching between
PAL N and NTSC 4.43 (60 Hz)

CSTD1

CSTD0

Colour standard control automatic switching between
NTSC N and PAL M

CSTD1

CSTD0

Compatibility to SAA7199 (CM99)

Default value

CM99

To be set if SAA7199 (digital encoder) is used for
re-encoding in conjunction with RTCO

CM99

Clear DTO (CDTO)

Disabled

CDTO

Every time CDTO is set, the internal subcarrier DTO
phase is reset to 0

�

and the RTCO output generates a

logic 0 at time slot 68 (see RTCO description Fig.16). So
an identical subcarrier phase can be generated by an
external device (e.g. an encoder).

CDTO

1998 May 15

Philips Semiconductors

Product specification

Video Input Processor (VIP)

SAA7111

16.2.15 S

UBADDRESS

Table 26 Format/delay control SA 10

Table 27 VREF pulse position and length VRLN SA 10 (D3)

Note

1. The numbers given in parenthesis refer to CCIR line counting.

Table 28 Fine position of HS HDEL0 and HDEL1 SA 10

Table 29 Output format selection OFTS0 and OFTS1 SA 10

LUMINANCE DELAY COMPENSATION

(STEPS IN 2/LLC)

CONTROL BITS D2 to D0

YDEL2

YDEL1

YDEL0

4...

...0...

...3

VRLN

VREF at 60 HZ 525 LINES

(1)

VREF at 50 HZ 625 LINES

Length

240

242

286

288

Line number

first

last

first

last

first

last

first

last

Field 1

19 (22)

258 (261)

18 (21)

259 (262)

309

310

Field 2

282 (285)

521 (524)

281 (284)

522 (525)

337

622

336

623

FINE POSITION OF HS WITH A STEP SIZE

OF 2/LLC

CONTROL BITS D5 and D4

HDEL1

HDEL0

FORMATS

CONTROL BITS D7 and D6

OFTS1

OFTS0

RGB 565, RGB 888 (dependent on control
bit RGB888) see Table 31

YUV 422 16 bits

YUV 411 12 bits

YUV CCIR-656 8 bits

1998 May 15

Philips Semiconductors

Product specification

Video Input Processor (VIP)

SAA7111

16.2.16 S

UBADDRESS

Table 30 Output control 1 SA 11

Note

1. The pin number given in parenthesis refers to the 64-pin package.

FUNCTION

BIT NAME

LOGIC LEVEL

CONTROL BIT

Colour on (COLO)

Automatic colour killer

COLO

Colour forced on

COLO

Decoder VIP bypassed (VIPB)

DMSD data to YUV output

VIPB

ADC data to YUV output; dependent on mode settings

VIPB

Output enable horizontal/vertical sync (OEHV)

HS, HREF, VREF and VS high impedance inputs

OEHV

Outputs HS, HREF, VREF and VS active

OEHV

Output enable YUV data (OEYC)

VPO-bus high-impedance inputs

OEYC

Output VPO-bus active

OEYC

Inverse composite blank (COMPO)

VREF is vertical reference

COMPO

VREF is inverse composite blank

COMPO

FEI control (FECO)

FEI sampling at CREF = LOW
(SAA7110 compatible; see Fig.17)

FECO

FEI sampling at CREF = HIGH

FECO

General purpose switch (GPSW)

Switches directly pin 64 (53) GPSW; note 1

GPSW

1998 May 15

Philips Semiconductors

Product specification

Video Input Processor (VIP)

SAA7111

16.2.17 S

UBADDRESS

Table 31 Output control 2 SA 12

Note

1. The pin number given in parenthesis refers to the 64-pin package.

FUNCTION

BIT NAME

LOGIC LEVEL

CONTROL BIT

Analog test select (AOSL)

AOUT connected to internal test point 1

AOSL1

AOSL0

AOUT connected to input AD1

AOSL1

AOSL0

AOUT connected to input AD2

AOSL1

AOSL0

AOUT connected to internal test point 2

AOSL1

AOSL0

Dithering (noise shaping) control (DIT)

Dithering off

DIT

Dithering on

DIT

RGB output format selection (RGB888)

RGB565

RGB888

Chroma interpolation filter function (CBR)

Cubic interpolation (default)

CBR

Linear interpolation (lower bandwidth)

CBR

Real time outputs mode select (RTSE0)

ODD switched to output pin 40 (29); note 1

RTSE0

VL switched to output pin 40 (29); note 1

RTSE0

Real time outputs mode select (RTSE1)

PLIN switched to output pin 39 (28); note 1

RTSE1

HL switched to output pin 39 (28); note 1

RTSE1

1998 May 15

Philips Semiconductors

Product specification

Video Input Processor (VIP)

SAA7111

16.2.18 S

UBADDRESS

1A (

READ

ONLY REGISTER

)

Table 32 Line-21 text slicer status SA 1A

16.2.19 S

UBADDRESS

1B (

READ

ONLY REGISTER

)

Table 33 First decoded data byte of the text slicer SA 1B

16.2.20 S

UBADDRESS

1C (

READ

ONLY REGISTER

)

Table 34 Second decoded data byte of the text slicer SA 1C

16.2.21 S

UBADDRESS

1F (

READ

ONLY REGISTER

)

Table 35 Status byte SA 1F

C-BUS

STATUS BIT

NAME

FUNCTION

STATUS BIT

F1RDY

new data on field 1 has been acquired (for asynchronous reading); active HIGH

F1VAL

Line-21 of field 1 carries valid data; active HIGH

F2RDY

new data on field 2 has been acquired (for asynchronous reading); active HIGH

F2VAL

Line-21 of field 2 carries valid data; active HIGH

C-BUS

TEXT DATA

BITS

FUNCTION

DATA BITS

BYTE1 (6 to 0)

data bit 6 to 0 of first data byte

D6 to D0

parity error flag bit; bit goes HIGH when a parity error has occurred

C-BUS

TEXT DATA

BITS

FUNCTION

DATA BITS

BYTE2 (6 to 0)

data bit 6 to 0 of second data byte

D6 to D0

parity error flag bit; bit goes HIGH when a parity error has occurred

C-BUS

STATUS BIT

NAME

FUNCTION

STATUS BIT

CODE

colour signal according to selected standard has been detected; active HIGH

SLTCA

slow time constant active in WIPA-mode; active HIGH

WIPA

white peak loop is activated; active HIGH

GLIMB

gain value for active luminance channel is limited [min (bottom)]; active HIGH

GLIMT

gain value for active luminance channel is limited [max (top)]; active HIGH

FIDT

identification bit for detected field frequency; LOW = 50 Hz and HIGH = 60 Hz

HLCK

status bit for locked horizontal frequency; LOW = locked and HIGH = unlocked

STTC

status bit for horizontal phase loop; LOW = TV time-constant and
HIGH = VTR time-constant

1998 May 15

Philips Semiconductors

Product specification

Video Input Processor (VIP)

SAA7111

Table 36 I

C-bus start set-up values

Notes

1. All X values must be set to LOW.

2. The I

C-bus subaddress 00 has to be initialized with 0 prior to reading.

SUB

(HEX)

FUNCTION

NAME

(1)

VALUES (BIN)

(HEX)

START

chip version

ID0(7 : 0); note 2

reserved

analog input control 1

FUSE(1 : 0), GUDL(2 : 0) and
MODE(2 : 0)

analog input control 2

X, HLNRS, VBSL, WPOFF, HOLDG,
GAFIX, GAI2 and GAI18

analog input control 3

GAI(17 : 10)

analog input control 4

GAI(27 : 20)

horizontal sync start

HSB(7 : 0)

horizontal sync stop

HSS(7 : 0)

sync control

AUFD, FSEL, EXFIL, X, VTRC and HPLL
and VNOI(1 : 0)

luminance control

BYPS, PREF, BPSS(1 : 0), VBLB,
UPTCV and APER(1 : 0)

luminance brightness

BRIG(7 : 0)

luminance contrast

CONT(7 : 0)

chrominance saturation SATN(7 : 0)

chroma hue control

HUEC(7 : 0)

chrominance control

CDTO, CM99, CSTD(1 : 0), DCCF, FCTC
and CHBW(1 : 0)

reserved

format/delay control

OFTS(1 : 0), HDEL(1 : 0), VRLN and
YDEL(2 : 0)

output control 1

GPSW, X, FECO, COMPO, OEYC,
OEHV, VIPB and COLO

output control 2

RTSE(1 : 0), X, CBR, RGB888, DIT and
AOSL(1 : 0)

13 to
19

reserved

text slicer status

0, 0, 0, 0, F2VAL, F2RDY, F1VAL and
F1RDY

read only register

decoded bytes of the
text slicer

P1 and BYTE1(6 : 0)

P2 and BYTE2(6 : 0)

1D to
1E

reserved

status byte

STTC, HLCK, FIDT, GLIMT, GLIMB,
WIPA and SLTCA and CODE

read only register

1998 May 15

Philips Semiconductors

Product specification

Video Input Processor (VIP)

SAA7111

19 PACKAGE OUTLINES

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

EIAJ

Note

1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.

SOT188-2

detail X

(A )

Z D

Z E

pin 1 index

112E10

MO-047AC

10 mm

scale

92-11-17
95-03-11

PLCC68: plastic leaded chip carrier; 68 leads

SOT188-2

UNIT

min.

max.

max. max.

(1)

4.57
4.19

0.51

3.30

0.53
0.33

0.021
0.013

1.27

0.51

2.16

0.18

0.10

0.18

DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)

(1)

24.33
24.13

25.27
25.02

2.16

0.81
0.66

1.22
1.07

0.180
0.165

0.020

0.13

0.25

0.01

0.05

0.020

0.085

0.007 0.004

0.007

1.44
1.02

0.057
0.040

0.958
0.950

24.33
24.13

0.958
0.950

0.995
0.985

25.27
25.02

0.995
0.985

23.62
22.61

0.930
0.890

23.62
22.61

0.930
0.890

0.085

0.032
0.026

0.048
0.042

inches

1998 May 15

Philips Semiconductors

Product specification

Video Input Processor (VIP)

SAA7111

20 SOLDERING

20.1

Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"IC Package Databook" (order code 9398 652 90011).

20.2

Reflow soldering

Reflow soldering techniques are suitable for all PLCC and
QFP packages.

The choice of heating method may be influenced by larger
PLCC or QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

"Quality

Reference Handbook" (order code 9397 750 00192).

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250

�

20.3

Wave soldering

20.3.1

PLCC

Wave soldering techniques can be used for all PLCC
packages if the following conditions are observed:

�

A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

�

The longitudinal axis of the package footprint must be
parallel to the solder flow.

�

The package footprint must incorporate solder thieves at
the downstream corners.

20.3.2

QFP

Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

If wave soldering cannot be avoided, for QFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:

�

A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.

�

The footprint must be at an angle of 45

�

to the board

direction and must incorporate solder thieves
downstream and at the side corners.

20.3.3

ETHOD

(PLCC

AND

QFP)

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260

�

C, and

maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150

�

C within

6 seconds. Typical dwell time is 4 seconds at 250

�

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

20.4

Repairing soldered joints

Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300

�

C. When

using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320

�

CAUTION

Wave soldering is NOT applicable for all QFP
packages with a pitch (e) equal or less than 0.5 mm.

1998 May 15

Philips Semiconductors

Product specification

Video Input Processor (VIP)

SAA7111

21 DEFINITIONS

22 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

23 PURCHASE OF PHILIPS I

C COMPONENTS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I

C components conveys a license under the Philips' I

C patent to use the

components in the I

C system provided the system conforms to the I

C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

Internet: http://www.semiconductors.philips.com

Philips Semiconductors � a worldwide company

� Philips Electronics N.V. 1998

SCA60

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811

Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341

Pakistan: see Singapore

Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327

Portugal: see Spain

Romania: see Italy

Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919

Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Tel. +65 350 2538, Fax. +65 251 6500

Slovakia: see Austria

Slovenia: see Italy

South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. +27 11 470 5911, Fax. +27 11 470 5494

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 S�O PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382

Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745

Switzerland: Allmendstrasse 140, CH-8027 Z�RICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793

Turkey: Talatpasa Cad. No. 5, 80640 G�LTEPE/ISTANBUL,
Tel. +90 212 279 2770, Fax. +90 212 282 6707

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381

Uruguay: see South America

Vietnam: see Singapore

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

Argentina: see South America

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010,
Fax. +43 160 101 1210

Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773

Belgium: see The Netherlands

Brazil: see South America

Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 689 211, Fax. +359 2 689 102

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700

Colombia: see South America

Czech Republic: see Austria

Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. +45 32 88 2636, Fax. +45 31 57 0044

Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615800, Fax. +358 9 61580920

France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427

Germany: Hammerbrookstra�e 69, D-20097 HAMBURG,
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300

Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240

Hungary: see Austria

India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966

Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381

Printed in The Netherlands

655102/1200/03/pp64

Date of release: 1998 May 15

Document order number:

9397 750 03116

Электронный компонент: SAA7111H