2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

CONTENTS

FEATURES

1.1

Video decoder

1.2

Video scaler

1.3

Vertical Blanking Interval (VBI) data decoder
and slicer

1.4

Audio clock generation

1.5

Digital I/O interfaces

1.6

Miscellaneous

APPLICATIONS

GENERAL DESCRIPTION

QUICK REFERENCE DATA

ORDERING INFORMATION

BLOCK DIAGRAM

PINNING

FUNCTIONAL DESCRIPTION

8.1

Decoder

8.2

Decoder output formatter

8.3

Scaler

8.4

VBI-data decoder and capture
(subaddresses 40H to 7FH)

8.5

Image port output formatter
(subaddresses 84H to 87H)

8.6

Audio clock generation
(subaddresses 30H to 3FH)

INPUT/OUTPUT INTERFACES AND PORTS

9.1

Analog terminals

9.2

Audio clock signals

9.3

Clock and real-time synchronization signals

9.4

Video expansion port (X-port)

9.5

Image port (I-port)

9.6

Host port for 16-bit extension of video data I/O
(H-port)

9.7

Basic input and output timing diagrams I-port
and X-port

BOUNDARY SCAN TEST

10.1

Initialization of boundary scan circuit

10.2

Device identification codes

LIMITING VALUES

THERMAL CHARACTERISTICS

CHARACTERISTICS

APPLICATION INFORMATION

C-BUS DESCRIPTION

15.1

C-bus format

15.2

C-bus details

15.3

Programming register audio clock generation

15.4

Programming register VBI-data slicer

15.5

Programming register interfaces and scaler
part

PROGRAMMING START SET-UP

16.1

Decoder part

16.2

Audio clock generation part

16.3

Data slicer and data type control part

16.4

Scaler and interfaces

PACKAGE OUTLINE

SOLDERING

18.1

Introduction to soldering surface mount
packages

18.2

Reflow soldering

18.3

Wave soldering

18.4

Manual soldering

18.5

Suitability of surface mount IC packages for
wave and reflow soldering methods

DEFINITIONS

LIFE SUPPORT APPLICATIONS

PURCHASE OF PHILIPS I

C COMPONENTS

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

FEATURES

1.1

Video decoder

�

Six analog inputs, internal analog source selectors, e.g.
6

�

CVBS or (2

�

Y/C and 2

�

CVBS) or (1

�

Y/C and

�

CVBS)

�

Two analog preprocessing channels in differential
CMOS style inclusive built-in analog anti-alias filters

�

Fully programmable static gain or Automatic Gain
Control (AGC) for the selected CVBS or Y/C channel

�

Automatic Clamp Control (ACC) for CVBS, Y and C

�

Switchable white peak control

�

Two 9-bit video CMOS Analog-to-Digital Converters
(ADCs), digitized CVBS or Y/C signals are available on
the expansion port

�

On-chip line-locked clock generation according
"ITU 601"

�

Digital PLL for synchronization and clock generation
from all standards and non-standard video sources e.g.
consumer grade VTR

�

Requires only one crystal (32.11 or 24.576 MHz) for all
standards

�

Horizontal and vertical sync detection

�

Automatic detection of 50 and 60 Hz field frequency,
and automatic switching between PAL and NTSC
standards

�

Luminance and chrominance signal processing for
PAL BGDHIN, combination PAL N, PAL M, NTSC M,
NTSC-Japan, NTSC 4.43 and SECAM

�

Adaptive 2/4-line comb filter for two dimensional
chrominance/luminance separation

� Increased luminance and chrominance bandwidth for

all PAL and NTSC standards

� Reduced cross colour and cross luminance artefacts

�

PAL delay line for correcting PAL phase errors

�

Independent Brightness Contrast Saturation (BCS)
adjustment for decoder part

�

User programmable sharpness control

�

Independent gain and offset adjustment for raw data
path.

1.2

Video scaler

�

Horizontal and vertical down-scaling and up-scaling to
randomly sized windows

�

Horizontal and vertical scaling range: variable zoom to

(icon); it should be noted that the H and V zoom are

restricted by the transfer data rates

�

Anti-alias and accumulating filter for horizontal scaling

�

Vertical scaling with linear phase interpolation and
accumulating filter for anti-aliasing (6-bit phase
accuracy)

�

Horizontal phase correct up and down scaling for
improved signal quality of scaled data, especially for
compression and video phone applications, with 6-bit
phase accuracy (1.2 ns step width)

�

Two independent programming sets for scaler part, to
define two `ranges' per field or sequences over frames

�

Fieldwise switching between decoder part and
expansion port (X-port) input

�

Brightness, contrast and saturation controls for scaled
outputs.

1.3

Vertical Blanking Interval (VBI) data decoder
and slicer

�

Versatile VBI-data decoder, slicer, clock regeneration
and byte synchronization e.g. for World Standard
Teletext (WST), North-American Broadcast Text
System (NABTS), close caption, Wide Screen Signalling
(WSS) etc.

1.4

Audio clock generation

�

Generation of a field locked audio master clock to
support a constant number of audio clocks per video
field

�

Generation of an audio serial and left/right (channel)
clock signal.

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

1.5

Digital I/O interfaces

�

Real-time signal port (R port), inclusive continuous
line-locked reference clock and real-time status
information supporting RTC level 3.1 (refer to external
document

"RTC Functional Specification" for details)

�

Bi-directional expansion port (X-port) with half duplex
functionality (D1), 8-bit YUV

� Output from decoder part, real-time and unscaled

� Input to scaler part, e.g. video from MPEG decoder

(extension to 16-bit possible)

�

Video image port (I-port) configurable for 8-bit data
(extension to 16-bit possible) in master mode (own
clock), or slave mode (external clock), with auxiliary
timing and hand shake signals

�

Discontinuous data streams supported

�

32-word

�

4-byte FIFO register for video output data

�

28-word

�

4-byte FIFO register for decoded VBI output

data

�

Scaled 4 : 2 : 2, 4 : 1 : 1, 4 : 2 : 0, 4 : 1 : 0 YUV output

�

Scaled 8-bit luminance only and raw CVBS data output

�

Sliced, decoded VBI-data output.

1.6

Miscellaneous

�

Power-on control

�

5 V tolerant digital inputs and I/O ports

�

Software controlled power saving standby modes
supported

�

Programming via serial I

C-bus, full read-back ability by

an external controller, bit rate up to 400 kbits/s

�

Boundary scan test circuit complies with the

"IEEE Std.

1149.b1 - 1994".

APPLICATIONS

�

Desktop video

�

Multimedia

�

Digital television

�

Image processing

�

Video phone applications.

GENERAL DESCRIPTION

The SAA7114H is a video capture device for applications
at the image port of VGA controllers.

The SAA7114H is a combination of a two-channel analog
preprocessing circuit including source selection,
anti-aliasing filter and ADC, an automatic clamp and gain
control, a Clock Generation Circuit (CGC), a digital
multi-standard decoder containing two-dimensional
chrominance/luminance separation by an adaptive comb
filter and a high performance scaler, including variable
horizontal and vertical up and down scaling and a
brightness, contrast and saturation control circuit.

It is a highly integrated circuit for desktop video
applications. The decoder is based on the principle of
line-locked clock decoding and is able to decode the colour
of PAL, SECAM and NTSC signals into ITU 601
compatible colour component values. The SAA7114H
accepts as analog inputs CVBS or S-video (Y/C) from
TV or VCR sources, including weak and distorted signals.
An expansion port (X-port) for digital video (bi-directional
half duplex, D1 compatible) is also supported to connect to
MPEG or video phone codec. At the so called image port
(I-port) the SAA7114H supports 8 or 16-bit wide output
data with auxiliary reference data for interfacing to VGA
controllers.

The target application for SAA7114H is to capture and
scale video images, to be provided as digital video stream
through the image port of a VGA controller, for display via
VGA's frame buffer, or for capture to system memory.

In parallel SAA7114H incorporates also provisions for
capturing the serially coded data in the vertical blanking
interval (VBI-data). Two principal functions are available:

1. To capture raw video samples, after interpolation to

the required output data rate, via the scaler

2. A versatile data slicer (data recovery) unit.

SAA7114H incorporates also a field locked audio clock
generation. This function ensures that there is always the
same number of audio samples associated with a field, or
a set of fields. This prevents the loss of synchronization
between video and audio, during capture or playback.

The circuit is I

C-bus controlled (full write/read capability

for all programming registers, bit rate up to 400 kbits/s).

2000

Mar

Philips Semiconductors

Preliminar

y specification

AL/NTSC/SECAM video decoder with adaptiv

e P
AL/NTSC

comb filter

, VBI-data slicer and high perf

mance scaler

SAA7114H

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BLOCK DIA

GRAM

ll pagewidth

MHB528

FIR-PREFILTER

PRESCALER

AND

SCALER BCS

GENERAL PURPOSE

VBI-DATA SLICER

VIDEO/TEXT

ARBITER

TEXT

FIFO

VIDEO

FIFO

PROGRAMMING

ARRAY

A/B

MUX

EVENT CONTROLLER

IMAGE PORT PIN MAPPING

X PORT I/O FORMATTING

EXPANSION PORT PIN MAPPING

I/O CONTROL

C-BUS

REAL-TIME OUTPUT

LLC

AI2D

LINE
FIFO

BUFFER

VERTICAL

SCALING

HORIZONTAL

FINE

(PHASE)

SCALING

8(16)

MUX

ITRI

AGND

AI1D

AOUT

AI24

AI23

AI22

AI21

AI12

AI11

XTALO

XTALI

XTOUT

TCK

TMS

TDI

VDD(XTAL)

VSS(XTAL)

VDDD(ICO1)

VDDD(ICO6)

33, 43,
58, 68,
83, 93

VDDD(EP1)

VDDD(EP4)

1, 25,
51, 75

VDDA0

VDDA2

23, 17,
11

VSSD(ICO1)

VSSD(ICO3)

38, 63,
88

VSSD(EP1)

VSSD(EP4)

26, 50,
76, 100

VSSA0

VSSA2

24,
15, 9

AMXCLK

TDO

AMCLK

ALRCLK

ASCLK

LLC2

RTCO

RTS0

RTS1

XCLK

XDQ

81, 82,
84 to 87
89, 90

XRH

XRV

XRDY

SDA

SCL

TEST5

TEST4

TEST3

TEST2

TEST1

TEST0

64 to 67,
69 to 72

XTRI

chrominance of 16-bit input

BOUNDARY

SCAN

TEST

CLOCK GENERATION

AND

POWER-ON CONTROL

ANALOG

DUAL

ADC

DIGITAL

DECODER

WITH

ADAPTIVE

COMB

FILTER

AUDIO

CLOCK

GENERATION

ITRDY

ICLK

IGP1

IGP0

IGPV

IGPH

IDQ

54 to 57,
59 to 62

IPD[7:0]

HPD[7:0]

XPD[7:0]

RES

SAA7114H

TRST

(1)

Fig.1 Block diagram.

(1) The pins RTCO and ALRCLK are used for configuration of the I

C-bus interface

and the definition of the crystal oscillator frequency at RESET (pin strapping).

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

PINNING

SYMBOL

PIN

TYPE

DESCRIPTION

DDD(EP1)

external digital pad supply voltage 1 (+3.3 V)

TDO

test data output for boundary scan test; note 1

TDI

test data input for boundary scan test; note 1

XTOUT

crystal oscillator output signal; auxiliary signal

SS(XTAL)

ground for crystal oscillator

XTALO

24.576 MHz (32.11 MHz) crystal oscillator output; not connected if TTL clock
input of XTALI is used

XTALI

input terminal for 24.576 MHz (32.11 MHz) crystal oscillator or connection of
external oscillator with TTL compatible square wave clock signal

DD(XTAL)

supply voltage for crystal oscillator

SSA2

ground for analog inputs AI2n

AI24

analog input 24

DDA2

analog supply voltage for analog inputs AI2n (+3.3 V)

AI23

analog input 23

AI2D

differential input for ADC channel 2 (pins AI24, AI23, AI22 and AI21)

AI22

analog input 22

SSA1

ground for analog inputs AI1n

AI21

analog input 21

DDA1

analog supply voltage for analog inputs AI1n (+3.3 V)

AI12

analog input 12

AI1D

differential input for ADC channel 1 (pins AI12 and AI11)

AI11

analog input 11

AGND

analog ground connection

AOUT

do not connect; analog test output

DDA0

analog supply voltage (+3.3 V) for internal Clock Generation Circuit (CGC)

SSA0

ground for internal clock generation circuit

DDD(EP2)

external digital pad supply voltage 2 (+3.3 V)

SSD(EP1)

external digital pad supply ground 1

chip enable or reset input (with internal pull-up)

LLC

line-locked system clock output (27 MHz nominal)

LLC2

line-locked

clock output (13.5 MHz nominal)

RES

reset output (active LOW)

SCL

I(/O)

serial clock input (I

C-bus) with inactive output path

SDA

I/O

serial data input/output (I

C-bus)

DDD(ICO1)

internal digital core supply voltage 1 (+3.3 V)

RTS0

real-time status or sync information, controlled by subaddresses 11H and 12H;
see Section 15.2.18, 15.2.19 and 15.2.20

RTS1

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

RTCO

(I/)O

real-time control output; contains information about actual system clock
frequency, field rate, odd/even sequence, decoder status, subcarrier frequency
and phase and PAL sequence (see external document

"RTC Functional

Description", available on request); the RTCO pin is enabled via I

C-bus

bit RTCE; see notes 2, 3 and Table 34

AMCLK

audio master clock output, up to 50% of crystal clock

SSD(ICO1)

internal digital core supply ground 1

ASCLK

audio serial clock output

ALRCLK

(I/)O

audio left/right clock output; can be strapped to supply via a 3.3 k

resistor to

indicate that the default 24.576 MHz crystal (ALRCLK = 0; internal pull-down)
has been replaced by a 32.110 MHz crystal (ALRCLK = 1); see notes 2 and 4

AMXCLK

audio master external clock input

ITRDY

target ready input, image port (with internal pull-up)

DDD(ICO2)

internal digital core supply voltage 2 (+3.3 V)

TEST0

do not connect; reserved for future extensions and for testing: scan output

ICLK

I/O

clock output signal for image port, or optional asynchronous back-end clock
input

IDQ

output data qualifier for image port (optional: gated clock output)

ITRI

I(/O)

image port output control signal, effects all input port pins inclusive ICLK, enable
and active polarity is under software control (bits IPE in subaddress 87H); output
path used for testing: scan output

IGP0

general purpose output signal 0; image port (controlled by subaddresses
84H and 85H)

IGP1

general purpose output signal 1; image port (controlled by subaddresses
84H and 85H)

SSD(EP2)

external digital pad supply ground 2

DDD(EP3)

external digital pad supply voltage 3 (+3.3 V)

IGPV

multi purpose vertical reference output signal; image port (controlled by
subaddresses 84H and 85H)

IGPH

multi purpose horizontal reference output signal; image port (controlled by
subaddresses 84H and 85H)

IPD7 to IPD4

54 to 57

image port data outputs

DDD(ICO3)

internal digital core supply voltage 3 (+3.3 V)

IPD3 to IPD0

59 to 62

image port data output

SSD(ICO2)

internal digital core supply ground 2

HPD7 to HPD4

64 to 67

I/O

host port data I/O, carries UV chrominance information in 16-bit video I/O modes

DDD(ICO4)

internal digital core supply voltage 4 (+3.3 V)

HPD3 to HPD0

69 to 72

I/O

host port data I/O, carries UV chrominance information in 16-bit video I/O modes

TEST1

do not connect; reserved for future extensions and for testing: scan input

TEST2

do not connect; reserved for future extensions and for testing: scan input

DDD(EP4)

external digital pad supply voltage 4 (+3.3 V)

SSD(EP3)

external digital pad supply ground 3

TEST3

do not connect; reserved for future extensions and for testing: scan input

SYMBOL

PIN

TYPE

DESCRIPTION

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

Notes

1. In accordance with the

"IEEE1149.1" standard the pads TDI, TMS, TCK and TRST are input pads with an internal

pull-up transistor and TDO is a 3-state output pad.

2. Pin strapping is done by connecting the pin to supply via a 3.3 k

resistor. During the power-up reset sequence the

corresponding pins are switched to input mode to read the strapping level. For the default setting no strapping
resistor is necessary (internal pull-down).

3. Pin RTCO: operates as I

C-bus slave address pin; RTCO = 0 slave address 42H/43H (default); RTCO = 1 slave

address 40H/41H.

4. Pin ALRCLK: 0 = 24.576 MHz crystal (default); 1 = 32.110 MHz crystal.

5. For board design without boundary scan implementation connect the TRST pin to ground.

6. This pin provides easy initialization of the Boundary Scan Test (BST) circuit. TRST can be used to force the Test

Access Port (TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once.

TEST4

do not connect; reserved for future extensions and for testing: scan output

TEST5

do not connect; reserved for future extensions and for testing: scan input

XTRI

X-port output control signal, affects all X-port pins (XPD7 to XPD0, XRH, XRV,
XDQ and XCLK), enable and active polarity is under software control (bits XPE
in subaddress 83H)

XPD7

I/O

expansion port data

XPD6

I/O

expansion port data

DDD(ICO5)

internal digital core supply voltage 5 (+3.3 V)

XPD5 to XPD2

84 to 87

I/O

expansion port data

SSD(ICO3)

internal digital core supply ground 3

XPD1

I/O

expansion port data

XPD0

I/O

expansion port data

XRV

I/O

vertical reference I/O expansion port

XRH

I/O

horizontal reference I/O expansion port

DDD(ICO6)

internal digital core supply voltage 6 (+3.3 V)

XCLK

I/O

clock I/O expansion port

XDQ

I/O

data qualifier I/O expansion port

XRDY

task flag or ready signal from scaler, controlled by XRQT

TRST

test reset input (active LOW), for boundary scan test (with internal pull-up);
notes 5 and 6

TCK

test clock for boundary scan test; note 1

TMS

test mode select input for boundary scan test or scan test; note 1

SSD(EP4)

100

external digital pad supply ground 4

SYMBOL

PIN

TYPE

DESCRIPTION

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

Fig.2 Pin configuration.

handbook, full pagewidth

XTRI

TEST5

TEST4

TEST3

SSD(EP3)

VDDD(EP4)

TEST2

TEST1

HPD0

HPD1

HPD2

HPD3

VDDD(ICO4)

HPD4

HPD5

HPD6

HPD7

VSSD(ICO2)

IPD0

IPD1

IPD2

IPD3

VDDD(ICO3)

IPD4

IPD5

IPD6

IPD7

IGPH

IGPV

VDDD(EP3)

VDDD(EP1)

TDO

TDI

XTOUT

VSS(XTAL)

XTALO

XTALI

VDD(XTAL)

VSSA2

AI24

VDDA2

AI23

AI2D

AI22

VSSA1

AI21

VDDA1

AI12

AI1D

AI11

AGND

AOUT

VDDA0

VSSA0

VDDD(EP2)

SSD(EP4)

TMS

TCK

XRDY

XDQ

XCLK

DDD(ICO6)

XRH

XRV

XPD0

XPD1

SSD(ICO3)

XPD2

XPD3

XPD4

XPD5

DDD(ICO5)

XPD6

XPD7

SCL

SDA

DDD(ICO1)

RTS0

RTS1

RTCO

AMCLK

SSD(ICO1)

ASCLK

ALRCLK

AMXCLK

ITRDY

DDD(ICO2)

TEST0

ICLK

IDQ

ITRI

IGP0

IGP1

SSD(EP2)

SSD(EP1)

LLC

LLC2

100

SAA7114H

RES

TRST

MHB529

2000

Mar

Philips Semiconductors

Preliminar

y specification

AL/NTSC/SECAM video decoder with adaptiv

e P
AL/NTSC

comb filter

, VBI-data slicer and high perf

mance scaler

SAA7114H

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Table 1

8-bit/16-bit and alternative pin functional configurations

PIN

SYMBOL

8-BIT

INPUT

MODES

16-BIT INPUT

MODES (ONLY

FOR I

C-BUS

PROGRAMMING)

ALTERNATIVE

INPUT

FUNCTIONS

8-BIT

OUTPUT

MODES

16-BIT OUTPUT

MODES (ONLY

FOR I

C-BUS

PROGRAMMING)

ALTERNATIVE

OUTPUT

FUNCTIONS

I/O

CONFIGURATION

PROGRAMMING

BITS

81, 82,
84 to 87,
89, 90

XPD7 to
XPD0

D1 data
input

Y data input

D1
decoder
output

XCODE[92H[3]]
XPE[1:0]83H[1:0]
+ pin XTRI

XCLK

clock
input

gated clock
input

decoder
clock
output

XPE[1:0]83H[1:0]
+ pin XTRI
XPCK[1:0]83H[5:4]
XCKS[92H[0]]

XDQ

data
qualifier
input

data
qualifier
output
(HREF and
VREF
gate)

XDQ[92H[1]]
XPE[1:0]83H[1:0]
+ pin XTRI

XRDY

input
ready
output

active task A/B
flag

XRQT[83H[2]]
XPE[1:0]83H[1:0]
+ pin XTRI

XRH

horizontal
reference
input

decoder
horizontal
reference
output

XDH[92H[2]]
XPE[1:0]83H[1:0]
+ pin XTRI

XRV

vertical
reference
input

decoder
vertical
reference
output

XDV[1:0]92H[5:4]
XPE[1:0]83H[1:0]
+ pin XTRI

XTRI

output
enable
input

XPE[1:0]83H[1:0]

64 to 67,
69 to 72

HPD7 to
HPD0

UV data input

UV scaler output

ICODE[93H[7]]
ISWP[1:0]85H[7:6]
I8_16[93H[6]]
IPE[1:0]87H[1:0]
+ pin ITRI

2000

Mar

Philips Semiconductors

Preliminar

y specification

AL/NTSC/SECAM video decoder with adaptiv

e P
AL/NTSC

comb filter

, VBI-data slicer and high perf

mance scaler

SAA7114H

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54 to 57,
59 to 62

IPD7 to
IPD0

D1 scaler
output

Y scaler output

ICODE[93H[7]]
ISWP[1:0]85H[7:6]
I8_16[93H[6]]
IPE[1:0]87H[1:0]
+ pin ITRI

ICLK

clock
output

clock input

ICKS[1:0]80H[1:0]
IPE[1:0]87H[1:0]
+ pin ITRI

IDQ

data
qualifier
output

gated clock
output

ICKS[3:2]80H[3:2]
IDQP[85H[0]]
IPE[1:0]87H[1:0]
+ pin ITRI

ITRDY

target
ready input

IGPH

H-gate
output

extended
H-gate,
horizontal
pulses

IDH[1:0]84H[1:0]
IRHP[85H[1]]
IPE[1:0]87H[1:0]
+ pin ITRI

IGPV

V-gate
output

V-sync, vertical
pulses

IDV[1:0]84H[3:2]
IRVP[85H[2]]
IPE[1:0]87H[1:0]
+ pin ITRI

IGP1

general
purpose

IDG1[1:0]84H[5:4]
IG1P[85H[3]]
IPE[1:0]87H[1:0]
+ pin ITRI

IGP0

general
purpose

IDG0[1:0]84H[7:6]
IG0P[85H[4]]
IPE[1:0]87H[1:0]
+ pin ITRI

ITRI

output
enable
input

PIN

SYMBOL

8-BIT

INPUT

MODES

16-BIT INPUT

MODES (ONLY

FOR I

C-BUS

PROGRAMMING)

ALTERNATIVE

INPUT

FUNCTIONS

8-BIT

OUTPUT

MODES

16-BIT OUTPUT

MODES (ONLY

FOR I

C-BUS

PROGRAMMING)

ALTERNATIVE

OUTPUT

FUNCTIONS

I/O

CONFIGURATION

PROGRAMMING

BITS

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

8.1.2.1

Clamping

The clamp control circuit controls the correct clamping of
the analog input signals. The coupling capacitor is also
used to store and filter the clamping voltage. An internal
digital clamp comparator generates the information with
respect to clamp-up or clamp-down. The clamping levels
for the two ADC channels are fixed for luminance (60) and
chrominance (128). Clamping time in normal use is set
with the HCL pulse at the back porch of the video signal.

8.1.2.2

Gain control

The gain control circuit receives (via the I

C-bus) the static

gain levels for the two analog amplifiers or controls one of
these amplifiers automatically via a built-in Automatic Gain
Control (AGC) as part of the Analog Input Control (AICO).

The AGC (automatic gain control for luminance) is used to
amplify a CVBS or Y signal to the required signal
amplitude, matched to the ADCs input voltage range.
The AGC active time is the sync bottom of the video signal.

Signal (white) peak control limits the gain at signal
overshoots. The flow charts (see Figs 7 and 8) show more
details of the AGC. The influence of supply voltage
variation within the specified range is automatically
eliminated by clamp and automatic gain control.

Fig.4

Analog line with clamp (HCL) and gain
range (HSY).

handbook, halfpage

HCL

MGL065

HSY

analog line blanking

TV line

255

GAIN

CLAMP

Fig.5 Automatic gain range.

handbook, halfpage

analog input level

controlled

ADC input level

maximum

minimum

range 9 dB

0 dB

MHB325

3 dB

6 dB

(1 V (p-p) 18/56

)

2000

Mar

Philips Semiconductors

Preliminar

y specification

AL/NTSC/SECAM video decoder with adaptiv

e P
AL/NTSC

comb filter

, VBI-data slicer and high perf

mance scaler

SAA7114H

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dbook, full pagewidth

MHB530

HOLDG
GAFIX
WPOFF
GUDL0-GUDL2
GAI20-GAI28
GAI10-GAI18
HLNRS
UPTCV

MODE 3
MODE 2
MODE 1
MODE 0

HSY

HCL

GLIMB
GLIMT
WIPA
SLTCA

ANALOG CONTROL

VBSL

SOURCE

SWITCH

CLAMP

CIRCUIT

ANALOG

AMPLIFIER

DAC9

ANTI-ALIAS

FILTER

BYPASS
SWITCH

ADC2

SOURCE

SWITCH

CLAMP

CIRCUIT

ANALOG

AMPLIFIER

DAC9

ANTI-ALIAS

FILTER

BYPASS
SWITCH

ADC1

VBLNK
SVREF

CROSS MULTIPLEXER

VERTICAL

BLANKING

CONTROL

CLAMP

CONTROL

GAIN

CONTROL

ANTI-ALIAS

CONTROL

MODE

CONTROL

FUSE [1:0]

AOSL [1:0]

AGND

CVBS/CHR

CVBS/LUM

AD1BYP

AD2BYP

AOUT

10, 12,
14, 16

AI2D

AI12

AI24 to AI21

AI1D

AI11

TEST

SELECTOR

AND

BUFFER

VDDA1

VSSA2

VDDA2

VSSA1

Fig.6 Analog input processing using the SAA7114H as differential front-end with 9-bit ADC.

2000

Mar

Philips Semiconductors

Preliminar

y specification

AL/NTSC/SECAM video decoder with adaptiv

e P
AL/NTSC

comb filter

, VBI-data slicer and high perf

mance scaler

SAA7114H

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8.1.3

OMINANCE

AND

LUMINANCE

PR
OCESSING

dbook, full pagewidth

MHB532

CVBS-IN

or CHR-IN

CODE

SECS

HUEC

DCVF

QUADRATURE

DEMODULATOR

PAL DELAY LINE

SECAM

RECOMBINATION

PHASE

DEMODULATOR

AMPLITUDE

DETECTOR

BURST GATE

ACCUMULATOR

LOOP FILTER

LOW-PASS 1

DOWNSAMPLING

SUBCARRIER

GENERATION 2

FCTC

ACGC

CGAIN[6:0]

IDEL[3:0]

INCS

RTCO

UV-

ADJUSTMENT

SECAM

PROCESSING

fH/2 switch signal

ADAPTIVE

COMB FILTER

CCOMB
YCOMB

LDEL

BYPS

LUFI[3:0]

CSTD[2:0]

YDEL[2:0]

LOW-PASS 2

CHBW

CHROMA

GAIN

CONTROL

INTERPOLATION

LOW-PASS 3

LUBW

QUADRATURE

MODULATOR

CDTO

CSTD[2:0]

SUBCARRIER

GENERATION 1

CHROMINANCE

INCREMENT

DTO-RESET

SUBCARRIER

INCREMENT

GENERATION

AND

DIVIDER

CHROMINANCE

INCREMENT

DELAY

LDEL
YCOMB

SUBTRACTOR

DELAY

COMPENSATION

CVBS-IN

or Y-IN

CHR

LUMINANCE-PEAKING

LOW-PASS,

Y-DELAY ADJUSTMENT

LCBW[2:0]

Y/CVBS

DBRI[7:0]

DCON[7:0]

DSAT[7:0]

RAWG[7:0]
RAWO[7:0]

COLO

BRIGHTNESS

CONTRAST

SATURATION

CONTROL

RAW DATA

GAIN AND

OFFSET

CONTROL

LDEL

YCOMB

Y-OUT/
CVBS OUT

UV-OUT

HREF-OUT

SET_RAW

SET_VBI

SET_RAW

SET_VBI

SET_RAW

SET_VBI

SET_RAW

SET_VBI

Fig.9 Chrominance and luminance processing.

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

8.1.3.1

Chrominance path

The 9-bit CVBS or chrominance input signal is fed to the
input of a quadrature demodulator, where it is multiplied by
two time-multiplexed subcarrier signals from the subcarrier
generation block 1 (0

�

and 90

�

phase relationship to the

demodulator axis). The frequency is dependent on the
chosen colour standard.

The time-multiplexed output signals of the multipliers are
low-pass filtered (low-pass 1). Eight characteristics are
programmable via LCWB3 to LCWB0 to achieve the
desired bandwidth for the colour difference signals (PAL,
NTSC) or the 0

�

and 90

�

FM signals (SECAM).

The chrominance low-pass 1 characteristic also influences
the grade of cross-luminance reduction during horizontal
colour transients (large chrominance bandwidth means
strong suppression of cross-luminance). If the Y-comb
filter is disabled by YCOMB = 0 the filter influences directly
the width of the chrominance notch within the luminance
path (large chrominance bandwidth means wide
chrominance notch resulting to lower luminance
bandwidth).

The low-pass filtered signals are fed to the adaptive comb
filter block. The chrominance components are separated
from the luminance via a two line vertical stage (four lines
for PAL standards) and a decision logic between the
filtered and the non-filtered output signals. This block is
bypassed for SECAM signals. The comb filter logic can be
enabled independently for the succeeding luminance and
chrominance processing by YCOMB (subaddress 09H,
bit 6) and/or CCOMB (subaddress 0EH, bit 0). It is always
bypassed during VBI or raw data lines programmable by
the LCRn registers (subaddresses 41H to 57H), see
Section 8.2.

The separated UV-components are further processed by a
second filter stage (low-pass 2) to modify the chrominance
bandwidth without influence to the luminance path. It's
characteristic is controlled by CHBW (subaddress 10H,
bit 3). For the complete transfer characteristic of
low-passes 1 and 2 see Figs 10 and 11.

The SECAM processing (bypassed for QUAM standards)
contains the following blocks:

�

Baseband `bell' filters to reconstruct the amplitude and
phase equalized 0

�

and 90

�

FM signals

�

Phase demodulator and differentiator
(FM-demodulation)

�

De-emphasis filter to compensate the pre-emphasized
input signal, including frequency offset compensation
(DB or DR white carrier values are subtracted from the
signal, controlled by the SECAM switch signal).

The succeeding chrominance gain control block amplifies
or attenuates the UV-signal according to the required
ITU 601/656 levels. It is controlled by the output signal
from the amplitude detection circuit within the burst
processing block.

The burst processing block provides the feedback loop of
the chrominance PLL and contains:

�

Burst gate accumulator

�

Colour identification and killer

�

Comparison nominal/actual burst amplitude
(PAL/NTSC standards only)

�

Loop filter chrominance gain control
(PAL/NTSC standards only)

�

Loop filter chrominance PLL (only active for
PAL/NTSC standards)

�

PAL/SECAM sequence detection, H/2-switch
generation.

The increment generation circuit produces the Discrete
Time Oscillator (DTO) increment for both subcarrier
generation blocks. It contains a division by the increment
of the line-locked clock generator to create a stable
phase-locked sine signal under all conditions (e.g. for
non-standard signals).

The PAL delay line block eliminates crosstalk between the
chrominance channels in accordance with the
PAL standard requirements. For NTSC colour standards
the delay line can be used as an additional vertical filter.
If desired, it can be switched off by DCVF = 1. It is always
disabled during VBI or raw data lines programmable by the
LCRn registers (subaddresses 41H to 47H), see
Section 8.2. The embedded line delay is also used for
SECAM recombination (cross-over switches).

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

8.1.3.2

Luminance path

The rejection of the chrominance components within the
9-bit CVBS or Y input signal is done by subtracting the
re-modulated chrominance signal from the CVBS input.

The comb filtered UV-components are interpolated
(upsampled) by the low-pass 3 block. It's characteristic is
controlled by LUBW (subaddress 09H, bit 4) to modify the
width of the chrominance `notch' without influence to the
chrominance path. The programmable frequency
characteristics available in conjunction with the
LCBW2 to LCBW0 settings can be seen in Figs 12 to 15.
Note that these frequency curves are only valid for Y-comb
disabled filter mode (YCOMB = 0). in comb filter mode the
frequency response is flat. The centre frequency of the
notch is automatically adapted to the chosen colour
standard.

The interpolated UV-samples are multiplied by two
time-multiplexed subcarrier signals from the subcarrier
generation block 2. This second DTO is locked to the first
subcarrier generator by an increment delay circuit
matched to the processing delay, which is different for
PAL and NTSC standards according to the chosen comb
filter algorithm. The two modulated signals are finally
added to build the re-modulated chrominance signal.

The frequency characteristic of the separated luminance
signal can be further modified by the succeeding
luminance filter block. It can be configured as peaking
(resolution enhancement) or low-pass block by
LUFI3 to LUFI0 (subaddress 09H, bits 3 to 0). The 16
resulting frequency characteristics can be seen in Fig.16.
The LUFI3 to LUFI0 settings can be used as a user
programmable sharpness control.

The luminance filter block also contains the adjustable
Y-delay part; programmable by YDEL2 to YDEL0
(subaddress 11H, bits 2 to 0).

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

8.1.3.3

Brightness Contrast Saturation (BCS) control and decoder output levels

The resulting Y (CVBS) and UV-signals are fed to the BCS block, which contains the following functions:

�

Chrominance saturation control by DSAT7 to DSAT0

�

Luminance contrast and brightness control by DCON7 to DCON0 and DBRI7 to DBRI0

�

Raw data (CVBS) gain and offset adjustment by RAWG7 to RAWG0 and RAWO7 to RAWO0

�

Limiting YUV or CVBS to the values 1 (minimum) and 254 (maximum) to fulfil

"ITU Recommendation 601/656".

Fig.17 YUV range for scaler input and X-port output.

"ITU Recommendation 601/656" digital levels with default BCS (decoder) settings DCON[7:0] = 44H, DBRI[7:0] = 80H and DSAT[7:0] = 40H.

Equations for modification to the YUV levels via BCS control I

C-bus bytes DBRI, DCON and DSAT.

Luminance:

Chrominance:

It should be noted that the resulting levels are limited to 1 to 254 in accordance with

"ITU Recommendation 601/656" .

OUT

Int

DCON

-----------------

128

�

(

)

�

DBRI

OUT

Int

DSAT

----------------

128

�

(

)

�

128

ndbook, full pagewidth

LUMINANCE 100%

255

235

128

white

black

U-COMPONENT

255

240

212

128

blue 100%

blue 75%

yellow 75%

yellow 100%

colourless

V-COMPONENT

255

240

128

red 100%

red 75%

cyan 75%

cyan 100%

colourless

MGC634

a. Y output range.

b. U output range (C

c. V output range (C

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

8.1.4

YNCHRONIZATION

The prefiltered luminance signal is fed to the
synchronization stage. Its bandwidth is further reduced to
1 MHz in a low-pass filter. The sync pulses are sliced and
fed to the phase detectors where they are compared with
the sub-divided clock frequency. The resulting output
signal is applied to the loop filter to accumulate all phase
deviations. Internal signals (e.g. HCL and HSY) are
generated in accordance with analog front-end
requirements. The loop filter signal drives an oscillator to
generate the line frequency control signal LFCO,
see Fig.19.

The detection of `pseudo syncs' as part of the macrovision
copy protection standard is also done within the
synchronization circuit.

The result is reported as flag COPRO within the decoder
status byte at subaddress 1FH.

8.1.5

LOCK GENERATION CIRCUIT

The internal CGC generates all clock signals required for
the video input processor.

The internal signal LFCO is a digital-to-analog converted
signal provided by the horizontal PLL. It is the multiple of
the line frequency:

6.75 MHz = 429

�

(50 Hz), or

6.75 MHz = 432

�

(60 Hz).

Internally the LFCO signal is multiplied by a factor of
2 and 4 in the PLL circuit (including phase detector, loop
filtering, VCO and frequency divider) to obtain the output
clock signals. The rectangular output clocks have a 50%
duty factor.

Table 2

Decoder clock frequencies

CLOCK

FREQUENCY (MHz)

XTALO

24.576 or 32.110

LLC

LLC2

13.5

LLC4 (internal)

6.75

LLC8 (virtual)

3.375

Fig.19 Block diagram of the clock generation circuit.

handbook, full pagewidth

BAND PASS

FC = LLC/4

ZERO

CROSS

DETECTION

PHASE

DETECTION

LOOP

FILTER

DIVIDER

1/2

DIVIDER

1/2

OSCILLATOR

MHB330

LLC2

LLC

LFCO

8.1.6

OWER

ON RESET AND

HIP

NABLE

(CE)

INPUT

A missing clock, insufficient digital or analog V

DDA0

supply

voltages (below 2.7 V) will start the reset sequence; all
outputs are forced to 3-state (see Fig.20). The indicator
output RES is LOW for about 128 LLC after the internal
reset and can be applied to reset other circuits of the digital
TV system.

It is possible to force a reset by pulling the Chip Enable
(CE) to ground. After the rising edge of CE and sufficient
power supply voltage, the outputs LLC, LLC2 and SDA
return from 3-state to active, while the other signals have
to be activated via programming.

2000 Mar 15

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Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

8.2

Decoder output formatter

The output interface block of the decoder part contains the
ITU 656 formatter for the expansion port data output
XPD7 to XPD0 (for a detailed description see
Section 9.4.1) and the control circuit for the signals
needed for the internal paths to the scaler and data slicer
part. It also controls the selection of the reference signals
for the RT port (RTCO, RTS0 and RTS1) and the
expansion port (XRH, XRV and XDQ).

The generation of the decoder data type control signals
SET_RAW and SET VBI is also done within this block.
These signals are decoded from the requested data type
for the scaler input and/or the data slicer, selectable by the
control registers LCR2 to LCR24 (see also Chapter 15
"I

C-bus description", subaddresses 41H to 57H).

For each LCR value from 2 to 23 the data type can be
programmed individually. LCR2 to LCR23 refer to line
numbers. The selection in LCR24 values is valid for the
rest of the corresponding field. The upper nibble contains
the value for field 1 (odd), the lower nibble for field 2
(even). The relationship between LCR values and line
numbers can be adjusted via VOFF8 to VOFF0, located in
subaddresses 5BH (bit 4) and 5AH (bits 7 to 0) and FOFF
subaddress 5BH (bit D7). The recommended values are
VOFF[8:0] = 03H for 50 Hz sources (with FOFF = 0) and
VOFF[8:0] = 06H for 60 Hz sources (with FOFF = 1), to
accommodate line number conventions as used for PAL,
SECAM and NTSC standards; see Tables 4 to 7.

Table 3

Data formats at decoder output

DATA TYPE NUMBER

DATA TYPE

DECODER OUTPUT DATA FORMAT

teletext EuroWST, CCST

raw

European closed caption

raw

Video Programming Service (VPS)

raw

Wide screen signalling bits

raw

US teletext (WST)

raw

US closed caption (line 21)

raw

video component signal, VBI region

YUV 4 : 2 : 2

CVBS data

raw

teletext

raw

VITC/EBU time codes (Europe)

raw

VITC/SMPTE time codes (USA)

raw

reserved

raw

US NABTS

raw

MOJI (Japanese)

raw

Japanese format switch (L20/22)

raw

video component signal, active video region

YUV 4 : 2 : 2

2000

Mar

Philips Semiconductors

Preliminar

y specification

AL/NTSC/SECAM video decoder with adaptiv

e P
AL/NTSC

comb filter

, VBI-data slicer and high perf

mance scaler

SAA7114H

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Table 4

Relationship of LCR to line numbers in 525 lines/60 Hz systems (part 1)

Vertical line offset, VOFF[8:0] = 06H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and
59H[7:0]); FOFF = 1 (subaddress 5BH[7])

Table 5

Relationship of LCR to line numbers in 525 lines/60 Hz systems (part 2)

Vertical line offset, VOFF[8:0] = 06H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and
59H[7:0]); FOFF = 1 (subaddress 5BH[7])

Table 6

Relationship of LCR to line numbers in 625 lines/50 Hz systems (part 1)

Vertical line offset, VOFF[8:0] = 03H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and
59H[7:0]); FOFF = 1 (subaddress 5BH[7])

Table 7

Relationship of LCR to line numbers in 625 lines/50 Hz systems (part 2)

Vertical line offset, VOFF[8:0] = 03H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and
59H[7:0]); FOFF = 1 (subaddress 5BH[7])

Line number
(1st field)

521

522

523

524

525

active video

equalization pulses

serration pulses

equalization pulses

Line number
(2nd field)

259

260

261

262

263

264

265

266

267

268

269

270

271

272

active video

equalization pulses

serration pulses

equalization pulses

LCR

Line number
(1st field)

nominal VBI-lines F1

active video

Line number
(2nd field)

273

274

275

276

277

278

279

280

281

282

283

284

285

286

287

288

nominal VBI-lines F2

active video

LCR

Line number
(1st field)

621

622

623

624

625

active video

equalization pulses

serration pulses

equalization pulses

Line number
(2nd field)

309

310

311

312

313

314

315

316

317

318

active video

equalization pulses

serration pulses

equalization pulses

LCR

Line number
(1st field)

nominal VBI-lines F1

active video

Line number
(2nd field)

319

320

321

322

323

324

325

326

327

328

329

330

331

332

333

334

335

336

337

338

nominal VBI-lines F2

active video

LCR

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

Fig.21 Vertical timing diagram for 50 Hz/625 line systems.

(1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during

the falling edge of V123, the field is ODD (field 1). If HREF is inactive during the falling edge of V123, the field
is EVEN. The specific position of the slope is dependent on the internal processing delay and may change a
few clock cycles from version to version.

The control signals listed above are available on pins RTS0, RTS1, XRH and XRV according to the following table:

For further information see Section 15.2: Tables 55, 56 and 57.

NAME

RTS0 (PIN 34) RTS1 (PIN 35)

XRH (PIN 92)

XRV (PIN 91)

HREF

F_ITU656

V123

VGATE

FID

handbook, full pagewidth

MHB540

VGATE

VSTO[8:0] = 134H

VSTA[8:0] = 15H

(a) 1st field

CVBS

ITU counting

single field counting

1
1

2
2

3
3

4
4

5
5

6
6

7
7

. . .
. . .

22
22

625
312

624
311

623
310

622
309

23
23

FID

HREF

F_ITU656

V123

(1)

VGATE

CVBS

ITU counting

single field counting

FID

HREF

F_ITU656

V123

(1)

VSTO[8:0] = 134H

VSTA[8:0] = 15H

(b) 2nd field

313
313

314

315

316

317

318

319

. . .
. . .

335

312
312

311
311

310
310

309
309

336

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

Fig.22 Vertical timing diagram for 60 Hz/525 line systems.

(1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during

The control signals listed above are available on pins RTS0, RTS1, XRH and XRV according to the following table:

For further information see Section 15.2: Tables 55, 56 and 57.

NAME

RTS0 (PIN 34) RTS1 (PIN 35)

XRH (PIN 92)

XRV (PIN 91)

HREF

F_ITU656

V123

VGATE

FID

handbook, full pagewidth

MHB541

VGATE

VSTO[8:0] = 101H

VSTA[8:0] = 011H

(a) 1st field

CVBS

ITU counting

single field counting

4
4

5
5

6
6

7
7

8
8

9
9

10
10

. . .
. . .

21
21

3
3

2
2

1
1

525
262

22
22

FID

HREF

F_ITU656

V123

(1)

VGATE

CVBS

ITU counting

single field counting

FID

HREF

F_ITU656

V123

(1)

VSTO[8:0] = 101H

VSTA[8:0] = 011H

(b) 2nd field

266

267

268

269

270

271

272

. . .
. . .

284

265

264

263
263

262
262

285

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

8.3

Scaler

The High Performance video Scaler (HPS) is based on the
system as implemented in SAA7140, but enhanced in
some aspects. Vertical upsampling is supported and the
processing pipeline buffer capacity is enhanced, to allow
more flexible video stream timing at the image port,
discontinuous transfers, and handshake. The internal data
flow from block to block is discontinuous dynamically, due
to the scaling process itself.

The flow is controlled by internal data valid and data
request flags (internal handshake signalling) between the
sub-blocks. Therefore the entire scaler acts as a pipeline
buffer. Depending on the actually programmed scaling
parameters the effective buffer can exceed to an entire
line. The access/bandwidth requirements to the VGA
frame buffer are reduced significantly.

The high performance video scaler in SAA7114H has the
following major blocks.

�

Acquisition control (horizontal and vertical timer) and
task handling (the region/field/frame based processing)

�

Prescaler, for horizontal down-scaling by an integer
factor, combined with appropriate band limiting filters,
especially anti-aliasing for CIF format

�

Brightness, saturation, contrast control for scaled output
data

�

Line buffer, with asynchronous read and write, to
support vertical up-scaling (e.g. for videophone
application, converting 240 into 288 lines, YUV 4 : 2 : 2)

�

Vertical scaling, with phase accurate Linear Phase
Interpolation (LPI) for zoom and down-scale, or phase
accurate Accumulation Mode (ACM) for large
down-scaling ratios and better alias suppression

�

Variable Phase Delay (VPD), operates as horizontal
phase accurate interpolation for arbitrary non-integer
scaling ratios, supporting conversion between square
(SQR) and rectangular (CCIR) pixel sampling

�

Output formatter for scaled YUV 4 : 2 : 2, YUV 4 : 1 : 1
and Y only (format also for raw data)

�

FIFO, 32-bit wide, with 64 pixel capacity in YUV formats

�

Output interface, 8 or 16 (only if extended by H-port)
data pins wide, synchronous or asynchronous
operation, with stream events on discrete pins, or coded
in the data stream.

The overall H and V zooming (HV_zoom) is restricted by
the input/output data rate relations. With a safety margin of
2% for running in and running out, the maximum
HV_zoom is equal to:

For example:

1. Input from decoder: 50 Hz, 720 pixel, 288 lines, 16-bit

data at 13.5 MHz data rate, 1 cycle per pixel;
output: 8-bit data at 27 MHz, 2 cycles per pixel;
the maximum HV_zoom is equal to:

2. Input from X-port: 60 Hz, 720 pixel, 240 lines, 8-bit

data at 27 MHz data rate (ITU 656), 2 cycles per pixel;
output via I + H-port: 16-bit data at 27 MHz clock,
1 cycle per pixel; the maximum HV_zoom is equal to:

The video scaler receives its input signal from the video
decoder or from the expansion port (X-port).
It gets 16-bit YUV 4 : 2 : 2 input data at a continuous rate
of 13.5 MHz from the decoder. Discontinuous data stream
can be accepted from the expansion port (X-port),
normally 8-bit wide ITU 656 like YUV data, accompanied
by a pixel qualifier on XDQ.

The input data stream is sorted into two data paths, one for
luminance (or raw samples), and one for time multiplexed
chrominance U and V samples. An YUV 4 : 1 : 1 input
format is converted to 4 : 2 : 2 for the horizontal prescaling
and vertical filter scaling operation.

The scaler operation is defined by two programming
pages A and B, representing two different tasks, that can
be applied field alternating or to define two regions in a
field (e.g. with different scaling range, factors, and signal
source during odd and even fields).

Each programming page contains control:

�

For signal source selection and formats

�

For task handling and trigger conditions

�

For input and output acquisition window definition

�

For H-prescaler, V-scaler and H-phase scaling.

0.98

T_input_field

T_v_blanking

�

in_pixel

in_lines

�

out_cycle_per_pix

�

T_out_clk

�

--------------------------------------------------------------------------------------------------------------------------------------

�

0.98

20 ms

�

720

288

�

37 ns

�

--------------------------------------------------------

1.18

�

0.98

16.666 ms

�

720

240

�

37 ns

�

--------------------------------------------------------------

2.34

�

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

Raw VBI-data will be handled as specific input format and
need an own programming page (= own task).

In VBI pass through operation the processing of prescaler
and vertical scaling has to be set to no-processing, but the
horizontal fine scaling VPD can be activated. Upscaling
(oversampling, zooming), free of frequency folding, up to
factor 3.5 can be achieved, as required by some software
data slicing algorithms.

These raw samples are transported through the image
port as valid data and can be output as Y only format.
The lines are framed by SAV and EAV codes.

8.3.1

CQUISITION CONTROL AND TASK HANDLING

(

SUBADDRESSES

80H, 90H, 94H

9FH

AND

C4H

CFH)

The acquisition control receives horizontal and vertical
synchronization signals from the decoder section or from
the X-port. The acquisition window is generated via pixel
and line counters at the appropriate places in the data
path. From X-port only qualified pixels and lines
(= lines with qualified pixel) are counted.

The acquisition window parameters are:

�

Signal source selection regarding input video stream
and formats from the decoder, or from X-port
(programming bits SCSRC[1:0]91H[5:4] and
FSC[2:0]91H[2:0])

Remark: The input of raw VBI-data from internal
decoder should be controlled via the decoder output
formatter and the LCR registers (see Section 8.2
"Decoder output formatter")

�

Vertical offset defined in lines of the video source,
parameter YO[11:0]99H[3:0]98H[7:0]

�

Vertical length defined in lines of the video source,
parameter YS[11:0]9BH[11:8]9AH[7:0]

�

Vertical length defined in number of target lines, as
result of vertical scaling, parameter
YD[11:0]9FH[11:8]9EH[7:0]

�

Horizontal offset defined in number of pixels of the video
source, parameter XO[11:0]95H[3:0]94H[7:0]

�

Horizontal length defined in number of pixels of the
video source, parameter XS[11:0]97H[3:0]96H[7:0]

�

Horizontal destination size, defined in target pixels after
fine scaling, parameter XD[11:0]9DH[3:0]9CH[7:0].

The source start offset (XO11 to XO0, YO11 to YO0)
opens the acquisition window, and the target size

(XD11 to XD0, YD11 to YD0) closes the window, but the
window is cut vertically, if there are less output lines than
expected. The trigger events for the pixel and line counts
are the horizontal and vertical reference edges as defined
in subaddress 92H.

The task handling is controlled by subaddress 90H (see
Section 8.3.1.2).

8.3.1.1

Input field processing

The trigger event for the field sequence detection from
external signals (X-port) are defined in subaddress 92H.
From the X-port the state of the scalers H-reference signal
at the time of the V-reference edge is taken as field
sequence identifier FID. For example, if the falling edge of
the XRV input signal is the reference and the state of XRH
input is logic 0 at that time, the detected field ID is logic 0.

The bits XFDV[92H[7]] and XFDH[92H[6]] are defining the
detection event and state of the flag from the X-port.
For the default setting of XFDV and XFDH at `00' the state
of the H-input at the falling edge of the V-input is taken.

The scaler directly gets a corresponding field ID
information from the SAA7114H decoder path.

The FID flag is used to determine, whether the first or
second field of a frame is going to be processed within the
scaler and it is used as trigger condition for the task
handling (see bits STRC[1:0]90H[1:0]).

According to ITU 656, FID at logic 0 means first field of a
frame. To ease the application, the polarities of the
detection results on the X-port signals and the internal
decoder ID can be changed via XFDH.

As the V-sync from the decoder path has a half line timing
(due to the interlaced video signal), but the scaler
processing only knows about full lines, during 1st fields
from the decoder the line count of the scaler possibly shifts
by one line, compared to the 2nd field. This can be
compensated by switching the V-trigger event, as defined
by XDV0, to the opposite V-sync edge or by using the
vertical scalers phase offsets. The vertical timing of the
decoder can be seen in Figs 21 and 22.

As the H and V reference events inside the ITU 656 data
stream (from X-port) and the real-time reference signals
from the decoder path are processed differently, the
trigger events for the input acquisition also have to be
programmed differently.

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

Table 8

Processing trigger and start

DESCRIPTION

XDV1

92H[5]

XDV0

92H[4]

XDH

92H[2]

Internal decoder: The processing triggers at the falling edge of the V123 pulse
(see Figs 21 (50 Hz) and 22 (60 Hz)), and starts earliest with the rising edge of the
decoder HREF at line number:

4/7 (50/60 Hz, 1st field), respectively 3/6 (50/60 Hz, 2nd field) (decoder count)

2/5 (50/60 Hz, 1st field), respectively 2/5 (50/60 Hz, 2nd field) (decoder count)

External ITU 656 stream: The processing starts earliest with SAV at line number 23
(50 Hz system), respectively line 20 (60 Hz system) (according ITU 656 count)

8.3.1.2

Task handling

The task handler controls the switching between the two
programming register sets. It is controlled by
subaddresses 90H and C0H. A task is enabled via the
global control bits TEA[80H[4]] and TEB[80H[5]].

The handler is then triggered by events, which can be
defined for each register set.

In case of a programming error the task handling and the
complete scaler can be reset to the initial states by the
software reset bit SWRST[88H[5]] at logic 0.

Especially if the programming registers, related acquisition
window and scale are reprogrammed, while a task is
active, a software reset must be done after programming.

Contrary to the disabling/enabling of a task, which is
evaluated at the end of a running task, SWRST at logic 0
sets the internal state machines directly to their idle states.

The start condition for the handler is defined by bits
STRC[1:0]90H[1:0] and means: start immediately, wait for
next V-sync, next FID at logic 0 or next FID at logic 1. The
FID is evaluated, if the vertical and horizontal offsets are
reached.

With RPTSK[90H[2]] at logic 1 the actual running task is
repeated (under the defined trigger conditions), before
handing control over to the alternate task.

To support field rate reduction, the handler is also enabled
to skip fields (bits FSKP[2:0]90H[5:3]) before executing the
task. A TOGGLE flag is generated (used for the correct
output field processing), which changes state at the
beginning of a task, every time a task is activated.
Examples can be seen in Section 8.3.1.3.

Remarks:

�

To activate a task the start condition must be
fulfilled and the acquisition window offsets must be
reached. For example, in case of `start immediately',
and two regions are defined for one field, the offset of
the lower region must be greater than (offset + length) of
upper region, if not, the actual counted H and V position
at the end of the upper task is beyond the programmed
offsets and the processing will `wait for next V'.

�

Basically the trigger conditions are checked, when a
task is activated. It is important to realize, that they are
not checked, while a task is inactive. So you can not
trigger to next logic 0 or logic 1 with overlapping offset
and active video ranges between the tasks (e.g. task A
STRC[2:0] = 2, YO[11:0] = 310 and task B
STRC[2:0] = 3, YO[11:0] = 310 results in output field
rate of

Hz).

�

After power-on or software reset
(via SWRST[88H[5]]) task B gets priority over
task A.

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

8.3.1.3

Output field processing

As reference for the output field processing, two signals
are available for the back-end hardware.

These signals are the input field ID from the scaler source
and a TOOGLE flag, which shows, that an active task is
used an odd (1, 3, 5...) or even (2, 4, 6...) number of times.
Using a single or both tasks and reducing the field or frame
rate with the task handling functionality, the TOGGLE
information can be used, to reconstruct an interlaced
scaled picture at a reduced frame rate. The TOGGLE flag
isn't synchronized to the input field detection, as it is only
dependent on the interpretation of this information by the
external hardware, whether the output of the scaler is
processed correctly (see Section 8.3.3).

With OFIDC = 0, the scalers input field ID is available as
output field ID on bit D6 of SAV and EAV, respectively on
pin IGP0 (IGP1), if FID output is selected.

When OFIDC[90H[6]] = 1, the TOGGLE information is
available as output field ID on bit D6 of SAV and EAV,
respectively on pin IGP0 (IGP1), if FID output is selected.

Additionally the bit D7 of SAV and EAV can be defined via
CONLH[90H[7]]. CONLH[90H[7]] = 0 (default) sets D7 to
logic 1, a logic 1 inverts the SAV/EAV bit D7. So it's
possible to mark the output of the both tasks by different
SAV/EAV codes. This bit can also be seen as `task flag' on
the pins IGP0 (IGP1), if TASK output is selected.

2000

Mar

Philips Semiconductors

Preliminar

y specification

AL/NTSC/SECAM video decoder with adaptiv

e P
AL/NTSC

comb filter

, VBI-data slicer and high perf

mance scaler

SAA7114H

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Table 9

Examples for field processing

Notes

1. Single task every field; OFIDC = 0; subaddress 90H at 40H; TEB[80H[5]] = 0.

2. Tasks are used to scale to different output windows, priority on task B after SWRST.

3. Both tasks at

frame rate; OFIDC = 0; subaddresses 90H at 43H and C0H at 42H.

4. In examples 3 and 4 the association between input FID and tasks can be flipped, dependent on which time the SWRST is de-asserted.

5. Task B at

frame rate constructed from neighbouring motion phases; task A at

frame rate of equidistant motion phases; OFIDC = 1;

subaddresses 90H at 41H and C0H at 45H.

6. Task A and B at

frame rate of equidistant motion phases; OFIDC = 1; subaddresses 90H at 41H and C0H at 49H.

7. State of prior field.

8. It is assumed that input/output FID = 0 (= upper lines); UP = upper lines; LO = lower lines.

9. O = data output; NO = no output.

SUBJECT

FIELD SEQUENCE FRAME/FIELD

EXAMPLE 1

(1)

EXAMPLE 2

(2)(3)

EXAMPLE 3

(2)(4)(5)

EXAMPLE 4

(2)(4)(6)

1/1

1/2

2/1

1/1

1/2

2/1

2/2

1/1

1/2

2/1

2/2

3/1

3/2

1/1

1/2

2/1

2/2

3/1

3/2

Processed by task

State of detected
ITU 656 FID

TOGGLE flag

(7)

Bit D6 of SAV/EAV byte

(7)

Required sequence
conversion at the vertical
scaler

(8)

Output

(9)

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

8.3.2

ORIZONTAL SCALING

The overall horizontal required scaling factor has to be split
into a binary and a rational value according to the
equation:

where, parameter of prescaler XPSC[5:0] = 1 to 63 and
parameter of VPD phase interpolation
XSCY[12:0] = 300 to 8191 (0 to 299 are only theoretical
values). For example,

3.5

is to split in

�

1.14286. The

binary factor is processed by the prescaler, the arbitrary
non-integer ratios is achieved via the variable phase delay
VPD circuitry, called horizontal fine scaling. Latter
calculates horizontally interpolated new samples with a
6-bit phase accuracy, which relates to less than 1 ns jitter
for regular sampling scheme. Prescaler and fine scaler are
building the horizontal scaler of the SAA7114H.

Using the accumulation length function of the prescaler
(XACL[5:0]A1H[5:0]), application and destination
dependent (e.g. scale for display or for a compression
machine), a compromise between visible bandwidth and
alias suppression can be found.

8.3.2.1

Horizontal prescaler (subaddresses
A0H to A7H and D0H to D7H)

The prescaling function consists of an FIR anti-alias filter
stage and an integer prescaler, which is building an
adaptive prescale dependent low-pass filter, to balance
sharpness and aliasing effects.

The FIR prefilter stage implements different low-pass
characteristics to reduce alias for down-scales in the range
of 1 to

. A CIF optimized filter is build in, which reduces

artefacts for CIF output formats (to be used in combination
with the prescaler set to

scale). See Table 10.

The functionality of the prescaler is defined by:

�

An integer prescaling ratio XPSC[5:0]A0H[5:0]
(= 1 to 63), which covers the integer down-scale
range 1 to

�

An averaging sequence length XACL[5:0]A1H[5:0]
(= 0 to 63); range 1 to 64

�

A DC gain renormalization XDCG[2:0]A2H[2:0];
1 down to

128

�

The bit XC2_1[A2H[3]], which defines the weighting of
the incoming pixels during the averaging process

� XC2_1 = 0

1 + 1...+ 1 +1

� XC2_1 = 1

1 + 2...+ 2 +1

The prescaler builds a prescale dependent FIR low-pass,
with up to (64 + 7) filter taps. The parameter XACL[5:0]
can be used to vary the low-pass characteristic for a given
integer prescale of

XPSC[5:0]

. The user can therewith

decide between signal bandwidth (= sharpness
impression) and alias.

Equation for XPSC[5:0] calculation is:

where,

the range is 1 to 63 (value 0 is not allowed!);

Npix_in = number of input pixel, and

Npix_out = number of desired output pixel over the
complete horizontal scaler.

The use of the prescaler results in a XACL[5:0] and
XC2_1 dependent gain amplification. The amplification
can be calculated according to the equation:

DC gain = ((XACL

XC2_1) + 1)

�

(XC2_1 + 1)

It is recommended to use sequence lengths and weights,
which results in a 2

DC gain amplification, as these

amplitudes can be renormalized by the XDCG[2:0]

controlled

shifter of the prescaler.

The renormalization range of XDCG[2:0] is 1,

... down to

128

Other amplifications have to be normalized by using the
following BCS control circuitry. In these cases the
prescaler has to be set to an overall gain

1, e.g. for an

accumulation sequence of `1 + 1 + 1' (XACL[5:0] = 2 and
XC2_1 = 0), XDCG[2:0] must be set to `010', equals

and the BCS has to amplify the signal to

(SATN[7:0] and CONT[7:0] value = lower integer of

�

64).

The use of XACL[5:0] is XPSC[5:0] dependent.
XACL[5:0] must be

�

XPSC[5:0].

XACL[5:0] can be used to find a compromise between
bandwidth (= sharpness) and alias effects.

H-scale ratio

output pixel

input pixel

------------------------------

H-scale ratio

XPSC[5:0]

----------------------------

1024

XSCY[12:0]

-------------------------------

�

XPSC[5:0]

lower integer of

Npix_in

Npix_out

-----------------------

------

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

Remark: Due to bandwidth considerations XPSC[5:0] and
XACL[5:0] can be chosen different to the previous
mentioned equations or Table 11, as the H-phase scaling
is able to scale in the range from zooming up by factor 3 to
down-scale by a factor of

1024

8191

Figs 26 and 27 show some resulting frequency
characteristics of the prescaler.

Table 11 shows the recommended prescaler
programming. Other programmings, than documented in
Table 11, may result in better alias suppression, but the
resulting DC gain amplification needs to be compensated
by the BCS control, according to the equation:

Where:

XDCG[2:0]

DC gain

DC gain = (XC2_1 + 1)

�

XACL[5:0] + (1

XC2_1).

For example, if XACL[5:0] = 5, XC2_1 = 1, then
DC gain = 10 and the required XDCG[2:0] = 4.

The horizontal source acquisition timing and the
prescaling ratio is identical for both luminance path and
chrominance path, but the FIR filter settings can be
defined differently in the two channels.

Fade-in and fade-out of the filters is achieved by copying
an original source sample each as first and last pixel after
prescaling.

Figs 24 and 25 show the frequency characteristics of the
selectable FIR filters.

CONT[7:0]

SATN[7:0]

lower integer of

XDG[2:0]

DC gain

�

----------------------------------

Table 10 FIR prefilter functions

PFUV[1:0]A2H[7:6]

PFY[1:0]A2H[5:4]

LUMINANCE FILTER COEFFICIENTS

CHROMINANCE COEFFICIENTS

bypassed

1 2 1

1 1 1.75 4.5 1.75 1

3 8 10 8 3

1 2 2 2 1

handbook, full pagewidth

MHB543

(dB)

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

f_sig/f_clock

(1)

(2)

(3)

Fig.24 Luminance prefilter characteristic.

(1) PFY[1:0] = 01.

(2) PFY[1:0] = 10.

(3) PFY[1:0] = 11.

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

Table 11 XACL[5:0] usage example

Note

1. Resulting FIR function.

PRESCALE

RATIO

XPS

[5:0]

RECOMMENDED VALUES

FIR

PREFILTER

PFY[1:0]/

PFUV[1:0]

FOR LOWER BANDWIDTH

REQUIREMENTS

FOR HIGHER BANDWIDTH

REQUIREMENTS

XACL[5:0]

XC2_1

XDCG[2:0]

XACL[5:0]

XC2_1

XDCG[2:0]

0 to 2

(1 2 1)

�

(1)

(1 1)

�

(1)

(1 2 2 2 1)

�

(1)

(1 1 1 1)

�

(1)

(1 2 2 2 2 2 2 2 1)

�

(1)

(1 2 2 2 1)

�

(1)

(1 2 2 2 2 2 2 2 1)

�

(1)

(1 1 1 1 1 1 1 1)

�

(1)

(1 2 2 2 2 2 2 2 1)

�

(1)

(1 1 1 1 1 1 1 1)

�

(1)

(1 2 2 2 2 2 2 2 1)

�

(1)

(1 1 1 1 1 1 1 1)

�

(1)

(1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1)

�

(1)

(1 2 2 2 2 2 2 2 1)

�

(1)

(1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1)

�

(1)

(1 2 2 2 2 2 2 2 1)

�

(1)

(1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1)

�

(1)

(1 2 2 2 2 2 2 2 1)

�

(1)

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

8.3.2.2

Horizontal fine scaling (variable phase delay
filter; subaddresses A8H to AFH and
D8H to DFH)

The horizontal fine scaling (VPD) should operate at scaling
ratios between

and 2 (0.8 and 1.6), but can also be

used for direct scale in the range from

7.999

to (theoretical)

zoom 3.5 (restriction due to the internal data path
architecture), without prescaler.

In combination with the prescaler a compromise between
sharpness impression and alias can be found, which is
signal source and application dependent.

For the luminance channel a filter structure with 10 taps is
implemented, for the chrominance a filter with 4 taps.

Luminance and chrominance scale increments
(XSCY[12:0]A9H[4:0]A8H[7:0] and
XSCC[12:0]ADH[4:0]ACH[7:0]) are defined
independently, but must be set in a 2 : 1 relation in the
actual data path implementation. The phase offsets
XPHY[7:0]AAH[7:0] and XPHC[7:0]AEH[7:0] can be used
to shift the sample phases slightly. XPHY[7:0] and
XPHC[7:0] covers the phase offset range 7.999T to

The phase offsets should also be programmed in a 2 : 1
ratio.

The underlying phase controlling DTO has a 13-bit
resolution.

According to the equations

and

the VPD covers the scale

range from 0.125 to zoom 3.5. VPD acts equivalent to a
polyphase filter with 64 possible phases. In combination
with the prescaler, it is possible to get very accurate
samples from a highly anti-aliased integer down-scaled
input picture.

8.3.3

ERTICAL SCALING

The vertical scaler of the SAA7114H consists of a line
FIFO buffer for line repetition and the vertical scaler block,
which implements the vertical scaling on the input data
stream in 2 different operational modes from theoretical
zoom by 64 down to icon size

. The vertical scaler is

located between the BCS and horizontal fine scaler, so
that the BCS can be used to compensate the DC gain
amplification of the ACM mode (see Section 8.3.3.2) as
the internal RAMs are only 8-bit wide.

8.3.3.1

Line FIFO buffer (subaddresses 91H, B4H and
C1H, E4H)

The line FIFO buffer is a dual ported RAM structure for
768 pixels, with asynchronous write and read access. The
line buffer can be used for various functions, but not all
functions may be available simultaneously.

The line buffer can buffer a complete unscaled active video
line or more than one shorter lines (only for non-mirror
mode), for selective repetition for vertical zoom-up.

For zooming up 240 lines to 288 lines e.g., every fourth
line is requested (read) twice from the vertical scaling
circuitry for calculation.

For conversion of a 4 : 2 : 0 or 4 : 1 : 0 input sampling
scheme (MPEG, video phone, video YUV-9) to CCIR like
sampling scheme 4 : 2 : 2, the chrominance line buffer is
read twice of four times, before being refilled again by the
source. By means of the input acquisition window
definition it has to be preserved, that the processing starts
with a line containing luminance and chrominance
information for 4 : 2 : 0 and 4 : 1 : 0 input. The bits
FSC[2:1]91H[2:1] are defining the distance between the
Y/C lines. In case of 4 : 2 : 2 and 4 : 1 : 1 FSC2 to FSC1
have to be set to `00'.

The line buffer can also be used for mirroring, i.e. for
flipping the image left to right, for the vanity picture in video
phone application (bit YMIR[B4H[4]]). In mirror mode only
one active prescaled line can be held in the FIFO at a time.

The line buffer can be utilized as excessive pipeline buffer
for discontinuous and variable rate transfer conditions at
expansion port or image port.

XSCY[12:0]

1024

Npix_in

XPSC

--------------------

�

Npix_out

-----------------------

�

XSCC[12:0]

XSCY[12:0]

-------------------------------

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

8.3.3.2

Vertical scaler (subaddresses B0H to BFH and
E0H to EFH)

Vertical scaling of any ratio from 64 (theoretical zoom) to

(icon) can be applied.

The vertical scaling block consists of another line delay,
and the vertical filter structure, that can operate in two
different modes. Called linear interpolation (LPI) and
accumulation (ACM) mode, controlled by
YMODE[B4H[0]].

�

LPI mode: In Linear Phase Interpolation (LPI) mode
(YMODE = 0) two neighbouring lines of the source video
stream are added together, but weighted by factors
corresponding to the vertical position (phase) of the
target output line relative to the source lines. This linear
interpolation has a 6-bit phase resolution, which equals
64 intra line phases. It interpolates between two
consecutive input lines only. LPI mode should be
applied for scaling ratios around 1 (down to

), it must

be applied for vertical zooming.

�

ACM mode: The vertical Accumulation (ACM) mode
(YMODE = 1) represents a vertical averaging window
over multiple lines, sliding over the field. This mode also
generates phase correct output lines. The averaging
window length corresponds to the scaling ration,
resulting in an adaptive vertical low-pass effect, to
greatly reduce aliasing artefacts. ACM can be applied
for down-scales only from ratio 1 down to

. ACM

results in a scale dependent DC gain amplification,
which has to be precorrected by the BCS control of the
scaler part.

The phase and scale controlling DTO calculates in 16-bit
resolution, controlled by parameters
YSCY[15:0]B1H[7:0]B0H[7:0] and
YSCC[15:0]B3H[7:0]B2H[7:0], continuously over the
entire filed. A start offset can be applied to the phase
processing by means of the parameters
YPY3[7:0] to YPY0[7:0] in BFH[7:0] to BCH[7:0] and
YPC3[7:0] to YPC0[7:0] in BBH[7:0] to B8H[7:0]. The start
phase covers the range of

255

lines offset.

By programming appropriate, opposite, vertical start
phase values (subaddresses B8H to BFH and
E8H to EFH) depending on odd/even field ID of the source
video stream and A/B-page cycle, frame ID conversion

and field rate conversion are supported (i.e. de-interlacing,
re-interlacing).

Figs 28 and 29 and Tables 12 and 13 are describing the
use of the offsets.

Remark: The vertical start phase, as well as scaling
ratio are defined independently for luminance and
chrominance channel, but must be set to the same
values in the actual implementation for accurate
4 : 2 : 2 output processing.

The vertical processing communicates on it's input side
with the line FIFO buffer. The scale related equations are:

�

Scaling increment calculation for ACM and LPI mode,
down-scale and zoom:

�

BCS value to compensate DC gain in ACM mode
(contrast and saturation have to be set):
CONT[7:0]A5H[7:0] respectively SATN[7:0]A6H[7:0]

, or

8.3.3.3

Use of the vertical phase offsets

As shown in Section 8.3.1.3, the scaler processing may
run randomly over the interlaced input sequence.
Additionally the interpretation and timing between ITU 656
field ID and real-time detection by means of the state of
H-sync at falling edge of V-sync may result in different field
ID interpretation.

Also a vertically scaled interlaced output gets a larger
vertical sampling phase error, if the interlaced input fields
are processed, without regarding the actual scale at the
starting point of operation (see Fig.28).

Four events are to be considered, they are illustrated in
Fig.29.

YSCY(C)[15:0]

lower integer of 1024

Nline_in

Nline_out

-------------------------

�

lower integer of

Nline_out

Nline_in

-------------------------

�

lower integer of

1024

YSCY[15:0]

-------------------------------

�

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

In Tables 12 and 13 PHO is a usable common phase
offset.

Please notice that the equations of Fig.29 are producing
an interpolated output also for the unscaled case, as the
geometrical reference position for all conversions is the
position of the first line of the lower field (see Table 12).

If there is no need for UP-LO and LO-UP conversion and
the input field ID is the reference for the back-end
operation, then it is UP-LO = UP-UP and LO-UP = LO-LO
and the

line phase shift (PHO + 16) can be skipped.

This case is listed in Table 13.

The SAA7114H supports 4 phase offset registers per task
and component (luminance and chrominance). The value
of 20H represents a phase shift of one line.

The registers are assigned to the following events;
e.g. subaddresses B8H to BBH:

�

B8H: 00 = input field ID 0, task status bit 0 (toggle
status, see Section 8.3.1.3)

�

B9H: 01 = input field ID 0, task status bit 1

�

BAH: 10 = input field ID 1, task status bit 0

�

BBH: 11 = input field ID 1, task status bit 1.

Dependent on the input signal (interlaced or
non-interlaced) and the task processing (50 Hz or field
reduced processing with one or two tasks, see examples
in Section 8.3.1.3), also other combinations may be
possible, but the basic equations are the same.

Table 12 Examples for vertical phase offset usage: global equations

INPUT FIELD UNDER

PROCESSING

OUTPUT FIELD

INTERPRETED AS

USED ABBREVIATION

EQUATION FOR PHASE OFFSET

CALCULATION (DECIMAL VALUES)

Upper input lines

upper output lines

UP-UP

PHO + 16

Upper input lines

lower output lines

UP-LO

Lower input lines

upper output lines

LO-UP

PHO

Lower input lines

Lower output lines

LO-LO

PHO

YSCY[15:0]

-------------------------------

PHO

YSCY[15:0]

-------------------------------

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

Table 13 Vertical phase offset usage; assignment of the phase offsets

Notes

1. Case 1: OFIDC[90H[6]] = 0; scaler input field ID as output ID; back-end interprets output field ID at logic 0 as upper

output lines.

2. Case 2: OFIDC[90H[6]] = 1; task status bit as output ID; back-end interprets output field ID at logic 0 as upper output

lines.

3. Case 3: OFIDC[90H[6]] = 1; task status bit as output ID; back-end interprets output field ID at logic 1 as upper output

lines.

DETECTED INPUT

FIELD ID

TASK STATUS BIT

VERTICAL PHASE

OFFSET

CASE

EQUATION TO BE USED

0 = upper lines

YPY(C)0[7:0]

case 1

(1)

UP-UP (PHO)

case 2

(2)

UP-UP

case 3

(3)

UP-LO

0 = upper lines

YPY(C)1[7:0]

case 1

UP-UP (PHO)

case 2

UP-LO

case 3

UP-UP

1 = lower lines

YPY(C)2[7:0]

case 1

LO-LO

case 2

LO-UP

case 3

LO-LO

1 = lower lines

YPY(C)3[7:0]

case 1

LO-LO

case 2

LO-LO

case 3

LO-UP

PHO

YSCY[15:0]

-------------------------------

�

PHO

YSCY[15:0]

-------------------------------

�

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

8.4

VBI-data decoder and capture
(subaddresses 40H to 7FH)

The SAA7114H contains a versatile VBI-data decoder.

The implementation and programming model accords to
the VBI-data slicer built in the multimedia video data
acquisition circuit SAA5284.

The circuitry recovers the actual clock phase during the
clock run-in period, slices the data bits with the selected
data rate, and groups them to bytes. The result is buffered
into a dedicated VBI-data FIFO with a capacity of
2

�

56 bytes (2

�

14 Dwords). The clock frequency,

signals source, field frequency, accepted error count must
be defined in subaddress 40H.

The supported VBI-data standards are shown in Table 14.

For lines 2 to 24 of a field, per VBI line, 1 of 16 standards
can be selected (LCR24_[7:0] to LCR2_[7:0] in
57H[7:0] to 41H[7:0]: 23

�

4 bit programming bits).

The definition for line 24 is valid for the rest of the
corresponding field, normally no text data (= video data)
should be selected there (LCR24_[7:0] = FFH) to stop the
activity of the VBI-data slicer during active video.

To adjust the slicers processing to the input signal source,
there are offsets in horizontal and vertical direction
available: parameters HOFF[10:0]5BH[2:0]59H[7:0],
VOFF[8:0]5BH[4]5AH[7:0] and FOFF[5BH[7]]).

Contrary to the scalers counting, the slicers offsets are
defining the position of the H and V trigger events related
to the processed video field. The trigger events are the
falling edge of HREF and the falling edge of V123 from the
decoder processing part.

The relation of these programming values to the input
signal and the recommended values can be seen in
Tables 4 to 7.

Table 14 Data types supported by the data slicer block

DT[3:0]

62H[3:0]

STANDARD TYPE

DATA RATE

(Mbits/s)

FRAMING CODE

WINDOW

HAM

CHECK

0000

teletext EuroWST, CCST

6.9375

27H

WST625

always

0001

European closed caption

0.500

001

CC625

0010

VPS

9951H

VPS

0011

wide screen signalling bits

1E3C1FH

WSS

0100

US teletext (WST)

5.7272

27H

WST525

always

0101

US closed caption (line 21)

0.503

001

CC525

0110

(video data selected)

none

disable

0111

(raw data selected)

none

disable

1000

teletext

6.9375

programmable

general text

optional

1001

VITC/EBU time codes (Europe)

1.8125

programmable

VITC625

1010

VITC/SMPTE time codes (USA)

1.7898

programmable

VITC625

1011

reserved

1100

US NABTS

5.7272

programmable

NABTS

optional

1101

MOJI (Japanese)

5.7272

programmable (A7H) Japtext

1110

Japanese format switch (L20/22)

programmable

open

1111

no sliced data transmitted
(video data selected)

none

disable

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

8.5

Image port output formatter
(subaddresses 84H to 87H)

The output interface consists of a FIFO for video and for
sliced text data, an arbitration circuit, which controls the
mixed transfer of video and sliced text data over the I-port
and a decoding and multiplexing unit, which generates the
8 or 16-bit wide output data stream and the accompanied
reference and supporting information.

The clock for the output interface can be derived from an
internal clock, decoder, expansion port, or an externally
provided clock which is appropriate for e.g. VGA and frame
buffer. The clock can be up to 33 MHz. The scaler provides
the following video related timing reference events
(signals), which are available on pins as defined by
subaddresses 84H and 85H:

�

Output field ID

�

Start and end of vertical active video range,

�

Start and end of active video line

�

Data qualifier or gated clock

�

Actually activated programming page (if CONLH is
used)

�

Threshold controlled FIFO filling flags (empty, full, filled)

�

Sliced data marker.

The disconnected data stream at the scaler output is
accompanied by a data valid flag (or data qualifier), or is
transported via a gated clock. Clock cycles with invalid
data on the I-port data bus (including the HPD pins in
16-bit output mode) are marked with code 00H.

The output interface also arbitrates the transfer between
scaled video data and sliced text data over the I-port
output.

The bits VITX1 and VITX0 (subaddress 86H) are used to
control the arbitration.

As further operation the serialization of the internal 32-bit
Dwords to 8-bit or optional 16-bit output, as well as the
insertion of the extended ITU 656 codes (SAV/EAV for
video data, ANC or SAV/EAV codes for sliced text data)
are done here.

For handshake with the VGA controller, or other memory
or bus interface circuitry, programmable FIFO flags are
provided (see Section 8.5.2).

8.5.1

CALER OUTPUT FORMATTER

(

SUBADDRESSES

93H

AND

C3H)

The output formatter organizes the packing into the output
FIFO. The following formats are available: YUV 4 : 2 : 2,
YUV 4 : 1 : 1, YUV 4 : 2 : 0, YUV 4 : 1 : 0, Y only (e.g. for
raw samples). The formatting is controlled by
FSI[2:0]93H[2:0], FOI[1:0]93H[4:3] and FYSK[93H[5]].

The data formats are defined on Dwords, or multiples, and
are similar to the video formats as recommended for PCI
multimedia applications (compare SAA7146A), but planar
formats are not supported.

FSI[2:0] defines the horizontal packing of the data,
FOI[1:0] defines, how many Y only lines are expected,
before a Y/C line will be formatted. If FYSK is set to logic 0
preceding Y only lines will be skipped, and output will
always start with a Y/C line.

Additionally the output formatter limits the amplitude range
of the video data (controlled by ILLV[85H[5]]); see
Table 17.

Table 15 Byte stream for different output formats

Table 16 Explanation to Table 15

OUTPUT FORMAT

BYTE SEQUENCE FOR 8-BIT OUTPUT MODES

YUV 4 : 2 : 2

YUV 4 : 1 : 1

Y only

Y10

Y11

Y12

Y13

NAME

EXPLANATION

U (B

Y) colour difference component, pixel number n = 0, 2, 4 to 718

Y (luminance) component, pixel number n = 0, 1, 2, 3 to 719

V (R

Y) colour difference component, pixel number n = 0, 2, 4 to 718

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

Table 17 Limiting range on I-port

LIMIT STEP

ILLV[85H[5]]

VALID RANGE

SUPPRESSED CODES (HEXADECIMAL VALUE)

DECIMAL VALUE

HEXADECIMAL VALUE

LOWER RANGE

UPPER RANGE

1 to 254

01 to FE

8 to 247

08 to F7

00 to 07

F8 to FF

8.5.2

IDEO

FIFO (

SUBADDRESS

86H)

The video FIFO at the scaler output contains 32 Dwords.
That corresponds to 64 pixels in 16-bit YUV 4 : 2 : 2
format. But as the entire scaler can act as pipeline buffer,
the actually available buffer capacity for the image port is
much higher, and can exceed beyond a video line.

The image port, and the video FIFO, can operate with the
video source clock (synchronous mode) or with externally
provided clock (asynchronous, and burst mode), as
appropriate for the VGA controller or attached frame
buffer.

The video FIFO provides 4 internal flags, reporting to
which extent the FIFO is actually filled. These are:

�

The FIFO Almost Empty (FAE) flag

�

The FIFO Combined Flag (FCF) or FIFO filled, which is
set at almost full level and reset, with hysteresis, only
after the level crosses below the almost empty mark

�

The FIFO Almost Full (FAF) flag

�

The FIFO Overflow (FOVL) flag.

The trigger levels for FAE and FAF are programmable by
FFL[1:0]86H[3:2] (16, 24, 28, full) and FEL[1:0]86H[1:0]
(16, 8, 4, empty).

The state of this flag can be seen on the
pins IGP0 or IGP1. The pin mapping is defined by
subaddresses 84H and 85H (see Section 9.5).

8.5.3

EXT

FIFO

In the text FIFO the data of the terminal VBI-data slicer are
collected before the transmission over the I-port is
requested (normally before the video window starts). It is
partitioned into two FIFO sections. A complete line is filled
into the FIFO, before a data transfer is requested. So
normally, one line text data is ready for transfer, while the
next text line is collected. So sliced text data are delivered
as a block of qualified data, without any qualification gaps
in the byte stream of the I-port.

The decoded VBI-data is collected in the dedicated
VBI-data FIFO. After capture of a line is completed, the
FIFO can be streamed through the image port, preceded
by a header, telling line number and standard.

The VBI-data period can be signalled via the sliced data
flag on pin IGP0 or IGP1. The decoded VBI-data is lead by
the ITU ancillary data header (DID[5:0]5DH[5:0] at value
<3EH) or by SAV/EAV codes selectable by DID[5:0] at
value 3EH or 3FH. IGP0 or IGP1 is set, if the first byte of
the ANC header is valid on the I-port bus. It is reset, if an
SAV occurs. So it may frame multiple lines of text data
output, in case video processing starts with a distance of
several video lines to the region of text data. Valid sliced
data from the text FIFO are available on the I-port as long
as the IGP0 or IGP1 flag is set and the data qualifier is
active on pin IDQ.

The decoded VBI-data are presented in two different data
formats, controlled by bit RECODE.

�

RECODE = 1: values 00H and FFH will be recoded to
even parity values 03H and FCH

�

RECODE = 0: values 00H and FFH may occur in the
data stream as detected.

8.5.4

IDEO AND TEXT ARBITRATION

(

SUBADDRESS

86H)

Sliced text data and scaled video data are transferred over
the same bus, the I-port. The mixed transfer is controlled
by an arbitration circuitry. If the video data are transferred
without any interrupt and the video FIFO does not need to
buffer any output pixel, the text data are inserted after an
end of a scaled video line, normally during the blanking
interval of the video.

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

8.5.5

ATA STREAM CODING AND REFERENCE SIGNAL

GENERATION

(

SUBADDRESSES

84H, 85H

AND

93H)

As H and V reference signals are logic 1, active gate
signals are generated, which are framing the transfer of
the valid output data. Alternative to the gates, H and V
trigger pulses are generated on the rising edges of the
gates.

Due to the dynamic FIFO behaviour of the complete scaler
path, the output signal timing has no fixed timing relation
to the real-time input video stream. So fixed propagation
delays, in therms of clock cycles, related to the analog
input can not be defined.

The data stream is accompanied by a data qualifier.
Additionally invalid data cycles are marked with code 00H.

If ITU 656 like codes are not wanted, these codes can be
suppressed in the output stream.

As further option, it is possible to provide the scaler with a
gating external signal on pin ITRDY. So it is possible to
hold the data output for a certain time and to get valid
output data in bursts of a guaranteed length.

The sketched reference signals and events can be
mapped to the I-port output pins IDQ, IGPH, IGPV,
IGP0 and IGP1. For flexible use the polarities of all the
outputs can be modified. The default polarity for the
qualifier and reference signals is logic 1 (= active).

Table 18 shows the relevant and supported SAV and EAV
coding.

Table 18 SAV/EAV codes on I-port

Notes

1. The leading byte sequence is: FFH-00H-00H.

2. The MSB of the SAV/EAV code byte is controlled by:

a) Scaler output data: task A

MSB = CONLH (90H[7]); task B

MSB = CONLH (C0H[7]).

b) VBI-data slicer output data: DID[5:0]5DH[5:0] = 3EH

MSB = 1; DID[5:0]5DH[5:0] = 3FH

MSB = 0.

EVENT DESCRIPTION

SAV/EAV CODES ON I-PORT

(1)

(HEX)

COMMENT

MSB

(2)

OF SAV/EAV BYTE = 0 MSB

(2)

OF SAV/EAV BYTE = 1

FIELD ID = 0

FIELD ID = 1

FIELD ID = 0

FIELD ID = 1

Next pixel is FIRST pixel of any
active line

HREF = active;
VREF = active

Previous pixel was LAST pixel
of any active line, but not the
last

HREF = inactive;
VREF = active

Next pixel is FIRST pixel of any
V-blanking line

HREF = active;
VREF = inactive

Previous pixel was LAST pixel
of the last active line or of any
V-blanking line

HREF = inactive;
VREF = inactive

No valid data, don't capture
and don't increment pointer

IDQ pin inactive

2000

Mar

Philips Semiconductors

Preliminar

y specification

AL/NTSC/SECAM video decoder with adaptiv

e P
AL/NTSC

comb filter

, VBI-data slicer and high perf

mance scaler

SAA7114H

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Table 19 Explanation to Fig.30

Notes

1. Inverted EP (bit 7); for EP see note 2.

2. Even parity (bit 6) of bits 5 to 0.

3. Odd parity (bit 7) of bits 6 to 0.

NAME

EXPLANATION

SAV

start of active data; see Table 20

SDID

sliced data identification: NEP

(1)

, EP

(2)

, SDID5 to SDID0, freely programmable via I

C-bus subaddress 5EH, D5 to D0, e. g. to be used as

source identifier

Dword count: NEP

(1)

, EP

(2)

, DC5 to DC0. DC describes the number of succeeding 32-bit words:

�

For SAV/EAV mode DC is fixed to 11 Dwords (byte value 4BH)

�

For ANC mode it is: DC =

(C + n), where C = 2 (the two data identification bytes IDI1 and IDI2) and n = number of decoded bytes

according to the chosen text standard.

Note that the number of valid bytes inside the stream can be seen in the BC byte.

IDI1

internal data identification 1: OP

(3)

, FID (field 1 = 0, field 2 = 1), LineNumber8 to LineNumber3 = Dword 1 byte 1; see Table 20

IDI2

internal data identification 2: OP

(3)

, LineNumber2 to LineNumber0, DataType3 to DataType0 = Dword 1 byte 2; see Table 20

n_m

Dword number n, byte number m

DC_4

last Dword byte 4, note: for SAV/EAV framing DC is fixed to 0BH, missing data bytes are filled up; the fill value is A0H

the check sum byte, the checksum is accumulated from the SAV (respectively DID) byte to the D

DC_4

byte

number of valid sliced bytes counted from the IDI1 byte

EAV

end of active data; see Table 20

MHB549

SAV SDID DC

IDI1

IDI2 D

1_3

1_4

2_1

DC_3

DC_4

EAV

...

1_2

1_1

...

EAV

DID SDID DC

IDI1

IDI2 D

1_3

1_4

DC_3

DC_4

...

ANC header

internal header

sliced data

ANC data output is only filled up
to the Dword boundary

timing reference code

invalid data

end of raw VBI line

timing reference code

internal header

sliced data

invalid data

and filling data

Fig.30 Sliced data formats on the I-port in 8-bit mode.

ANC header active for DID (subaddress 5DH) <3EH

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

Table 20 Bytes stream of the data slicer

Notes

1. NEP = inverted EP (see note 2).

2. EP = Even Parity of bits 5 to 0.

3. FID = 0: field 1; FID = 1: field 2.

4. I1 = 0 and I0 = 0: before line 1; I1 = 0 and I0 = 1: lines 1 to 23; I1 = 1 and I0 = 0: after line 23; I1 = 1 and I0 = 1:

line 24 to end of field.

5. Subaddress 5DH at 3EH and 3FH are used for ITU 656 like SAV/EAV header generation; recommended value.

6. V = 0: active video; V = 1: blanking.

7. H = 0: start of line; H = 1: end of line.

8. DC = Data Count in Dwords according to the data type.

9. OP = Odd Parity of bits 6 to 0.

10. LN = Line Number.

11. DT = Data Type according to table.

NICK

NAME

COMMENT

DID,
SAV,
EAV

subaddress
5DH = 00H

NEP

(1)

(2)

FID

(3)

(4)

subaddress 5DH;
D5 = 1

NEP

D4[5DH] D3[5DH] D2[5DH] D1[5DH] D0[5DH]

subaddress 5DH
D5 = 3EH; note 5

FID

(3)

(6)

(7)

subaddress 5DH
D5 = 3FH; note 5

FID

(3)

(6)

(7)

SDID

programmable via
subaddress 5EH

NEP

D5[5EH]

D4[5EH]

D3[5EH]

D2[5EH]

D1[5EH]

D0[5EH]

(8)

NEP

(2)

DC5

DC4

DC3

DC2

DC1

DC0

IDI1

(9)

FID

(3)

LN8

(10)

LN7

(10)

LN6

(10)

LN5

(10)

LN4

(10)

LN3

(10)

IDI2

LN2

(10)

LN1

(10)

LN0

(10)

DT3

(11)

DT2

(11)

DT1

(11)

DT0

(11)

check sum byte

CS6

CS5

CS4

CS3

CS2

CS1

CS0

valid byte count

CNT5

CNT4

CNT3

CNT2

CNT1

CNT0

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SAA7114H

8.6

Audio clock generation
(subaddresses 30H to 3FH)

SAA7114H incorporates generation of a field locked audio
clock, as an auxiliary function for video capture. An audio
sample clock, that is locked to the field frequency, makes
sure that there is always the same predefined number of
audio samples associated with a field, or a set of fields.
That ensures synchronous playback of audio and video
after digital recording (e.g. capture to hard disk), MPEG or
other compression, or non-linear editing.

8.6.1

ASTER AUDIO CLOCK

The audio clock is synthesized from the same crystal
frequency as the line-locked video clock is generated.
The master audio clock is defined by the parameters:

�

Audio master Clocks Per Field,
ACPF[17:0]32H[1:0]31H[7:0]30H[7:0] according to the

equation:

�

Audio master Clocks Nominal Increment,
ACNI[21:0]36H[5:0]35H[7:0]34H[7:0] according to the

equation:

See Table 21 for examples.

Remark: For standard applications the synthesized audio
clock AMCLK can be used directly as master clock and as
input clock for port AMXCLK (short cut) to generate
ASCLK and ALRCLK. For high-end applications it is
recommended to use an external analog PLL circuit to
enhance the performance of the generated audio clock.

ACPF[17:0]

round

audio frequency

field frequency

------------------------------------------

ACNI21:0]

round

audio frequency

crystal frequency

---------------------------------------------

�

Table 21 Programming examples for audio master clock generation

XTALO (MHz)

FIELD (Hz)

ACPF

ACNI

DECIMAL

HEX

DECIMAL

HEX

AMCLK = 256

�

48 kHz (12.288 MHz)

32.11

245760

3C000

3210190

30FBCE

59.94

205005

320CD

3210190

30FBCE

24.576

59.94

AMCLK = 256

�

44.1 kHz (11.2896 MHz)

32.11

225792

37200

2949362

2D00F2

59.94

188348

2DFBC

2949362

2D00F2

24.576

225792

37200

3853517

3ACCCD

59.94

188348

2DFBC

3853 517

3ACCCD

AMCLK = 256

�

32 kHz (8.192 MHz)

32.11

163840

28000

2140127

20A7DF

59.94

136670

215DE

2140127

20A7DF

24.576

163840

28000

2796203

2AAAAB

59.94

136670

215DE

2796203

2AAAAB

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SAA7114H

8.6.2

IGNALS

ASCLK

AND

ALRCLK

Two binary divided signals ASCLK and ALRCLK are
provided for slower serial digital audio signal transmission
and for channel-select. The frequencies of these signals
are defined by the parameters:

�

SDIV[5:0]38H[5:0] according to the equation:

�

LRDIV[5:0]39H[5:0] according to the equation:

See Table 22 for examples.

ASCLK

AMXCLK

SDIV

(

)

�

--------------------------------------

SDIV[5:0]

AMXCLK

ASCLK

--------------------

�

ALRCLK

ASCLK

LRDIV

�

---------------------------

LRDIV[5:0]

ASCLK

ALRCLK

-----------------------

Table 22 Programming examples for ASCLK/ALRCLK clock generation

AMXCLK

(MHz)

ASCLK

(kHz)

SDIV

ALRCLK

(kHz)

LRDIV

DECIMAL

HEX

DECIMAL

HEX

12.288

1536

768

11.2896

1411.2

44.1

2822.4

8.192

1024

2048

8.6.3

THER CONTROL SIGNALS

Further control signals are available to define reference
clock edges and vertical references:

APLL[3AH[3]]; Audio PLL mode:

0: PLL closed

1: PLL open

AMVR[3AH[2]]; Audio Master clock Vertical Reference:

0: internal V

1: external V

LRPH[3AH[1]]; ALRCLK Phase

0: invert ASCLK, ALRCLK edges triggered by falling
edge of ASCLK

1: don't invert ASCLK, ALRCLK edges triggered by
rising edge of ASCLK

SCPH[3AH[0]]; ASCLK Phase:

0: invert AMXCLK, ASCLK edges triggered by falling
edge of AMXCLK

1: don't invert AMXCLK, ASCLK edges triggered by
rising edge of AMXCLK

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SAA7114H

INPUT/OUTPUT INTERFACES AND PORTS

The SAA7114H has 5 different I/O interfaces:

�

Analog video input interface, for analog CVBS and/or
Y and C input signals

�

Audio clock port

�

Digital real-time signal port (RT port)

�

Digital video expansion port (X-port), for unscaled digital
video input and output

�

Digital image port (I-port) for scaled video data output
and programming

�

Digital host port (H-port) for extension of the image port
or expansion port from 8 to 16-bit.

9.1

Analog terminals

The SAA7114H has 6 analog inputs AI21 to AI24, AI11
and AI12 for composite video CVBS or S-video Y/C signal
pairs. Additionally, there are two differential reference
inputs, which must be connected to ground via a capacitor
equivalent to the decoupling capacitors at the 6 inputs.
There are no peripheral components required other than
these decoupling capacitors and 18

/56

termination

resistors, one set per connected input signal (see also
application example in Fig.40). Two anti-alias filters are
integrated, and self adjusting via the clock frequency.

Clamp and gain control for the two ADC's are also
integrated. An analog video output pin AOUT is provided
for testing purposes.

Table 23 Analog pin description

SYMBOL

PIN

I/O

DESCRIPTION

BIT

AI24 to AI21

10, 12, 14 and 16

analog video signal inputs, e.g. 2 CVBS signals and
two Y/C pairs can be connected simultaneously

MODE3 to MODE0

AI12 and AI11

18 and 20

AOUT

analog video output, for test purposes

AOSL1 and AOSL0

AI1D and AI2D

19 and 13

analog reference pins for differential ADC operation

9.2

Audio clock signals

The SAA7114H also synchronizes the audio clock and
sampling rate to the video frame rate, via a very slow PLL.
This ensures that the multimedia capture and compression
processes always gather the same predefined number of
samples per video frame.

An audio master clock AMCLK and two divided clocks
ASCLK and ALRCLK are generated;

�

ASCLK: can be used as audio serial clock

�

ALRCLK: audio left/right channel clock.

The ratios are programmable, see also Section 8.6.

Table 24 Audio clock pin description

SYMBOL PIN I/O

DESCRIPTION

BIT

AMCLK

audio master clock output

ACPF[17:0]32H[1:0]31H[7:0]30H[7:0] and
ACNI[21:0]36H[5:0]35H[7:0]34H[7:0]

AMXCLK

external audio master clock input for the clock
division circuit, can be directly connected to output
AMCLK for standard applications

ASCLK

serial audio clock output, can be synchronized to
rising or falling edge of AMXCLK

SDIV[5:0]38H[5:0] and SCPH[3AH[0]]

ALRCLK

audio channel (left/right) clock output, can be
synchronized to rising or falling edge of ASCLK

LRDIV[5:0]39H[5:0] and LRPH[3AH[1]]

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SAA7114H

9.3

Clock and real-time synchronization signals

For the generation of the line-locked video (pixel) clock
LLC, and of the frame locked audio serial bit clock, a
crystal accurate frequency reference is required. An
oscillator is built in, for fundamental or third harmonic
crystals. The supported crystal frequencies are 32.11 or
24.576 MHz (defined during reset by strapping
pin ALRCLK).

Alternatively pin XTALI can be driven from an external
single ended oscillator.

The crystal oscillation can be propagated as clock to other
ICs in the system via pin XOUT.

The Line-Locked Clock (LLC) is the double pixel clock of
nominal 27 MHz. It is locked to the selected video input,
generating baseband video pixels according to

"ITU

recommendation 601". In order to support interfacing
circuitries, a direct pixel clock LLC2 is also provided.

The pins for line and field timing reference signals are
RTCO, RTS1 and RTS0. Various real-time status
information can be selected for the RTS pins. The signals
are always available (output) and reflect the
synchronization operation of the decoder part in the
SAA7114H. The function of the RTS1 and RTS0 pins can
be defined by bits RTSE1[3:0]12H[7:4] and
RTSE0[3:0]12H[3:0].

Table 25 Clock and real-time synchronization signals

SYMBOL PIN I/O

DESCRIPTION

BIT

Crystal oscillator

XTALI

input for crystal oscillator, or reference clock

XTALO

output of crystal oscillator

XOUT

reference (crystal) clock output drive (optional)

XTOUTE[14H[3]]

Real-time signals (RT port)

LLC

line-locked clock, nominal 27 MHz, double pixel clock locked to the
selected video input signal

LLC2

line-locked pixel clock, nominal 13.5 MHz

RTCO

real-time control output, transfers real-time status information
supporting RTC level 3.1 (see external document

"RTC Functional

Description", available on request)

RTS0

real-time status information line 0, can be programmed to carry various
real-time informations (see Table 55)

RTSE0[3:0]12H[3:0]

RTS1

real-time status information line 1, can be programmed to carry various
real-time informations (see Table 56)

RTSE1[3:0]12H[7:4]

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SAA7114H

9.4

Video expansion port (X-port)

The expansion port is intended for transporting video
streams image data from other digital video circuits like
MPEG encoder/decoder and video phone codec, to the
image port (I-port).

The expansion port consists of two groups of signals/pins:

�

8-bit data, I/O, regularly components video
YUV 4 : 2 : 2, i.e. C

-Y-C

-Y, byte serial, exceptionally

raw video samples (e.g. ADC test). In input mode the
data bus can be extended to 16-bit by the pins
HPD7 to HPD0.

�

Clock, synchronization and auxiliary signals,
accompanying the data stream, I/O.

As output, these are direct copies of the decoder signals.

The data transfers through the expansion port represent a
single D1 port, with half duplex mode. The SAV and EAV
codes may be inserted optionally for data input (controlled
by bit XCODE[92H[3]]). The input/output direction is
switched for complete fields, only.

Table 26 Signals dedicated to the expansion port

SYMBOL

PIN

I/O

DESCRIPTION

BIT

XPD7 to
XPD0

81, 82,

84 to 87,

89 and 90

I/O X-port data: in output mode controlled by decoder

section, data format see Table 27; in input mode
YUV 4 : 2 : 2 serial input data or luminance part of
a 16-bit YUV 4 : 2 : 2 input

OFTS[2:0]13H[2:0];
91H[7:0] and C1H[7:0]

XCLK

I/O clock at expansion port: if output, then copy of LLC;

as input normally a double pixel clock of up to
32 MHz or a gated clock (clock gated with a
qualifier)

XCKS[92H[0]]

XDQ

I/O data valid flag of the expansion port input (qualifier):

if output, then decoder (HREF and VGATE) gate
(see Fig.23)

XRDY

data request flag = ready to receive, to work with
optional buffer in external device, to prevent internal
buffer overflow;
second function: input related task flag A/B

XRQT[83H[2]]

XRH

I/O horizontal reference signal for the X-port: as output:

HREF or HS from the decoder (see Fig.23); as
input: a reference edge for horizontal input timing
and a polarity for input field ID detection can be
defined

XRHS[13H[6]], XFDH[92H[6]] and
XDH[92H[2]]

XRV

I/O vertical reference signal for the X-port: as output:

V123 or field ID from the decoder,
see Figs 21 and 22; as input: a reference edge for
vertical input timing and for input field ID detection
can be defined

XRVS[1:0]13H[5:4], XFDV[92H[7]]
and XDV[1:0]92H[5:4]

XTRI

port control: switches X-port input 3-state

XPE[1:0]83H[1:0]

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SAA7114H

9.4.1

X-

PORT CONFIGURED AS OUTPUT

If data output is enabled at the expansion port, then the
data stream from the decoder is presented. The data
format of the 8-bit data bus is dependent on the chosen
data type, selectable by the line control registers
LCR2 to LCR24; see Table 3. In contrast to the image
port, the sliced data format is not available on the
expansion port. Instead, raw CVBS samples are always
transferred if any sliced data type is selected.

Following are some details of data types on the expansion
port:

�

Active video (data type 15) contains component
YUV 4 : 2 : 2 signal, 720 active pixels per line. The
amplitude and offsets are programmable via
DBRI7 to DBRI0, DCON7 to DCON0,
DSAT7 to DSAT0, OFFU1, OFFU0,
OFFV1 and OFFV0. For nominal levels see Fig.17.

�

Test line (data type 6) is similar to active video format,
with some constraints within the data processing:

� adaptive chrominance comb filter, vertical filter

(chrominance comb filter for NTSC standards, PAL
phase error correction) within the chrominance
processing are disabled

� adaptive luminance comb filter, peaking and

chrominance trap are bypassed within the luminance
processing.

This data type is defined for future enhancements. It
could be activated for lines containing standard test
signals within the vertical blanking period. Currently the
most sources do not contain test lines. For nominal
levels see Fig.17.

�

Raw samples (data types 0 to 5 and 7 to 14):
UV-samples are similar to data type 6, but CVBS
samples are transferred instead of processed luminance
samples within the Y time slots.

The amplitude and offset of the CVBS signal is
programmable via RAWG7 to RAWG0 and
RAWO7 to RAWO0; see Chapter 15 "I

C-bus

description", Tables 62 and 63. For nominal levels
see Fig.18.

The relation of LCR programming to line numbers is
described in Section 8.2, see Tables 4 to 7.

The data type selections by LCR are overruled by setting
OFTS2 (subaddress 13H bit 2) = 1. This setting is mainly
intended for device production test. The VPO-bus carries
the upper or lower 8 bits of the two ADCs dependent on
OFTS[1:0]13H[1:0] settings; see Table 57. The output
configuration is done via MODE[3:0]02H[3:0] settings; see
Table 39. If a YC mode is selected, the expansion port
carries the multiplexed output signals of both ADCs, in
CVBS mode the output of only one ADC. No timing
reference codes are generated in this mode.

Remark: The LSBs (bit 0) of the ADCs are also available
on pin RTS0. For details see Table 55.

The SAV/EAV timing reference codes define start and end
of valid data regions. During horizontal blanking period
between EAV and SAV the ITU-blanking code sequence
`- 80 - 10 - 80 - 10 -...' is transmitted.

The position of the F-bit is constant according to ITU 656
(see Tables 29 and 30).

The V-bit can be generated in two different ways (see
Tables 29 and 30) controlled via OFTS1 and OFTS0, see
Table 57.

F and V bits change synchronously with the EAV code.

Table 27 Data format on the expansion port

Notes

1. The generation of the timing reference codes can be suppressed by setting OFTS[2:0] to `010', see Table 57. In this

event the code sequence is replaced by the standard `- 80 - 10 -' blanking values.

2. If raw samples or sliced data are selected by the line control registers (LCR2 to LCR24), the Y-samples are replaced

by CVBS samples.

BLANKING

PERIOD

TIMING

REFERENCE

CODE (HEX)

(1)

720 PIXELS YUV 4 : 2 : 2 DATA

(2)

TIMING

REFERENCE

CODE (HEX)

(1)

BLANKING

PERIOD

...

10 FF 00 00 SAV C

0 Y0 C

0 Y1 C

2 Y2 ... C

718 Y719 FF 00 00 EAV

...

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comb filter, VBI-data slicer and high performance scaler

SAA7114H

Table 28 SAV/EAV format on expansion port XPD7 to XPD0

Table 29 525 lines/60 Hz vertical timing

Table 30 625 lines/50 Hz vertical timing

BIT 7

BIT 6

(F)

BIT 5

(V)

BIT 4

(H)

BIT 3

(P3)

BIT 2

(P2)

BIT 1

(P1)

BIT 0

(P0)

field bit

vertical blanking bit

format

reserved; evaluation not
recommended (protection
bits according to ITU 656)

1st field: F = 0

2nd field: F = 1

VBI: V = 1

active video: V = 0

H = 0 in SAV format

H = 1 in EAV format

for vertical timing see Tables 29 and 30

LINE NUMBER

F (ITU 656)

OFTS[2:0] = 000 (ITU 656)

OFTS[2:0] = 001

1 to 3

according to selected VGATE
position type via
VSTA and VSTO
(subaddresses 15H to 17H);
see Tables 59 to 61

4 to 19

22 to 261

262

263

264 and 265

266 to 282

283

284

285 to 524

525

LINE NUMBER

F (ITU 656)

OFTS[2:0] = 000 (ITU 656)

OFTS[1:0] = 10

1 to 22

according to selected VGATE
position type via
VSTA and VSTO
(subaddresses 15H to 17H);
see Tables 59 to 61

24 to 309

310

311 and 312

313 to 335

336

337 to 622

623

624 and 625

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SAA7114H

9.4.2

X-

PORT CONFIGURED AS INPUT

If data input mode is selected at the expansion port, then
the scaler can choose it's input data stream from the
on-chip video decoder, or from expansion port (controlled
by bit SCSRC[1:0]91H[5:4]). Byte serial YUV 4 : 2 : 2, or
subsets for other sampling schemes, or raw samples from
an external ADC may be input (see also bits
FSC[2:0]91H[2:0]). The input stream must be
accompanied by an external clock XCLK, qualifier XDQ
and reference signals XRH and XRV. Instead of the
reference signal, embedded SAV and EAV codes
according to ITU 656 are also accepted. The protection
bits are not evaluated.

XRH and XRV carry the horizontal and vertical
synchronization signals for the digital video stream
through the expansion port. The field ID of the input video
stream is carried in the phase (edge) of XRV and state of
XRH, or directly as FS (frame sync, odd/even signal) on
the XRV pin (controlled by XFDV[92H[7]],
XFDH[92H[6]] and XDV1[92H[5]]).

The trigger events on XRH (rising/falling edge) and XRV
(rising/falling/both edges) for the scalers acquisition
window are defined by XDV[1:0]92H[5:4] and
XDH[92H[2]]. Also the signal polarity of the qualifier can be
defined (bit XDQ[92H[1]]). Alternatively to a qualifier, the
input clock can be applied to a gated clock (means clock
gated with a data qualifier, controlled by bit
XCKS[92H[0]]). In this event, all input data will be qualified.

9.5

Image port (I-port)

The image port transfers data from the scaler as well as
from the VBI-data slicer, if so selected (maximum
33 MHz). The reference clock is available at the ICLK pin,
as output, or as input (maximum 33 MHz). As output, ICLK
is derived from the locked decoder or expansion port input
clock. The data stream from the scaler output is normally
discontinuous. Therefore valid data during a clock cycle is
accompanied by a data qualifying (data valid) flag on
pin IDQ. For pin constrained applications the IDQ pin can
be programmed to function as gated clock output (bit
ICKS2[80H[2]]).

The data formats at the image port are defined in Dwords
of 32 bits (4 bytes), like the related FIFO structures. But
the physical data stream at the image port is only 16-bit or
8-bit wide; in 16-bit mode data pins HPD7 to HPD0 are
used for chrominance data. The four bytes of the Dwords
are serialized in words or bytes.

Available formats are:

�

YUV 4 : 2 : 2,

�

YUV 4 : 1 : 1,

�

Raw samples

�

Decoded VBI-data.

For handshake with the receiving VGA controller, or other
memory or bus interface circuitry, F, H and V reference
signals and programmable FIFO flags are provided. The
information will be provided on pins IGP0, IGP1, IGPH and
IGPV. The functionality on this pins is controlled via
subaddresses 84H and 85H.

VBI-data is collected over an entire line in its own FIFO,
and transferred as an uninterrupted block of bytes.
Decoded VBI-data can be signed by the VBI flag on
pin IGP0/1.

As scaled video data and decoded VBI-data may come
from different and asynchronous sources, an arbitration
scheme is needed. Normally VBI-data slicer has priority.

The image port consists of the pins and/or signals, as
listed in Table 31.

For pin constrained applications, or interfaces, the relevant
timing and data reference signals can also get encoded
into the data stream. Therefore the corresponding pins do
not need to get connected. The minimum image port
configuration requires 9 pins only, i.e. 8 pins for data
including codes, and 1 pin for clock or gated clock. The
inserted codes are defined in close relation to the
ITU/CCIR-656 (D1) recommendation, where possible.

The following deviations from

"ITU 656 recommendation"

are implemented at SAA7114H's image port interface:

�

SAV and EAV codes are only present in those lines,
where data is to be transferred, i.e. active video lines, or
VBI-raw samples, no codes for empty lines

�

There may be more or less than 720 pixels between
SAV and EAV

�

Data content and number of clock cycles during
horizontal and vertical blanking is undefined, and may
be not constant

�

Data stream may be interleaved with not-valid data
codes, 00H, but SAV and EAV 4-byte codes are not
interleaved with not-valid data codes

�

There may be an irregular pattern of not-valid data, or
IDQ, and as a result, `C

- Y - C

- Y -' is not in a fixed

phase to a regular clock divider

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SAA7114H

�

VBI-raw sample streams are enveloped with
SAV and EAV, like normal video

�

Decoded VBI-data is transported as Ancillary (ANC)
data, two modes:

� direct decoded VBI-data bytes (8-bit) are directly

placed in the ANC data field, 00H and FFH codes
may appear in data block (violation to CCIR-656)

� recoded VBI-data bytes (8-bit) directly placed in ANC

data field, 00H and FFH codes will be recoded to
even parity codes 03H and FCH to suppress invalid
CCIR-656 codes.

There are no empty cycles in the ancillary code and its
data field. The data codes 00H and FFH are suppressed
(changed to 01H or FEH respectively) in active video
stream, as well as in VBI-raw sample stream (VBI
pass-through). Optionally the number range can be limited
further.

Table 31 Signals dedicated to the image port

SYMBOL

PIN

I/O

DESCRIPTION

BIT

IPD7 to
IPD0

54 to 57

and

59 to 62

I/O I-port data

ICODE[93H[7]], ISWP[1:0]85H[7:6]
and IPE[1:0]87[1:0]

ICLK

I/O continuous reference clock at image port, can

be input or output, as output decoder LLC or
XCLK from X-port

ICKS[1:0]80H[1:0] and
IPE[1:0]87H[1:0]

IDQ

data valid flag at image port, qualifier, with
programmable polarity;
secondary function: gated clock

ICKS2[80H[2]], IDQP[85H[0]] and
IPE[1:0]87H[1:0]

IGPH

horizontal reference output signal, copy of the
H-gate signal of the scaler, with programmable
polarity; alternative functions: HRESET pulse

IDH[1:0]84H[1:0], IRHP[85H[1]] and
IPE[1:0]87H[1:0]

IGPV

vertical reference output signal, copy of the
V-gate signal of the scaler, with programmable
polarity;
alternative functions: VRESET pulse

IDV[1:0]84H[3:2], IRVP[85H[2]] and
IPE[1:0]87H[1:0]

IGP1

general purpose output signal for I-port

IDG12[86H[4]], IDG1[1:0]84H[5:4],
IG1P[85H[3]] and IPE[1:0]87H[1:0]

IGP0

general purpose output signal for I-port

IDG02[86H[5]], IDG0[1:0]84H[7:6],
IG0P[85H[4]] and IPE[1:0]87H[1:0]

ITRDY

target ready input signals

ITRI

port control, switches I-port into 3-state

IPE[1:0]87H[1:0]

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

9.6

Host port for 16-bit extension of video data I/O (H-port)

The H-port pins HPD can be used for extension of the data I/O paths to 16-bit.

Functional priority has the I-port. If I8_16[93H[6]] is set to logic 1 the output drivers of the H-port are enabled dependent
on the I-port enable control. For I8_16 = 0, the HPD output is disabled.

Table 32 Signals dedicated to the host port

9.7

Basic input and output timing diagrams I-port and X-port

9.7.1

I-

PORT OUTPUT TIMING

The following diagrams are sketching the output timing via the I-port. IGPH and IGPV are sketched as logic 1 active gate
signals. If reference pulses are programmed, these pulses are generated on the rising edge of the logic 1 active gates.
Valid data is accompanied by the output data qualifier on pin IDQ. In addition invalid cycles are marked with output code
00H.

The IDQ output pin may be defined to be a gated clock output signal (ICLK AND internal IDQ).

9.7.2

X-

PORT INPUT TIMING

At the X-port the input timing requirements are the same as sketched for the I-port output. But different to this:

�

It is not necessary to mark invalid cycles with a 00H code

�

No constraints on the input qualifier (can be a random pattern)

�

XCLK may be a gated clock (XCLK AND external XDQ).

Remark: All timings illustrated in Figs 31 to 37 are given for an uninterrupted output stream (no handshake with the
external hardware).

SYMBOL

PIN

I/O

DESCRIPTION

BIT

HPD7 to HPD0

64 to 67

and

69 to 72

I/O 16-bit extension for digital I/O (chrominance

component)

IPE[1:0]87H[1:0], ITRI[8FH[6]] and
I8_16[93H[6]]

Fig.31 Output timing I-port for serial 8-bit data at start of a line (ICODE = 1).

handbook, full pagewidth

IPD[7:0]

IGPH

IDQ

ICLK

SAV

MHB550

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

10 BOUNDARY SCAN TEST

The SAA7114H has built in logic and 5 dedicated pins to
support boundary scan testing which allows board testing
without special hardware (nails). The SAA7114H follows
the

"IEEE Std. 1149.1 - Standard Test Access Port and

Boundary-Scan Architecture" set by the Joint Test Action
Group (JTAG) chaired by Philips.

The 5 special pins are Test Mode Select (TMS), Test
Clock (TCK), Test Reset (TRST), Test Data Input (TDI)
and Test Data Output (TDO).

The Boundary Scan Test (BST) functions BYPASS,
EXTEST, INTEST, SAMPLE, CLAMP and IDCODE are all
supported (see Table 33). Details about the
JTAG BST-TEST can be found in the specification "

IEEE

Std. 1149.1". A file containing the detailed Boundary Scan
Description Language (BSDL) description of the
SAA7114H is available on request.

Table 33 BST instructions supported by the SAA7114H

INSTRUCTION

DESCRIPTION

BYPASS

This mandatory instruction provides a minimum length serial path (1 bit) between TDI and TDO
when no test operation of the component is required.

EXTEST

This mandatory instruction allows testing of off-chip circuitry and board level interconnections.

SAMPLE

This mandatory instruction can be used to take a sample of the inputs during normal operation of
the component. It can also be used to preload data values into the latched outputs of the
boundary scan register.

CLAMP

This optional instruction is useful for testing when not all ICs have BST. This instruction addresses
the bypass register while the boundary scan register is in external test mode.

IDCODE

This optional instruction will provide information on the components manufacturer, part number and
version number.

INTEST

This optional instruction allows testing of the internal logic (no customer support available).

USER1

This private instruction allows testing by the manufacturer (no customer support available).

10.1

Initialization of boundary scan circuit

The TAP (Test Access Port) controller of an IC should be
in the reset state (TEST_LOGIC_RESET) when the IC is
in functional mode. This reset state also forces the
instruction register into a functional instruction such as
IDCODE or BYPASS.

To solve the power-up reset, the standard specifies that
the TAP controller will be forced asynchronously to the
TEST_LOGIC_RESET state by setting the TRST pin
LOW.

10.2

Device identification codes

A device identification register is specified in

"IEEE Std.

1149.1b-1994". It is a 32-bit register which contains fields
for the specification of the IC manufacturer, the IC part
number and the IC version number. Its biggest advantage
is the possibility to check for the correct ICs mounted after
production and determination of the version number of ICs
during field service.

When the IDCODE instruction is loaded into the BST
instruction register, the identification register will be
connected between TDI and TDO of the IC.
The identification register will load a component specific
code during the CAPTURE_DATA_REGISTER state of
the TAP controller and this code can subsequently be
shifted out. At board level this code can be used to verify
component manufacturer, type and version number. The
device identification register contains 32 bits, numbered
31 to 0, where bit 31 is the most significant bit (nearest to
TDI) and bit 0 is the least significant bit (nearest to TDO);
see Fig.38.

2000 Mar 15

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Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

Fig.38 32 bits of identification code.

handbook, full pagewidth

MHB557

00000010101

0111000100010100

nnnn

4-bit

version

code

16-bit part number

11-bit manufacturer

identification

TDI

TDO

MSB

LSB

28 27

12 11

11 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); all ground pins connected together and all supply
pins connected together.

Notes

1. Maximum: 4.6 V.

2. Except pin XTALI.

3. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k

resistor.

12 THERMAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

DDD

digital supply voltage

0.5

+4.6

DDA

analog supply voltage

0.5

+4.6

input voltage at analog inputs

0.5

DDA

+ 0.5

(1)

output voltage at analog output

0.5

DDA

+ 0.5

input voltage at digital inputs and outputs

outputs in 3-state;
note 2

0.5

+5.5

output voltage at digital outputs

outputs active

0.5

DDD

+ 0.5

voltage difference between V

SSAn

and V

SSDn

100

stg

storage temperature

+150

�

amb

operating ambient temperature

�

amb(bias)

operating ambient temperature under bias

+80

�

esd

electrostatic discharge all pins

note 3

2000 +2000

SYMBOL

PARAMETER

CONDITIONS

VALUE

UNIT

th(j-a)

thermal resistance from junction to ambient

in free air

K/W

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

13 CHARACTERISTICS
V

DDD

= 3.0 to 3.6 V; V

DDA

= 3.1 to 3.5 V; T

amb

= 25

�

C; timings and levels refer to drawings and conditions illustrated in

Fig.39; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies

DDD

digital supply voltage

3.0

3.3

3.6

DDD

digital supply current

X-port 3-state; 8-bit I-port

power dissipation digital
part

300

DDA

analog supply voltage

3.1

3.3

3.5

DDA

analog supply current

AOSL1 to AOSL0 = 0

CVBS mode

Y/C mode

power dissipation analog
part

CVBS mode

150

Y/C mode

240

tot(A+D)

total power dissipation
analog and digital part

CVBS mode

450

Y/C mode

540

tot(A+D)(pd)

total power dissipation
analog and digital part in
power-down mode

CE pulled down to ground

tot(A+D)(ps)

total power dissipation
analog and digital part in
power-save mode

C-bus controlled via

subaddress 88H = 0FH

Analog part

clamp

clamping current

= 0.9 V DC

�

i(p-p)

input voltage
(peak-to-peak value)

for normal video levels
1 V (p-p),

3 dB

termination 27/47

and

AC coupling required;
coupling capacitor = 22 nF

0.7

input impedance

clamping current off

200

input capacitance

channel crosstalk

< 5 MHz

9-bit analog-to-digital converters

analog bandwidth

3 dB

MHz

diff

differential phase
(amplifier plus anti-alias
filter bypassed)

deg

diff

differential gain
(amplifier plus anti-alias
filter bypassed)

clk(ADC)

ADC clock frequency

12.8

14.3

MHz

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

dc(d)

DC differential linearity
error

0.7

LSB

dc(i)

DC integral linearity error

LSB

Digital inputs

IL(SCL,SDA)

LOW-level input voltage
pins SDA and SCL

0.5

+0.3V

DDD

IH(SCL,SDA)

HIGH-level input voltage
pins SDA and SCL

0.7V

DDD

+ 0.5

IL(XTALI)

LOW-level CMOS input
voltage pin XTALI

0.3

+0.8

IH(XTALI)

HIGH-level CMOS input
voltage pin XTALI

2.0

DDD

+ 0.3

IL(n)

LOW-level input voltage all
other inputs

0.3

+0.8

IH(n)

HIGH-level input voltage
all other inputs

2.0

5.5

input leakage current

�

LI/O

I/O leakage current

�

input capacitance

I/O at high impedance

Digital outputs; note 1

OL(SDA)

LOW-level output voltage
pin SDA

SDA at 3 mA sink current

0.4

OL(clk)

LOW-level output voltage
for clocks

0.5

+0.6

OH(clk)

HIGH-level output voltage
for clocks

2.4

DDD

+ 0.5

LOW-level output voltage
all other digital outputs

0.4

HIGH-level output voltage
all other digital outputs

2.4

DDD

+ 0.5

Clock output timing (LLC and LLC2); note 2

output load capacitance

cycle time

pin LLC

pin LLC2

duty factors for t

LLCH

LLC

and t

LLC2H

LLC2

= 40 pF

rise time LLC and LLC2

0.2 V to V

DDD

0.2 V

fall time LLC and LLC2

DDD

0.2 V to 0.2 V

d(LLC-LLC2)

delay time between LLC
and LLC2 output

measured at 1.5 V;
C

= 25 pF

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

Horizontal PLL

hor(n)

nominal line frequency

50 Hz field

15625

60 Hz field

15734

hor

hor(n)

permissible static deviation

5.7

Subcarrier PLL

sc(n)

nominal subcarrier
frequency

PAL BGHI

4433619

NTSC M

3579545

PAL M

3575612

PAL N

3582056

lock-in range

�

400

Crystal oscillator for 32.11 MHz; note 3

xtal(n)

nominal frequency

3rd harmonic

32.11

MHz

xtal(n)

permissible nominal
frequency deviation

�

xtal(n)(T)

permissible nominal
frequency deviation with
temperature

�

RYSTAL SPECIFICATION

(Y1)

amb(X1)

operating ambient
temperature

�

load capacitance

series resonance resistor

motional capacitance

1.5

�

20%

parallel capacitance

4.3

�

20%

Crystal oscillator for 24.576 MHz; note 3

xtal(n)

nominal frequency

3rd harmonic

24.576

MHz

xtal(n)

permissible nominal
frequency deviation

�

xtal(n)(T)

permissible nominal
frequency deviation with
temperature

�

RYSTAL SPECIFICATION

(Y1)

amb(X1)

operating ambient
temperature

�

load capacitance

series resonance resistor

motional capacitance

1.5

�

20%

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

parallel capacitance

3.5

�

20%

Clock input timing (XCLK)

cycle time

duty factors for t

LLCH

LLC

rise time

fall time

Data and control signal input timing X-port, related to XCLK input

SU;DAT

input data set-up time

HD;DAT

input data hold time

Clock output timing

output load capacitance

cycle time

duty factors for
t

XCLKH

XCLKL

rise time

0.6 to 2.6 V

fall time

2.6 to 0.6 V

Data and control signal output timing X-port, related to XCLK output (for XPCK[1:0]83H[5:4] = 00 is default);
note 2

output load capacitance

OHD;DAT

output data hold time

= 15 pF

propagation delay from
positive edge of XCLK
output

= 15 pF

fall time

<tbf>

Control signal output timing RT port, related to LLC output

output load capacitance

OHD;DAT

output hold time

= 15 pF

propagation delay from
positive edge of LLC
output

= 15 pF

fall time

<tbf>

ICLK output timing

output load capacitance

cycle time

duty factors for t

ICLKH

ICLKL

rise time

0.6 to 2.6 V

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

Notes

1. The levels must be measured with load circuits; 1.2 k

at 3 V (TTL load); C

= 50 pF.

2. The effects of rise and fall times are included in the calculation of t

OHD;DAT

and t

. Timings and levels refer to

drawings and conditions illustrated in Fig.39.

3. The crystal oscillator drive level is typical 0.28 mW.

fall time

2.6 to 0.6 V

Data and control signal output timing I-port, related to ICLK output (for IPCK[1:0]87H[5:4] = 00 is default)

output load capacitance at
all outputs

OHD;DAT

output data hold time

= 15 pF

o(d)

output delay time

= 15 pF

dis

port disable time to 3-state C

= 25 pF

<tbf>

port enable time from
3-state

= 25 pF

<tbf>

ICLK input timing

cycle time

100

, t

LOW and HIGH times

<tbf>

rise time

<tbf>

Data and control signal output timing I-port, related to ICLK input (for ICKS[1:0]80H[1:0] = 11)

output load capacitance at
all outputs

<tbf>

OHD;DAT

output data hold time

= 15 pF

<tbf>

o(d)

output delay time

= 15 pF

<tbf>

dis

port disable time to 3-state C

= 25 pF

<tbf>

port enable time from
3-state

= 25 pF

<tbf>

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2000

Mar

Philips Semiconductors

Preliminar

y specification

AL/NTSC/SECAM video decoder with adaptiv

e P
AL/NTSC

comb filter

, VBI-data slicer and high perf

mance scaler

SAA7114H

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APPLICA

TION INFORMA

TION

handbook, full pagewidth

100

C24

�

3.3 V (D)

100

C12

100

C10

100

C11

100

C13

100

C23

�

3.3 V (A)

R19 open

DGND

AGND

AI11

AI12

AI21

AI22

AI23

AI24

R23

3.3

R10

R11

R12

R14

3.3 k

R24

C26

47 nF

C18

47 nF

C25

47 nF

C16

47 nF

C15

47 nF

C14

47 nF

C17

47 nF

C19

AI1D

AI12

AI2D

AI21

AI22

AI23

AI24

AI11

47 nF

R16

DGND

TP1

TP5

TP6

XCON[7:0]

XPD[7:0]

LLC

RTS0

RTS1

RTCO

RESON

TP7

TP4

TP2

TP3

�

DGND

24.576 MHz

C20
10 pF

1 nF

C22

C21
10 pF

IMCON[7:0]

IPDL[7:0]

HPDL[7:0]

BST2

BST[2:0]

TDI

TDO

DD(3.3)

3.3 V (D)

3.3 V (A)

L2 2.2

�

L3 2.2

�

DDA(3.3)

AOUT

SDA

SCL

R18 0

R21 open
R22 open

R15 3.3 k

R17

ACLK

3.3 V (D)

DGND

R20 open

R13 open

Strapping
clock frequency

Strapping
I

C-bus slave address

Place 0

if BST is not used

AMCLK

ASCLK

ALRCLK

AMXCLK

XTALO

XTALI

XRH

XRV

XRDY

XDQ

XCLK

XTRI

XTOUT

XCON0

XCON1

XCON2

XCON3

XCON4

XCON5

XCON6

XPD7

XPD6

XPD5

XPD4

XPD3

XPD2

XPD1

XPD0

XPD7

XPD6

XPD5

XPD4

XPD3

XPD2

XPD1

XPD0

RTCO

RTS1

RTS0

TEST0

TEST1

TEST2

LLC

LLC2

RES

SSDE1

100

SSDE2

SSDE3

SSDE4

SSX

SSDI3

SSDI2

SSDI1

SSA0

SSA1

SSA2

AGND

IGPH

ITRDY

ICLK

IDQ

ITRI

IGP0

IGP1

IGPV

IMCON0

IMCON7

IMCON6

IMCON5

IMCON4

IMCON3

IMCON2

IMCON1

IPD7

IPD6

IPD5

IPD4

IPD3

IPD2

IPD1

IPD0

IPD6

IPD5

IPD4

IPD3

IPD2

IPD1

IPD0

IPD7

98 99 97 3

TCK

TMS

TRST

TDI

TDO

BST0

BST1

BST2

23 17 11

33 43 58 68 83 93

SAA7114H

DDX

DDDE1

DDDI1

DDDI2

DDDI3

DDDI4

DDDI5

DDDI6

DDA0

DDA1

DDA2

DDDE2

DDDE4

DDDE3

72 71 70 69 67 66 65 64

31 32

HPD5

HPD6

HPD7

TEST3

SCL

SDA

AOUT

78 79

TEST4

TEST5

HPD0

HPD1

HPD2

HPD3

HPD4

HPD5

HPD6

HPD7

HPD0

HPD1

HPD2

HPD3

HPD4

MHB527

Fig.40 Application example with 24.576 MHz crystal.

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

Table 34 Description of I

C-bus format

Note

1. If pin RTCO strapped to ground via a 3.3 k

resistor.

Table 35 Subaddress description and access

CODE

DESCRIPTION

START condition

repeated START condition

Slave address W

`0100 0010' (= 42H, default) or `0100 0000' (= 40H; note 1)

Slave address R

`0100 0011' (= 43H, default) or `0100 0001' (= 41H; note 1)

ACK-s

acknowledge generated by the slave

ACK-m

acknowledge generated by the master

Subaddress

subaddress byte; see Tables 35 and 36

Data

data byte; see Table 36; if more than one byte DATA is transmitted the subaddress pointer is
automatically incremented

STOP condition

read/write control bit (LSB slave address); X = 0, order to write (the circuit is slave receiver);
X = 1, order to read (the circuit is slave transmitter)

SUBADDRESS

DESCRIPTION

ACCESS (READ/WRITE)

00H

chip version

read only

F0H to FFH

reserved

Video decoder: 01H to 2FH

01H to 05H

front-end part

read and write

06H to 19H

decoder part

read and write

1AH to 1EH

reserved

1FH

video decoder status byte

read only

20H to 2FH

reserved

Audio clock generation: 30H to 3FH

30H to 3AH

audio clock generator

read and write

3BH to 3FH

reserved

General purpose VBI-data slicer: 40H to 7FH

40H to 60H

VBI-data slicer

read and write

61H to 62H

VBI-data slicer status

read only

64H to 7FH

reserved

X-port, I-port and the scaler: 80H to EFH

80H to 8FH

task independent global settings

read and write

90H to BFH

task A definition

read and write

C0H to EFH

task B definition

read and write

2000

Mar

Philips Semiconductors

Preliminar

y specification

AL/NTSC/SECAM video decoder with adaptiv

e P
AL/NTSC

comb filter

, VBI-data slicer and high perf

mance scaler

SAA7114H

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Table 36 I

C-bus receiver/transmitter overview

REGISTER FUNCTION

SUB

ADDR.

(HEX)

Chip version: register 00H

Chip version (read only)

ID07

ID06

ID05

ID04

Video decoder: registers 01H to 2FH

RONT

END PART

REGISTERS

01H

05H

Horizontal increment delay

(1)

IDEL3

IDEL2

IDEL1

IDEL0

Analog input control 1

FUSE1

FUSE0

GUDL1

GUDL0

MODE3

MODE2

MODE1

MODE0

Analog input control 2

(1)

HLNRS

VBSL

WPOFF

HOLDG

GAFIX

GAI28

GAI18

Analog input control 3

GAI17

GAI16

GAI15

GAI14

GAI13

GAI12

GAI11

GAI10

Analog input control 4

GAI27

GAI26

GAI25

GAI24

GAI23

GAI22

GAI21

GAI20

ECODER PART

REGISTERS

06H

2FH

Horizontal sync start

HSB7

HSB6

HSB5

HSB4

HSB3

HSB2

HSB1

HSB0

Horizontal sync stop

HSS7

HSS6

HSS5

HSS4

HSS3

HSS2

HSS1

HSS0

Sync control

AUFD

FSEL

FOET

HTC1

HTC0

HPLL

VNOI1

VNOI0

Luminance control

BYPS

YCOMB

LDEL

LUBW

LUFI3

LUFI2

LUFI1

LUFI0

Luminance brightness control

DBRI7

DBRI6

DBRI5

DBRI4

DBRI3

DBRI2

DBRI1

DBRI0

Luminance contrast control

DCON7

DCON6

DCON5

DCON4

DCON3

DCON2

DCON1

DCON0

Chrominance saturation control

DSAT7

DSAT6

DSAT5

DSAT4

DSAT3

DSAT2

DSAT1

DSAT0

Chrominance hue control

HUEC7

HUEC6

HUEC5

HUEC4

HUEC3

HUEC2

HUEC1

HUEC0

Chrominance control 1

CDTO

CSTD2

CSTD1

CSTD0

DCVF

FCTC

(1)

CCOMB

Chrominance gain control

ACGC

CGAIN6

CGAIN5

CGAIN4

CGAIN3

CGAIN2

CGAIN1

CGAIN0

Chrominance control 2

OFFU1

OFFU0

OFFV1

OFFV0

CHBW

LCBW2

LCBW1

LCBW0

Mode/delay control

COLO

RTP1

HDEL1

HDEL0

RTP0

YDEL2

YDEL1

YDEL0

RT signal control

RTSE13

RTSE12

RTSE11

RTSE10

RTSE03

RTSE02

RTSE01

RTSE00

RT/X-port output control

RTCE

XRHS

XRVS1

XRVS0

HLSEL

OFTS2

OFTS1

OFTS0

Analog/ADC/compatibility
control

CM99

UPTCV

AOSL1

AOSL0

XTOUTE

OLDSB

APCK1

APCK0

VGATE start, FID change

VSTA7

VSTA6

VSTA5

VSTA4

VSTA3

VSTA2

VSTA1

VSTA0

VGATE stop

VSTO7

VSTO6

VSTO5

VSTO4

VSTO3

VSTO2

VSTO1

VSTO0

Miscellaneous/VGATE MSBs

LLCE

LLC2E

(1)

VGPS

VSTO8

VSTA8

2000

Mar

Philips Semiconductors

Preliminar

y specification

AL/NTSC/SECAM video decoder with adaptiv

e P
AL/NTSC

comb filter

, VBI-data slicer and high perf

mance scaler

SAA7114H

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Raw data gain control

RAWG7

RAWG6

RAWG5

RAWG4

RAWG3

RAWG2

RAWG1

RAWG0

Raw data offset control

RAWO7

RAWO6

RAWO5

RAWO4

RAWO3

RAWO2

RAWO1

RAWO0

Reserved

1A to 1E

(1)

Status byte video decoder
(read only, OLDSB = 0)

INTL

HLVLN

FIDT

GLIMT

GLIMB

WIPA

COPRO

RDCAP

Status byte video decoder
(read only, OLDSB = 1)

INTL

HLCK

FIDT

GLIMT

GLIMB

WIPA

SLTCA

CODE

Reserved

20 to 2F

(1)

Audio clock generator part: registers 30H to 3FH

Audio master clock cycles per
field

ACPF7

ACPF6

ACPF5

ACPF4

ACPF3

ACPF2

ACPF1

ACPF0

ACPF15

ACPF14

ACPF13

ACPF12

ACPF11

ACPF10

ACPF9

ACPF8

(1)

ACPF17

ACPF16

Reserved

(1)

Audio master clock nominal
increment

ACNI7

ACNI6

ACNI5

ACNI4

ACNI3

ACNI2

ACNI1

ACNI0

ACNI15

ACNI14

ACNI13

ACNI12

ACNI11

ACNI10

ACNI9

ACNI8

(1)

ACNI21

ACNI20

ACNI19

ACNI18

ACNI17

ACNI16

Reserved

(1)

Clock ratio AMCLK to ASCLK

(1)

SDIV5

SDIV4

SDIV3

SDIV2

SDIV1

SDIV0

Clock ratio ASCLK to ALRCLK

(1)

LRDIV5

LRDIV4

LRDIV3

LRDIV2

LRDIV1

LRDIV0

Audio clock control

(1)

APLL

AMVR

LRPH

SCPH

Reserved

3B to 3F

(1)

General purpose VBI-data slicer part: registers 40H to 7FH

Slicer control 1

(1)

HAM_N

FCE

HUNT_N

(1)

LCR2 to LCR24 (n = 2 to 24)

41 to 57

LCRn_7

LCRn_6

LCRn_5

LCRn_4

LCRn_3

LCRn_2

LCRn_1

LCRn_0

Programmable framing code

FC7

FC6

FC5

FC4

FC3

FC2

FC1

FC0

Horizontal offset for slicer

HOFF7

HOFF6

HOFF5

HOFF4

HOFF3

HOFF2

HOFF1

HOFF0

Vertical offset for slicer

VOFF7

VOFF6

VOFF5

VOFF4

VOFF3

VOFF2

VOFF1

VOFF0

Field offset and MSBs for
horizontal and vertical offset

FOFF

RECODE

(1)

VOFF8

(1)

HOFF10

HOFF9

HOFF8

Reserved (for testing)

(1)

REGISTER FUNCTION

SUB

ADDR.

(HEX)

2000

Mar

Philips Semiconductors

Preliminar

y specification

AL/NTSC/SECAM video decoder with adaptiv

e P
AL/NTSC

comb filter

, VBI-data slicer and high perf

mance scaler

SAA7114H

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Header and data identification
(DID) code control

FVREF

(1)

DID5

DID4

DID3

DID2

DID1

DID0

Sliced data identification (SDID)
code

(1)

SDID5

SDID4

SDID3

SDID2

SDID1

SDID0

Reserved

(1)

Slicer status byte 0 (read only)

FC8V

FC7V

VPSV

PPV

CCV

Slicer status byte 1 (read only)

F21_N

LN8

LN7

LN6

LN5

LN4

Slicer status byte 2 (read only)

LN3

LN2

LN1

LN0

DT3

DT2

DT1

DT0

Reserved

63 to 7F

(1)

X-port, I-port and the scaler part: registers 80H to EFH

ASK INDEPENDENT GLOBAL SETTINGS

: 80H

8FH

Global control 1

(1)

SMOD

TEB

TEA

ICKS3

ICKS2

ICKS1

ICKS0

Reserved

81 and

(1)

X-port I/O enable and output
clock phase control

(1)

XPCK1

XPCK0

(1)

XRQT

XPE1

XPE0

I-port signal definitions

IDG01

IDG00

IDG11

IDG10

IDV1

IDV0

IDH1

IDH0

I-port signal polarities

ISWP1

ISWP0

ILLV

IG0P

IG1P

IRVP

IRHP

IDQP

I-port FIFO flag control and
arbitration

VITX1

VITX0

IDG02

IDG12

FFL1

FFL0

FEL1

FEL0

I-port I/O enable, output clock
and gated clock phase control

IPCK3

IPCK2

IPCK1

IPCK0

(1)

IPE1

IPE0

Power save control

CH4EN

CH2EN

SWRST

DPROG

SLM3

(1)

SLM1

SLM0

Reserved

89 to 8E

(1)

Status information scaler part

XTRI

ITRI

FFIL

FFOV

PRDON

ERR_OF

FIDSCI

FIDSCO

ASK

DEFINITION

REGISTERS

90H

BFH

Basic settings and acquisition window definition

Task handling control

CONLH

OFIDC

FSKP2

FSKP1

FSKP0

RPTSK

STRC1

STRC0

X-port formats and configuration

CONLV

HLDFV

SCSRC1

SCSRC0

SCRQE

FSC2

FSC1

FSC0

X-port input reference signal
definition

XFDV

XFDH

XDV1

XDV0

XCODE

XDH

XDQ

XCKS

REGISTER FUNCTION

SUB

ADDR.

(HEX)

2000

Mar

Philips Semiconductors

Preliminar

y specification

AL/NTSC/SECAM video decoder with adaptiv

e P
AL/NTSC

comb filter

, VBI-data slicer and high perf

mance scaler

SAA7114H

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I-port format and configuration

ICODE

I8_16

FYSK

FOI1

FOI0

FSI2

FSI1

FSI0

Horizontal input window start

XO7

XO6

XO5

XO4

XO3

XO2

XO1

XO0

(1)

XO11

XO10

XO9

XO8

Horizontal input window length

XS7

XS6

XS5

XS4

XS3

XS2

XS1

XS0

(1)

XS11

XS10

XS9

XS8

Vertical input window start

YO7

YO6

YO5

YO4

YO3

YO2

YO1

YO0

(1)

YO11

YO10

YO9

YO8

Vertical input window length

YS7

YS6

YS5

YS4

YS3

YS2

YS1

YS0

(1)

YS11

YS10

YS9

YS8

Horizontal output window length

XD7

XD6

XD5

XD4

XD3

XD2

XD1

XD0

(1)

XD11

XD10

XD9

XD8

Vertical output window length

YD7

YD6

YD5

YD4

YD3

YD2

YD1

YD0

(1)

YD11

YD10

YD9

YD8

FIR filtering and prescaling

Horizontal prescaling

(1)

XPSC5

XPSC4

XPSC3

XPSC2

XPSC1

XPSC0

Accumulation length

(1)

XACL5

XACL4

XACL3

XACL2

XACL1

XACL0

Prescaler DC gain and FIR
prefilter control

PFUV1

PFUV0

PFY1

PFY0

XC2_1

XDCG2

XDCG1

XDCG0

Reserved

(1)

Luminance brightness setting

BRIG7

BRIG6

BRIG5

BRIG4

BRIG3

BRIG2

BRIG1

BRIG0

Luminance contrast setting

CONT7

CONT6

CONT5

CONT4

CONT3

CONT2

CONT1

CONT0

Chrominance saturation setting

SATN7

SATN6

SATN5

SATN4

SATN3

SATN2

SATN1

SATN0

Reserved

(1)

Horizontal phase scaling

Horizontal luminance scaling
increment

XSCY7

XSCY6

XSCY5

XSCY4

XSCY3

XSCY2

XSCY1

XSCY0

(1)

XSCY12

XSCY11

XSCY10

XSCY9

XSCY8

Horizontal luminance phase
offset

XPHY7

XPHY6

XPHY5

XPHY4

XPHY3

XPHY2

XPHY1

XPHY0

Reserved

(1)

REGISTER FUNCTION

SUB

ADDR.

(HEX)

2000

Mar

Philips Semiconductors

Preliminar

y specification

AL/NTSC/SECAM video decoder with adaptiv

e P
AL/NTSC

comb filter

, VBI-data slicer and high perf

mance scaler

SAA7114H

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Horizontal chrominance scaling
increment

XSCC7

XSCC6

XSCC5

XSCC4

XSCC3

XSCC2

XSCC1

XSCC0

(1)

XSCC12

XSCC11

XSCC10

XSCC9

XSCC8

Horizontal chrominance phase
offset

XPHC7

XPHC6

XPHC5

XPHC4

XPHC3

XPHC2

XPHC1

XPHC0

Reserved

(1)

Vertical scaling

Vertical luminance scaling
increment

YSCY7

YSCY6

YSCY5

YSCY4

YSCY3

YSCY2

YSCY1

YSCY0

YSCY15

YSCY14

YSCY13

YSCY12

YSCY11

YSCY10

YSCY9

YSCY8

Vertical chrominance scaling
increment

YSCC7

YSCC6

YSCC5

YSCC4

YSCC3

YSCC2

YSCC1

YSCC0

YSCC15

YSCC14

YSCC13

YSCC12

YSCC11

YSCC10

YSCC9

YSCC8

Vertical scaling mode control

(1)

YMIR

(1)

YMODE

Reserved

B5 to B7

(1)

Vertical chrominance phase
offset `00'

YPC07

YPC06

YPC05

YPC04

YPC03

YPC02

YPC01

YPC00

Vertical chrominance phase
offset `01'

YPC17

YPC16

YPC15

YPC14

YPC13

YPC12

YPC11

YPC10

Vertical chrominance phase
offset `10'

YPC27

YPC26

YPC25

YPC24

YPC23

YPC22

YPC21

YPC20

Vertical chrominance phase
offset `11'

YPC37

YPC36

YPC35

YPC34

YPC33

YPC32

YPC31

YPC30

Vertical luminance phase
offset `00'

YPY07

YPY06

YPY05

YPY04

YPY03

YPY02

YPY01

YPY00

Vertical luminance phase
offset `01'

YPY17

YPY16

YPY15

YPY14

YPY13

YPY12

YPY11

YPY10

Vertical luminance phase
offset `10'

YPY27

YPY26

YPY25

YPY24

YPY23

YPY22

YPY21

YPY20

Vertical luminance phase
offset `11'

YPY37

YPY36

YPY35

YPY34

YPY33

YPY32

YPY31

YPY30

ASK

DEFINITION REGISTERS

C0H

EFH

Basic settings and acquisition window definition

Task handling control

CONLH

OFIDC

FSKP2

FSKP1

FSKP0

RPTSK

STRC1

STRC0

REGISTER FUNCTION

SUB

ADDR.

(HEX)

2000

Mar

Philips Semiconductors

Preliminar

y specification

AL/NTSC/SECAM video decoder with adaptiv

e P
AL/NTSC

comb filter

, VBI-data slicer and high perf

mance scaler

SAA7114H

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X-port formats and configuration

CONLV

HLDFV

SCSRC1

SCSRC0

SCRQE

FSC2

FSC1

FSC0

Input reference signal definition

XFDV

XFDH

XDV1

XDV0

XCODE

XDH

XDQ

XCKS

I-port format and configuration

ICODE

I8_16

FYSK

FOI1

FOI0

FSI2

FSI1

FSI0

Horizontal input window start

XO7

XO6

XO5

XO4

XO3

XO2

XO1

XO0

(1)

XO11

XO10

XO9

XO8

Horizontal input window length

XS7

XS6

XS5

XS4

XS3

XS2

XS1

XS0

(1)

XS11

XS10

XS9

XS8

Vertical input window start

YO7

YO6

YO5

YO4

YO3

YO2

YO1

YO0

(1)

YO11

YO10

YO9

YO8

Vertical input window length

YS7

YS6

YS5

YS4

YS3

YS2

YS1

YS0

(1)

YS11

YS10

YS9

YS8

Horizontal output window length

XD7

XD6

XD5

XD4

XD3

XD2

XD1

XD0

(1)

XD11

XD10

XD9

XD8

Vertical output window length

YD7

YD6

YD5

YD4

YD3

YD2

YD1

YD0

(1)

YD11

YD10

YD9

YD8

FIR filtering and prescaling

Horizontal prescaling

(1)

XPSC5

XPSC4

XPSC3

XPSC2

XPSC1

XPSC0

Accumulation length

(1)

XACL5

XACL4

XACL3

XACL2

XACL1

XACL0

Prescaler DC gain and FIR
prefilter control

PFUV1

PFUV0

PFY1

PFY0

XC2_1

XDCG2

XDCG1

XDCG0

Reserved

(1)

Luminance brightness setting

BRIG7

BRIG6

BRIG5

BRIG4

BRIG3

BRIG2

BRIG1

BRIG0

Luminance contrast setting

CONT7

CONT6

CONT5

CONT4

CONT3

CONT2

CONT1

CONT0

Chrominance saturation setting

SATN7

SATN6

SATN5

SATN4

SATN3

SATN2

SATN1

SATN0

Reserved

(1)

Horizontal phase scaling

Horizontal luminance scaling
increment

XSCY7

XSCY6

XSCY5

XSCY4

XSCY3

XSCY2

XSCY1

XSCY0

(1)

XSCY12

XSCY11

XSCY10

XSCY9

XSCY8

Horizontal luminance phase
offset

XPHY7

XPHY6

XPHY5

XPHY4

XPHY3

XPHY2

XPHY1

XPHY0

REGISTER FUNCTION

SUB

ADDR.

(HEX)

2000

Mar

Philips Semiconductors

Preliminar

y specification

AL/NTSC/SECAM video decoder with adaptiv

e P
AL/NTSC

comb filter

, VBI-data slicer and high perf

mance scaler

SAA7114H

This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in

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Note

1. All unused control bits must be programmed with logic 0 to ensure compatibility to future enhancements.

Reserved

(1)

Horizontal chrominance scaling
increment

XSCC7

XSCC6

XSCC5

XSCC4

XSCC3

XSCC2

XSCC1

XSCC0

(1)

XSCC12

XSCC11

XSCC10

XSCC9

XSCC8

Horizontal chrominance phase
offset

XPHC7

XPHC6

XPHC5

XPHC4

XPHC3

XPHC2

XPHC1

XPHC0

Reserved

(1)

Vertical scaling

Vertical luminance scaling
increment

YSCY7

YSCY6

YSCY5

YSCY4

YSCY3

YSCY2

YSCY1

YSCY0

YSCY15

YSCY14

YSCY13

YSCY12

YSCY11

YSCY10

YSCY9

YSCY8

Vertical chrominance scaling
increment

YSCC7

YSCC6

YSCC5

YSCC4

YSCC3

YSCC2

YSCC1

YSCC0

YSCC15

YSCC14

YSCC13

YSCC12

YSCC11

YSCC10

YSCC9

YSCC8

Vertical scaling mode control

(1)

YMIR

(1)

YMODE

Reserved

E5 to E7

(1)

Vertical chrominance phase
offset `00'

YPC07

YPC06

YPC05

YPC04

YPC03

YPC02

YPC01

YPC00

Vertical chrominance phase
offset `01'

YPC17

YPC16

YPC15

YPC14

YPC13

YPC12

YPC11

YPC10

Vertical chrominance phase
offset `10'

YPC27

YPC26

YPC25

YPC24

YPC23

YPC22

YPC21

YPC20

Vertical chrominance phase
offset `11'

YPC37

YPC36

YPC35

YPC34

YPC33

YPC32

YPC31

YPC30

Vertical luminance phase
offset `00'

YPY07

YPY06

YPY05

YPY04

YPY03

YPY02

YPY01

YPY00

Vertical luminance phase
offset `01'

YPY17

YPY16

YPY15

YPY14

YPY13

YPY12

YPY11

YPY10

Vertical luminance phase
offset `10'

YPY27

YPY26

YPY25

YPY24

YPY23

YPY22

YPY21

YPY20

Vertical luminance phase
offset `11'

YPY37

YPY36

YPY35

YPY34

YPY33

YPY32

YPY31

YPY30

REGISTER FUNCTION

SUB

ADDR.

(HEX)

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

15.2

C-bus details

15.2.1

UBADDRESS

00H

Table 37 Chip Version (CV) identification; 00H[7:4]; read only register

15.2.2

UBADDRESS

01H

The programming of the horizontal increment delay is used to match internal processing delays to the delay of the ADC.
Use recommended position only.

Table 38 Horizontal increment delay; 01H[3:0]

15.2.3

UBADDRESS

02H

Table 39 Analog input control 1 (AICO1); 02H[7:0]

FUNCTION

LOGIC LEVELS

ID07

ID06

ID05

ID04

Chip Version (CV)

CV0

CV1

CV2

CV3

FUNCTION

IDEL3

IDEL2

IDEL1

IDEL0

No update

Minimum delay

Recommended position

Maximum delay

BIT

DESCRIPTION

SYMBOL

VALUE

FUNCTION

D[7:6] analog function

select (see Fig.6)

FUSE[1:0]

amplifier plus anti-alias filter bypassed

amplifier active

amplifier plus anti-alias filter active

D[5:4] update

hysteresis for
9-bit gain (see
Fig.7)

GUDL[1:0]

off

�

1 LSB

�

2 LSB

�

3 LSB

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

Note

1. To take full advantage of the Y/C-modes 6 to 9 the I

C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1

(full luminance bandwidth).

D[3:0] mode selection

MODE[3:0]

0000

Mode 0: CVBS (automatic gain) from AI11 (pin 20); see Fig. 43

0001

Mode 1: CVBS (automatic gain) from AI12 (pin 18); see Fig. 44

0010

Mode 2: CVBS (automatic gain) from AI21 (pin 16); see Fig. 45

0011

Mode 3: CVBS (automatic gain) from AI22 (pin 14); see Fig. 46

0100

Mode 4: CVBS (automatic gain) from AI23 (pin 12); see Fig. 47

0101

Mode 5: CVBS (automatic gain) from AI24 (pin 10); see Fig. 48

0110

Mode 6: Y (automatic gain) from AI11 (pin 20) + C (gain adjustable
via GAI28 to GAI20) from AI21 (pin 16); note 1; see Fig. 49

0111

Mode 7: Y (automatic gain) from AI12 (pin 18) + C (gain adjustable
via GAI28 to GAI20) from AI22 (pin 14); note 1; see Fig. 50

1000

Mode 8: Y (automatic gain) from AI11 (pin 20) + C (gain adapted to
Y gain) from AI21 (pin 16); note 1; see Fig. 51

1001

Mode 9: Y (automatic gain) from AI12 (pin 18) + C (gain adapted to
Y gain) from AI22 (pin 14); note 1; see Fig. 52

1111

Modes 10 to 15: reserved

BIT

DESCRIPTION

SYMBOL

VALUE

FUNCTION

Fig.43 Mode 0; CVBS (automatic gain).

handbook, halfpage

MHB559

AI22
AI21

AI12

AI11

AD2

AD1

CHROMA

LUMA

AI24
AI23

Fig.44 Mode 1; CVBS (automatic gain).

handbook, halfpage

MHB560

AI12

AI11

AD2

AD1

CHROMA

LUMA

AI22
AI21

AI24
AI23

Fig.45 Mode 2; CVBS (automatic gain).

handbook, halfpage

MHB561

AI12

AI11

AD2

AD1

CHROMA

LUMA

AI22
AI21

AI24
AI23

Fig.46 Mode 3; CVBS (automatic gain).

handbook, halfpage

MHB562

AI12

AI11

AD2

AD1

CHROMA

LUMA

AI22
AI21

AI24
AI23

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

Fig.47 Mode 4; CVBS (automatic gain).

handbook, halfpage

MHB563

AI12

AI11

AD2

AD1

CHROMA

LUMA

AI22
AI21

AI24
AI23

Fig.48 Mode 5; CVBS (automatic gain).

handbook, halfpage

MHB564

AI12

AI11

AD2

AD1

CHROMA

LUMA

AI22
AI21

AI24
AI23

Fig.49 Mode 6; Y + C (gain channel 2 adjusted via

GAI2).

C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1

(full luminance bandwidth).

handbook, halfpage

MHB565

AI12

AI11

AD2

AD1

CHROMA

LUMA

AI22
AI21

AI24
AI23

Fig.50 Mode 7; Y + C (gain channel 2 adjusted via

GAI2).

C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1

(full luminance bandwidth).

handbook, halfpage

MHB566

AI12

AI11

AD2

AD1

CHROMA

LUMA

AI22
AI21

AI24
AI23

Fig.51 Mode 8; Y + C (gain channel 2 adapted to Y

gain).

C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1

(full luminance bandwidth).

handbook, halfpage

MHB567

AI12

AI11

AD2

AD1

CHROMA

LUMA

AI22
AI21

AI24
AI23

Fig.52 Mode 9; Y + C (gain channel 2 adapted to Y

gain).

C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1

(full luminance bandwidth).

handbook, halfpage

MHB568

AI12

AI11

AD2

AD1

CHROMA

LUMA

AI22
AI21

AI24
AI23

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

15.2.4

UBADDRESS

03H

Table 40 Analog input control 2 (AICO2); 03H[6:0]

15.2.5

UBADDRESS

04H

Table 41 Analog input control 3 (AICO3): static gain control channel 1; 03H[0] and 04H[7:0]

15.2.6

UBADDRESS

05H

Table 42 Analog input control 4 (AICO4); static gain control channel 2; 03H[1] and 05H[7:0]

BIT

DESCRIPTION

SYMBOL VALUE

FUNCTION

D6 HL not reference select

HLNRS

normal clamping if decoder is in unlocked state

reference select if decoder is in unlocked state

D5 AGC hold during vertical

blanking period

VBSL

short vertical blanking (AGC disabled during equalization
and serration pulses)

long vertical blanking (AGC disabled from start of
pre-equalization pulses until start of active video (line 22 for
60 Hz, line 24 for 50 Hz)

D4 white peak off

WPOFF

white peak control active

white peak off

D3 automatic gain control

integration

HOLDG

AGC active

AGC integration hold (freeze)

gain control fix

GAFIX

automatic gain controlled by MODE3 to MODE0

gain is user programmable via GAI[17:10] and GAI[27:20]

static gain control channel 2
sign bit

GAI28

see Table 42

static gain control channel 1
sign bit

GAI18

see Table 41

DECIMAL

VALUE

GAIN

(dB)

SIGN BIT

03H[0]

CONTROL BITS D7 TO D0

GAI18

GAI17

GAI16

GAI15

GAI14

GAI13

GAI12

GAI11

GAI10

0...

...144

145...

...511

DECIMAL

VALUE

GAIN

(dB)

SIGN BIT

03H[1]

CONTROL BITS D7 TO D0

GAI28

GAI27

GAI26

GAI25

GAI24

GAI23

GAI22

GAI21

GAI20

0...

...144

145...

...511

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

15.2.7

UBADDRESS

06H

Table 43 Horizontal sync start; 06H[7:0]

15.2.8

UBADDRESS

07H

Table 44 Horizontal sync stop; 07H[7:0]

DELAY TIME

(STEP SIZE = 8/LLC)

CONTROL BITS D7 TO D0

HSB7

HSB6

HSB5

HSB4

HSB3

HSB2

HSB1

HSB0

128...

109 (50 Hz)

forbidden (outside available central counter range)

128...

108 (60 Hz)

108 (50 Hz)...

107 (60 Hz)...

...108 (50 Hz)

...107 (60 Hz)

109...127 (50 Hz)

forbidden (outside available central counter range)

108...127 (60 Hz)

DELAY TIME

(STEP SIZE = 8/LLC)

CONTROL BITS D7 TO D0

HSS7

HSS6

HSS5

HSS4

HSS3

HSS2

HSS1

HSS0

128...

109 (50 Hz)

forbidden (outside available central counter range)

128...

108 (60 Hz)

108 (50 Hz)...

107 (60 Hz)...

...108 (50 Hz)

...107 (60 Hz)

109...127 (50 Hz)

forbidden (outside available central counter range)

108...127 (60 Hz)

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

15.2.9

UBADDRESS

08H

Table 45 Sync control; 08H[7:0]

BIT

DESCRIPTION

SYMBOL VALUE

FUNCTION

automatic field detection

AUFD

field state directly controlled via FSEL

automatic field detection; recommended setting

field selection

FSEL

50 Hz, 625 lines

60 Hz, 525 lines

forced ODD/EVEN toggle

FOET

ODD/EVEN signal toggles only with interlaced source

ODD/EVEN signal toggles fieldwise even if source is
non-interlaced

D[4:3] horizontal time constant

selection

HTC[1:0]

TV mode, recommended for poor quality TV signals only; do
not use for new applications

VTR mode, recommended if a deflection control circuit is
directly connected to the SAA7114H

reserved

fast locking mode; recommended setting

horizontal PLL

HPLL

PLL closed

PLL open; horizontal frequency fixed

D[1:0] vertical noise reduction

VNOI[1:0]

normal mode; recommended setting

fast mode, applicable for stable sources only; automatic field
detection (AUFD) must be disabled

free running mode

vertical noise reduction bypassed

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

15.2.10 S

UBADDRESS

09H

Table 46 Luminance control; 09H[7:0]

15.2.11 S

UBADDRESS

0AH

Table 47 Luminance brightness control: decoder part; 0AH[7:0]

BIT

DESCRIPTION

SYMBOL VALUE

FUNCTION

chrominance trap/comb filter
bypass

BYPS

chrominance trap or luminance comb filter active;
default for CVBS mode

chrominance trap or luminance comb filter bypassed;
default for S-video mode

adaptive luminance comb filter

YCOMB

disabled (= chrominance trap enabled, if BYPS = 0)

active, if BYPS = 0

processing delay in non comb
filter mode

LDEL

processing delay is equal to internal pipelining delay

one (NTSC standards) or two (PAL standards) video
lines additional processing delay

remodulation bandwidth for
luminance; see Figs 12 to 15

LUBW

small remodulation bandwidth
(narrow chroma notch

higher luminance bandwidth)

large remodulation bandwidth
(wider chroma notch

smaller luminance bandwidth)

D[3:0] sharpness control, luminance

filter characteristic; see Fig.16

LUFI[3:0]

0001

resolution enhancement filter 8.0 dB at 4.1 MHz

0010

resolution enhancement filter 6.8 dB at 4.1 MHz

0011

resolution enhancement filter 5.1 dB at 4.1 MHz

0100

resolution enhancement filter 4.1 dB at 4.1 MHz

0101

resolution enhancement filter 3.0 dB at 4.1 MHz

0110

resolution enhancement filter 2.3 dB at 4.1 MHz

0111

resolution enhancement filter 1.6 dB at 4.1 MHz

0000

plain

1000

low-pass filter 2 dB at 4.1 MHz

1001

low-pass filter 3 dB at 4.1 MHz

1010

low-pass filter 3 dB at 3.3 MHz; 4 dB at 4.1 MHz

1011

low-pass filter 3 dB at 2.6 MHz; 8 dB at 4.1 MHz

1100

low-pass filter 3 dB at 2.4 MHz; 14 dB at 4.1 MHz

1101

low-pass filter 3 dB at 2.2 MHz; notch at 3.4 MHz

1110

low-pass filter 3 dB at 1.9 MHz; notch at 3.0 MHz

1111

low-pass filter 3 dB at 1.7 MHz; notch at 2.5 MHz

OFFSET

CONTROL BITS D7 TO D0

DBRI7

DBRI6

DBRI5

DBRI4

DBRI3

DBRI2

DBRI1

DBRI0

255 (bright)

128 (ITU level)

0 (dark)

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

15.2.12 S

UBADDRESS

0BH

Table 48 Luminance contrast control; decoder part; 0BH[7:0]

15.2.13 S

UBADDRESS

0CH

Table 49 Chrominance saturation control: decoder part; 0CH[7:0]

15.2.14 S

UBADDRESS

0DH

Table 50 Chrominance hue control; 0DH[7:0]

GAIN

CONTROL BITS D7 TO D0

DCON7

DCON6

DCON5

DCON4

DCON3

DCON2

DCON1

DCON0

1.984 (maximum)

1.063 (ITU level)

1.0

0 (luminance off)

1 (inverse luminance)

2 (inverse luminance)

GAIN

CONTROL BITS D7 TO D0

DSAT7

DSAT6

DSAT5

DSAT4

DSAT3

DSAT2

DSAT1

DSAT0

1.984 (maximum)

1.0 (ITU level)

0 (colour off)

1 (inverse chrominance)

2 (inverse chrominance)

HUE PHASE (DEG)

CONTROL BITS D7 TO D0

HUEC7

HUEC6

HUEC5

HUEC4

HUEC3

HUEC2

HUEC1

HUEC0

+178.6...

...0...

...

180

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

15.2.15 S

UBADDRESS

0EH

Table 51 Chrominance control 1; 0EH[7:0]

15.2.16 S

UBADDRESS

0FH

Table 52 Chrominance gain control; 0FH[7:0]

BIT

DESCRIPTION

SYMBOL

VALUE

FUNCTION

50 Hz/625 LINES

60 Hz/525 LINES

clear DTO

CSTDO

disabled

Every time CDTO is set, the internal subcarrier DTO
phase is reset to 0

�

and the RTCO output generates a

logic 0 at time slot 68 (see external document

"RTC

Functional Description", available on request). So an
identical subcarrier phase can be generated by an
external device (e.g. an encoder).

D[6:4] colour standard selection

CSTD[2:0]

000

PAL BGDHI (4.43 MHz)

NTSC M (3.58 MHz)

001

NTSC 4.43 (50 Hz)

PAL 4.43 (60 Hz)

010

Combination-PAL N
(3.58 MHz)

NTSC 4.43 (60 Hz)

011

NTSC N (3.58 MHz)

PAL M (3.58 MHz)

100

reserved

NTSC-Japan (3.58 MHz)

101

SECAM

reserved

110

reserved; do not use

111

reserved; do not use

disable chrominance
vertical filter and PAL
phase error correction

DCVF

chrominance vertical filter and PAL phase error
correction on (during active video lines)

chrominance vertical filter and PAL phase error
correction permanently off

fast colour time constant

FCTC

nominal time constant

fast time constant for special applications

adaptive chrominance
comb filter

CCOMB

disabled

active

BIT

DESCRIPTION

SYMBOL

VALUE

FUNCTION

automatic chrominance
gain control

ACGC

programmable gain via CGAIN6 to CGAIN0; need to be
set for SECAM standard

D[6:0] chrominance gain value

(if ACGC is set to logic 1)

CGAIN[6:0] 000 0000 minimum gain (0.5)

010 0100 nominal gain (1.125)

111 1111 maximum gain (7.5)

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

15.2.17 S

UBADDRESS

10H

Table 53 Chrominance control 2; 10H[7:0]

15.2.18 S

UBADDRESS

11H

Table 54 Mode/delay control; 11H[7:0]

BIT

DESCRIPTION

SYMBOL

VALUE

FUNCTION

D[7:6] fine offset adjustment B-Y component

OFFU[1:0]

0 LSB

LSB

D[5:4] fine offset adjustment R-Y component

OFFV[1:0]

0 LSB

LSB

chrominance bandwidth; see Figs 10 and 11

CHBW

small

wide

D[2:0] combined luminance/chrominance bandwidth

adjustment; see Figs 10 to 16

LCBW[2:0]

000

smallest chrominance
bandwidth/largest luminance
bandwidth

...

... to ...

111

largest chrominance
bandwidth/smallest luminance
bandwidth

BIT

DESCRIPTION

SYMBOL

VALUE

FUNCTION

colour on

COLO

automatic colour killer enabled

colour forced on

polarity of RTS1 output signal

RTP1

non inverted

inverted

D[5:4] fine position of HS (steps in 2/LLC)

HDEL[1:0]

polarity of RTS0 output signal

RTP0

non inverted

inverted

D[2:0] luminance delay compensation (steps in 2/LLC)

YDEL[2:0]

100

4...

000

...0...

011

...3

2000 Mar 15

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

15.2.19 S

UBADDRESS

12H

Table 55 RT signal control: RTS0 output; 12H[3:0]

The polarity of any signal on RTS0 can be inverted via RTP0[11H[3]].

Note

1. Function of HL is selectable via HLSEL[13H[3]]:

a) HLSEL = 0: HL is standard horizontal lock indicator.

b) HLSEL = 1: HL is fast horizontal lock indicator (use is not recommended for sources with unstable timebase e.g.

VCRs).

RTS0 OUTPUT

RTSE03 RTSE02 RTSE01 RTSE00

3-state

Constant LOW

CREF (13.5 MHz toggling pulse; see Fig.23)

CREF2 (6.75 MHz toggling pulse; see Fig.23)

HL; horizontal lock indicator (note 1):

HL = 0: unlocked

HL = 1: locked

VL; vertical and horizontal lock:

VL = 0: unlocked

VL = 1: locked

DL, vertical and horizontal lock and colour detected:

DL = 0: unlocked

DL = 1: locked

Reserved

HREF, horizontal reference signal; indicates 720 pixels valid data on the
expansion port. The positive slope marks the beginning of a new active
line. HREF is also generated during the vertical blanking interval
(see Fig.23).

HS:

programmable width in LLC8 steps via HSB[7:0]06H[7:0] and
HSS[7:0]07H[7:0]

fine position adjustment in LLC2 steps via HDEL[1:0]11H[5:4]
(see Fig.23)

HQ; HREF gated with VGATE

Reserved

V123; vertical sync (see vertical timing diagrams Figs 21 and 22)

VGATE; programmable via VSTA[8:0]17H[0]15H[7:0],
VSTO[8:0]17H[1]16H[7:0] and VGPS[17H[2]]

LSBs of the 9-bit ADC's

FID; position programmable via STA[8:0]17H[0]15H[7:0]; see vertical timing
diagrams Figs 21 and 22

2000 Mar 15

100

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

Table 56 RT signal control: RTS1 output; 12H[7:4]
The polarity of any signal on RTS1 can be inverted via RTP1[11H[6]].

Note

1. Function of HL is selectable via HLSEL[13H[3]]:

a) HLSEL = 0: HL is standard horizontal lock indicator.

b) HLSEL = 1: HL is fast horizontal lock indicator (use is not recommended for sources with unstable timebase e.g.

VCRs).

RTS1 OUTPUT

RTSE13 RTSE12 RTSE11 RTSE10

3-state

Constant LOW

CREF (13.5 MHz toggling pulse; see Fig.23)

CREF2 (6.75 MHz toggling pulse; see Fig.23)

HL; horizontal lock indicator (note 1):

HL = 0: unlocked

HL = 1: locked

VL; vertical and horizontal lock:

VL = 0: unlocked

VL = 1: locked

DL, vertical and horizontal lock and colour detected:

DL = 0: unlocked

DL = 1: locked

Reserved

HS:

programmable width in LLC8 steps via HSB[7:0]06H[7:0] and
HSS[7:0]07H[7:0]

fine position adjustment in LLC2 steps via HDEL[1:0]11H[5:4]
(see Fig.23)

HQ; HREF gated with VGATE

Reserved

V123; vertical sync (see vertical timing diagrams Figs 21 and 22)

VGATE; programmable via VSTA[8:0]17H[0]15H[7:0],
VSTO[8:0]17H[1]16H[7:0] and VGPS[17H[2]]

LSBs of the 9-bit ADC's

FID; position programmable via STA[8:0]17H[0]15H[7:0]; see vertical timing
diagrams Figs 21 and 22

2000 Mar 15

101

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

15.2.20 S

UBADDRESS

13H

Table 57 RT/X-port output control; 13H[7:0]

BIT

DESCRIPTION

SYMBOL

VALUE

FUNCTION

RTCO output enable

RTCE

3-state

enabled

X-port XRH output
selection

XRHS

HREF (see Fig.23)

HS:

programmable width in LLC8 steps via HSB[7:0]06H[7:0]
and HSS[7:0]07H[7:0]

fine position adjustment in LLC2 steps via
HDEL[1:0]11H[5:4] (see Fig.23)

D[5:4] X-port XRV output

selection

XRVS[1:0]

V123 (see Figs 21 and 22)

ITU 656 related field ID (see Figs 21 and 22)

inverted V123

inverted ITU 656 related field ID

horizontal lock indicator
selection

HLSEL

copy of inverted HLCK status bit (default)

fast horizontal lock indicator (for special applications only)

D[2:0] XPD7 to XPD0 (port

output format selection);
see Section 9.4

OFTS[2:0]

000

ITU 656

001

ITU 656 like format with modified field blanking according to
VGATE position (programmable via VSTA8 to VSTA0,
VSTO8 to VSTO0 and VGPS, subaddresses 15H,
16H and 17H)

010

YUV 4 : 2 : 2 8-bit format (no SAV/EAV codes inserted)

011

reserved

100

multiplexed AD2/AD1 bypass (bits 8 to 1) dependent on
mode settings; if both ADCs are selected AD2 is output at
CREF = 1 and AD1 is output at CREF = 0

101

multiplexed AD2/AD1 bypass (bits 7 to 0) dependent on
mode settings; if both ADCs are selected AD2 is output at
CREF = 1 and AD1 is output at CREF = 0

110

reserved

111

multiplexed ADC MSB/LSB bypass dependent on mode
settings; only one ADC should be selected at a time;
ADx8 to ADx1 are outputs at CREF = 1 and ADx7 to ADx0
are outputs at CREF = 0

2000

Mar

103

Philips Semiconductors

Preliminar

y specification

AL/NTSC/SECAM video decoder with adaptiv

e P
AL/NTSC

comb filter

, VBI-data slicer and high perf

mance scaler

SAA7114H

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15.2.22

UBADDRESS

15H

Table 59 VGATE pulse; FID polarity change; 17H[0] and 15H[7:0]
Start of VGATE pulse (LOW-to-HIGH transition) and polarity change of FID pulse, VGPS = 0; see Figs 21 and 22.

FIELD

FRAME LINE

COUNTING

DECIMAL

VALUE

MSB

17H[0]

CONTROL BITS D7 TO D0

VSTA8

VSTA7

VSTA6

VSTA5

VSTA4

VSTA3

VSTA2

VSTA1

VSTA0

50 Hz

1st

312

2nd

314

1st

0...

2nd

315

1st

312

...310

2nd

625

60 Hz

1st

262

2nd

267

1st

0...

2nd

268

1st

265

...260

2nd

2000

Mar

104

Philips Semiconductors

Preliminar

y specification

AL/NTSC/SECAM video decoder with adaptiv

e P
AL/NTSC

comb filter

, VBI-data slicer and high perf

mance scaler

SAA7114H

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15.2.23

UBADDRESS

16H

Table 60 VGATE stop; 17H[1] and 16H[7:0]
Stop of VGATE pulse (HIGH-to-LOW transition), VGPS = 0; see Figs 21 and 22.

FIELD

FRAME LINE

COUNTING

DECIMAL

VALUE

MSB

17H[1]

CONTROL BITS D7 TO D0

VSTO8

VSTO7

VSTO6

VSTO5

VSTO4

VSTO3

VSTO2

VSTO1

VSTO0

50 Hz

1st

312

2nd

314

1st

0...

2nd

315

1st

312

...310

2nd

625

60 Hz

1st

262

2nd

267

1st

0...

2nd

268

1st

265

...260

2nd

2000 Mar 15

105

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

15.2.24 S

UBADDRESS

17H

Table 61 Miscellaneous/VGATE MSBs; 17H[7:6] and 17H[2:0]

15.2.25 S

UBADDRESS

18H

Table 62 Raw data gain control; RAWG[7:0]18H[7:0]
See Fig.18.

15.2.26 S

UBADDRESS

19H

Table 63 Raw data offset control; RAWO[7:0]19H[7:0]
See Fig.18.

BIT

DESCRIPTION

SYMBOL VALUE

FUNCTION

LLC output enable

LLCE

enable

3-state

LLC2 output enable

LLC2E

enable

3-state

alternative VGATE
position

VGPS

VGATE position according to Tables 59 and 60

VGATE occurs one line earlier during field 2

MSB VGATE stop

VSTO8

see Table 60

MSB VGATE start

VSTA8

see Table 59

GAIN

CONTROL BITS D7 TO D0

RAWG7

RAWG6

RAWG5

RAWG4

RAWG3

RAWG2

RAWG1

RAWG0

255 (double amplitude)

128 (nominal level)

0 (off)

OFFSET

CONTROL BITS D7 TO D0

RAWO7

RAWO6

RAWO5

RAWO4

RAWO3

RAWO2

RAWO1

RAWO0

128 LSB

0 LSB

+128 LSB

2000 Mar 15

106

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

15.2.27 S

UBADDRESS

1FH (

READ ONLY REGISTER

)

Table 64 Status byte video decoder; 1FH[7:0]

15.3

Programming register audio clock generation

See equations in Section 8.6 and examples in Tables 21 and 22.

15.3.1

UBADDRESSES

30H

32H

Table 65 Audio master clock (AMCLK) cycles per field

BIT

DESCRIPTION

C-BUS

CONTROL

BIT

OLDSB

14H[2]

VALUE

FUNCTION

status bit for interlace detection

INTL

non-interlaced

interlaced

status bit for horizontal and vertical loop

HLVLN

both loops locked

unlocked

status bit for locked horizontal frequency

HLCK

locked

unlocked

identification bit for detected field frequency

FIDT

50 Hz

60 Hz

gain value for active luminance channel is limited;
maximum (top)

GLIMT

not active

active

gain value for active luminance channel is limited;
minimum (bottom)

GLIMB

not active

active

white peak loop is activated

WIPA

not active

active

copy protected source detected according to
macrovision version up to 7.01

COPRO

not active

active

slow time constant active in WIPA mode

SLTCA

not active

active

ready for capture (all internal loops locked)

RDCAP

not active

active

colour signal in accordance with selected standard has
been detected

CODE

not active

active

SUBADDRESS

CONTROL BITS D7 TO D0

30H

ACPF7

ACPF6

ACPF5

ACPF4

ACPF3

ACPF2

ACPF1

ACPF0

31H

ACPF15

ACPF14

ACPF13

ACPF12

ACPF11

ACPF10

ACPF9

ACPF8

32H

ACPF17

ACPF16

2000 Mar 15

107

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

15.3.2

UBADDRESSES

34H

36H

Table 66 Audio master clock (AMCLK) nominal increment

15.3.3

UBADDRESS

38H

Table 67 Clock ratio AMCLK (audio master clock) to ASCLK (serial bit clock)

15.3.4

UBADDRESS

39H

Table 68 Clock ratio ASCLK (serial bit clock) to ALRCLK (channel select clock)

15.3.5

UBADDRESS

3AH

Table 69 Audio clock control; 3AH[3:0]

15.4

Programming register VBI-data slicer

15.4.1

UBADDRESS

40H

Table 70 Slicer control 1; 40H[6:4]

SUBADDRESS

CONTROL BITS D7 TO D0

34H

ACNI7

ACNI6

ACNI5

ACNI4

ACNI3

ACNI2

ACNI1

ACNI0

35H

ACNI15

ACNI14

ACNI13

ACNI12

ACNI11

ACNI10

ACNI9

ACNI8

36H

ACNI21

ACNI20

ACNI19

ACNI18

ACNI17

ACNI16

SUBADDRESS

CONTROL BITS D7 TO D0

38H

SDIV5

SDIV4

SDIV3

SDIV2

SDIV1

SDIV0

SUBADDRESS

CONTROL BITS D7 TO D0

39H

LRDIV5

LRDIV4

LRDIV3

LRDIV2

LRDIV1

LRDIV0

BIT

DESCRIPTION

SYMBOL VALUE

FUNCTION

audio PLL modes

APLL

PLL active, AMCLK is field-locked

PLL open, AMCLK is free-running

audio master clock
vertical reference

AMVR

vertical reference pulse is taken from internal decoder

vertical reference is taken from XRV input (expansion port)

ALRCLK phase

LRPH

ALRCLK edges triggered by falling edges of ASCLK

ALRCLK edges triggered by rising edges of ASCLK

ASCLK phase

SCPH

ASCLK edges triggered by falling edges of AMCLK

ASCLK edges triggered by rising edges of AMCLK

BIT

DESCRIPTION

SYMBOL VALUE

FUNCTION

Hamming check

HAM_N

Hamming check for 2 bytes after framing code,
dependent on data type (default)

no Hamming check

framing code error

FCE

one framing code error allowed

no framing code errors allowed

amplitude searching

HUNT_N

amplitude searching active (default)

amplitude searching stopped

2000 Mar 15

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Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

15.4.2

UBADDRESSES

41H

57H

Table 71 Line control register; LCR2 to LCR24 (41H to 57H)

See Sections 8.2 and 8.4.

15.4.3

UBADDRESS

58H

Table 72 Programmable framing code; slicer set 58H[7:0]

According to Tables 14 and 71.

15.4.4

UBADDRESS

59H

Table 73 Horizontal offset for slicer; slicer set 59H and 5BH

NAME

DESCRIPTION

FRAMING CODE

D[7:4]

(41H TO 57H)

D[3:0]

(41H TO 57H)

DT[3:0]62H[3:0]

(FIELD 1)

DT[3:0]62H[3:0]

(FIELD 2)

WST625

teletext EuroWST, CCST

27H

0000

CC625

European closed caption

001

0001

VPS

video programming service

9951H

0010

WSS

wide screen signalling bits

1E3C1FH

0011

WST525

US teletext (WST)

27H

0100

CC525

US closed caption (line 21)

001

0101

Test line

video component signal, VBI region

0110

Intercast

raw data

0111

General text teletext

programmable

1000

VITC625

VITC/EBU time codes (Europe)

programmable

1001

VITC/SMPTE time codes (USA)

programmable

1010

Reserved

reserved

1011

NABTS

US NABTS

1100

Japtext

MOJI (Japanese)

programmable (A7H)

1101

JFS

Japanese format switch (L20/22)

programmable

1110

Active video video component signal, active video

region (default)

1111

FRAMING CODE FOR PROGRAMMABLE DATA TYPES

CONTROL BITS D7 TO D0

Default value

FC[7:0] = 40H

HORIZONTAL OFFSET

CONTROL BITS D[2:0]5BH[2:0]

CONTROL BITS D[7:0]59H[7:0]

Recommended value

HOFF[10:8] = 3H

HOFF[7:0] = 47H

2000 Mar 15

109

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

15.4.5

UBADDRESS

5AH

Table 74 Vertical offset for slicer; slicer set 5AH and 5BH

15.4.6

UBADDRESS

5BH

Table 75 Field offset, and MSBs for horizontal and vertical offsets; slicer set 5BH[7:6]
See Sections 15.4.4 and 15.4.5 for HOFF[10:8]5BH[2:0] and VOFF8[5BH[4]].

15.4.7

UBADDRESS

5DH

Table 76 Header and data identification (DID; ITU 656) code control; slicer set 5DH[7:0]

15.4.8

UBADDRESS

5EH

Table 77 Sliced data identification (SDID) code; slicer set 5EH[5:0]

VERTICAL OFFSET

CONTROL BIT D[4]5BH[4]

CONTROL BITS D[7:0]5AH[7:0]

VOFF8

VOFF[7:0]

Minimum value 0

00H

Maximum value 312

38H

Value for 50 Hz 625 lines input

03H

Value for 60 Hz 525 lines input

06H

BIT

DESCRIPTION SYMBOL VALUE

FUNCTION

field offset

FOFF

no modification of internal field indicator (default for 50 Hz 625 lines
input sources)

invert field indicator (default for 60 Hz 525 lines input sources)

recode

RECODE

let data unchanged (default)

convert 00H and FFH data bytes into 03H and FCH

BIT

DESCRIPTION

SYMBOL

VALUE

FUNCTION

field ID and V-blank selection
for text output (F and V
reference selection)

FVREF

F and V output of slicer is LCR table dependent

F and V output is taken from decoder real time signals
EVEN_CCIR and VBLNK_CCIR

D[5:0] default; DID[5:0] = 00H

DID[5:0]

00 0000 ANC header framing; see Fig.30 and Table 20

special cases of DID
programming

11 1110 DID[5:0] = 3EH SAV/EAV framing, with FVREF = 1

11 1111 DID[5:0] = 3FH SAV/EAV framing, with FVREF = 0

BIT

DESCRIPTION

SYMBOL VALUE

FUNCTION

D[5:0] SDID codes

SDID[5:0]

00H

default

2000 Mar 15

110

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

15.4.9

UBADDRESS

60H (

READ

ONLY REGISTER

)

Table 78 Slicer status byte 0; 60H[6:2]

15.4.10 S

UBADDRESSES

61H

AND

62H (

READ

ONLY REGISTERS

)

Table 79 Slicer status byte 1; 61H[5:0] and slicer status byte 2; 62H[7:0]

15.5

Programming register interfaces and scaler part

15.5.1

UBADDRESS

80H

Table 80 Global control 1; global set 80H[3:0]
X = don't care.

Note

1. Although the ICLKO I/O is independent of ICKS2 and ICKS3, this selection can only be used if ICKS2 = 1.

BIT

DESCRIPTION

SYMBOL VALUE

FUNCTION

framing code valid

FC8V

no framing code (0 error) in the last frame detected

framing code with 0 error detected

framing code valid

FC7V

no framing code (1 error) in the last frame detected

framing code with 1 error detected

VPS valid

VPSV

no VPS in the last frame

VPS detected

PALplus valid

PPV

no PALplus in the last frame

PALplus detected

close caption valid

CCV

no closed caption in the last frame

closed caption detected

SUBADDRESS

BIT

SYMBOL

DESCRIPTION

61H

F21_N

field ID as seen by the VBI slicer; for field 1: D5 = 0

D[4:0]

LN[8:4]

line number

62H

D[7:4]

LN[3:0]

D[3:0]

DT[3:0]

data type; according to Table 14

I-PORT AND SCALER BACK-END CLOCK SELECTION

CONTROL BITS D3 TO D0

ICKS3

ICKS2

ICKS1

ICKS0

ICLK output and back-end clock is line-locked clock LLC from decoder

ICLK output and back-end clock is XCLK from X-port

ICLK output is LLC and back-end clock is LLC2 clock

(1)

Back-end clock is the ICLK input

IDQ pin carries the data qualifier

IDQ pin carries a gated back-end clock (IDQ AND CLK)

IDQ generation only for valid data

IDQ qualifies valid data inside the scaling region and all data outside the scaling
region

2000 Mar 15

111

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

Table 81 Global control 1; global set 80H[6:4]

SWRST moved to subaddress 88H[5]; X = don't care.

15.5.2

UBADDRESSES

83H

87H

Table 82 X-port I/O enable and output clock phase control; global set 83H[5:4]

Table 83 X-port I/O enable and output clock phase control; global set 83H[2:0]

X = don't care.

TASK ENABLE CONTROL

CONTROL BITS D6 TO D4

SMOD

TEB

TEA

Task of register set A is disabled

Task of register set A is enabled

Task of register set B is disabled

Task of register set B is enabled

The scaler window defines the F and V timing of the scaler output

VBI-data slicer defines the F and V timing of the scaler output

OUTPUT CLOCK PHASE CONTROL

CONTROL BITS D5 AND D4

XPCK1

XPCK0

XCLK default output phase, recommended value

XCLK output inverted

XCLK phase shifted by about 3 ns

XCLK output inverted and shifted by about 3 ns

X-PORT I/O ENABLE

CONTROL BITS D2 TO D0

XRQT

XPE1

XPE0

X-port output is disabled by software

X-port output is enabled by software

X-port output is enabled by pin XTRI at logic 0

X-port output is enabled by pin XTRI at logic 1

XRDY output signal is A/B task flag from event handler (A = 1)

XRDY output signal is ready signal from scaler path (XRDY = 1 means SAA7114H is
ready to receive data)

2000 Mar 15

112

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

Table 84 I-port output signal definitions; global set 84H[3:0]
X = don't care.

Table 85 I-port signal definitions; global set 84H[5:4] and 86H[4]

I-PORT OUTPUT SIGNAL DEFINITIONS

CONTROL BITS D3 TO D0

IDV1

IDV0

IDH1

IDH0

IGPH is a H-gate signal, framing the scaler output

IGPH is an extended H-gate (framing H-gate during scaler output and scaler
input H-reference outside the scaler window)

IGPH is a horizontal trigger pulse, on active going edge of H-gate

IGPH is a horizontal trigger pulse, on active going edge of extended H-gate

IGPV is a V-gate signal, framing scaled output lines

IGPV is the reference signal from scaler input

IGPV is a vertical trigger pulse, derived from V-gate

IGPV is a vertical trigger pulse derived from input V-reference

I-PORT SIGNAL DEFINITIONS

CONTROL BITS

86H[4]

84H[5:4]

IDG12

IDG11

IDG10

IGP1 is output field ID, as defined by OFIDC[90H[6]]

IGP1 is A/B task flag, as defined by CONLH[90H[7]]

IGP1 is sliced data flag, framing the sliced VBI-data at the I-port

IGP1 is set to logic 0 (default polarity)

IGP1 is the output FIFO almost filled flag

IGP1 is the output FIFO overflow flag

IGP1 is the output FIFO almost full flag, level to be programmed in
subaddress 86H

IGP1 is the output FIFO almost empty flag, level to be programmed in
subaddress 86H

2000 Mar 15

113

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

Table 86 I-port signal definitions; global set 84H[7:6] and 86H[5]

Table 87 I-port reference signal polarities; global set 85H[4:0]
X = don't care.

Table 88 X-port signal definitions text slicer; global set 85H[7:5]

X = don't care.

I-PORT SIGNAL DEFINITIONS

CONTROL BITS

86H[5]

84H[7:6]

IDG02

IDG01

IDG00

IGP0 is output field ID, as defined by OFIDC[90H[6]]

IGP0 is A/B task flag, as defined by CONLH[90H[7]]

IGP0 is sliced data flag, framing the sliced VBI-data at the I-port

IGP0 is set to logic 0 (default polarity)

IGP0 is the output FIFO almost filled flag

IGP0 is the output FIFO overflow flag

IGP0 is the output FIFO almost full flag, level to be programmed in subaddress
86H

IGP0 is the output FIFO almost empty flag, level to be programmed in subaddress
86H

I-PORT REFERENCE SIGNAL POLARITIES

CONTROL BITS D4 TO D0

IGP0P

IGP1P

IGVP

IGHP

IDQP

IDQ at default polarity (1 = active)

IDQ is inverted

IGPH at default polarity (1 = active)

IGPH is inverted

IGPV at default polarity (1 = active)

IGPV is inverted

IGP1 at default polarity

IGP1 is inverted

IGP0 at default polarity

IGP0 is inverted

X-PORT SIGNAL DEFINITIONS TEXT SLICER

CONTROL BITS D7 TO D5

ISWP1

ISWP0

ILLV

Video data limited to range 1 to 254

Video data limited to range 8 to 247

Dword byte swap, influences serial output timing
D0 D1 D2 D3

FF 00 00 SAV C

0 Y0 C

0 Y1

D1 D0 D3 D2

00 FF SAV 00 Y0 C

0 Y1 C

D2 D3 D0 D1

00 SAV FF 00 C

0 Y1 C

0 Y0

D3 D2 D1 D0

SAV 00 00 FF Y1 C

0 Y0 C

2000 Mar 15

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Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

Table 89 I-port FIFO flag control and arbitration; global set 86H[3:0]
X = don't care.

Table 90 I-port FIFO flag control and arbitration; global set 86H[7:4]

X = don't care.

I-PORT FIFO FLAG CONTROL AND ARBITRATION

CONTROL BITS D3 TO D0

FFL1

FFL0

FEL1

FEL0

FAE FIFO flag almost empty level

<16 Dwords

<8 Dwords

<4 Dwords

0 Dwords

FAF FIFO flag almost full level

16 Dwords

24 Dwords

28 Dwords

32 Dwords

FUNCTION

CONTROL BITS D7 TO D4

VITX1

VITX0

IDG02

IDG12

See subaddress 84H: IDG11 and IDG10

See subaddress 84H: IDG01 and IDG00

I-port signal definitions

I-port data output inhibited

Only video data are transferred

Only text data are transferred (no EAV, SAV will occur)

Text and video data are transferred, text has priority

2000 Mar 15

115

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

Table 91 I-port I/O enable, output clock and gated clock phase control; global set 87H[7:4]

Notes

1. X = don't care.

2. IPCK3 and IPCK2 only affects the gated clock (subaddress 80H, bit ICKS2 = 1).

Table 92 I-port I/O enable, output clock and gated clock phase control; global set 87H[1:0]

15.5.3

UBADDRESS

88H

Table 93 Power save control; global set 88H[3] and 88H[1:0]
X = don't care.

OUTPUT CLOCK AND GATED CLOCK PHASE CONTROL

CONTROL BITS D7 TO D4

(1)

IPCK3

(2)

IPCK2

(2)

IPCK1 IPCK0

ICLK default output phase

ICLK phase shifted by

clock cycle

recommended for ICKS1 = 1 and

ICKS0 = 0 (subaddress 80H)

ICLK phase shifted by about 3 ns

ICLK phase shifted by

clock cycle + about 3 ns

alternatively to setting `01'

IDQ = gated clock default output phase

IDQ = gated clock phase shifted by

clock cycle

recommended for gated

clock output

IDQ = gated clock phase shifted by about 3 ns

IDQ = gated clock phase shifted by

clock cycle + about 3 ns

alternatively

to setting `01'

I-PORT I/O ENABLE

CONTROL BITS D1 AND D0

IPE1

IPE0

I-port output is disabled by software

I-port output is enabled by software

I-port output is enabled by pin ITRI at logic 0

I-port output is enabled by pin ITRI at logic 1

POWER SAVE CONTROL

CONTROL BITS

88H[3]

88H[1:0]

SLM3

SLM1

SLM0

Decoder and VBI slicer are in operational mode

Decoder and VBI slicer are in power-down mode; scaler only operates, if scaler
input and ICLK source is the X-port (refer to subaddresses 80H and 91H/C1H)

Scaler is in operational mode

Scaler is in power-down mode; scaler in power-down stops I-port output

Audio clock generation active

Audio clock generation in power-down and output disabled

2000 Mar 15

116

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

Table 94 Power save control; global set 88H[7:4]

Notes

1. X = don't care.

2. Bit SWRST is now located here.

15.5.4

UBADDRESS

8FH (

READ

ONLY REGISTER

)

Table 95 Status information scaler part; 8FH[7:0]

Note

1. Status information is unsynchronized and shows the actual status at the time of I

C-bus read.

POWER SAVE CONTROL

CONTROL BITS D7 TO D4

(1)

CH4EN

CH2EN

SWRST

(2)

DPROG

DPROG = 0 after reset

DPROG = 1 can be used to assign that the device has been
programmed; this bit can be monitored in the scalers status byte,
bit PRDON; if DPROG was set to logic 1 and PRDON status bit
shows a logic 0 a power- or start-up fail has occurred

Scaler path is reset to it's idle state, software reset

Scaler is switched back to operation

AD1x analog channel is in power-down mode

AD1x analog channel is active

AD2x analog channel is in power-down mode

AD2x analog channel is active

BIT

I2C-BUS

STATUS BIT

FUNCTION

(1)

XTRI

status on input pin XTRI, if not used for 3-state control, usable as hardware flag for software use

ITRI

status on input pin ITRI, if not used for 3-state control, usable as hardware flag for software use

FFIL

status of the internal `FIFO almost filled' flag

FFOV

status of the internal `FIFO overflow' flag

PRDON

copy of bit DPROG, can be used to detect power-up and start-up fails

ERR_OF

error flag of scalers output formatter, normally set, if the output processing needs to be
interrupted, due to input/output data rate conflicts, e.g. if output data rate is much too low and all
internal FIFO capacity used

FIDSCI

status of the field sequence ID at the scalers input

FIDSCO

status of the field sequence ID at the scalers output, scaler processing dependent

2000 Mar 15

117

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

15.5.5

UBADDRESSES

90H

AND

C0H

Table 96 Task handling control; register set A (90H[2:0]) and B (C0H[2:0])
X = don't care.

Table 97 Task handling control; register set A (90H[5:3]) and B (C0H[5:3])

Table 98 Task handling control; register set A (90H[7:6]) and B (C0H[7:6])
X = don't care.

EVENT HANDLER CONTROL

CONTROL BITS D2 TO D0

RPTSK

STRC1

STRC0

Event handler triggers immediately after finishing a task

Event handler triggers with next V-sync

Event handler triggers with field ID = 0

Event handler triggers with field ID = 1

If active task is finished, handling is taken over by the next task

Active task is repeated once, before handling is taken over by the next task

EVENT HANDLER CONTROL

CONTROL BITS D5 TO D3

FSKP2

FSKP1

FSKP0

Active task is carried out directly

1 field is skipped before active task is carried out

... fields are skipped before active task is carried out

...

6 fields are skipped before active task is carried out

7 fields are skipped before active task is carried out

EVENT HANDLER CONTROL

CONTROL BITS D7 AND D6

CONLH

OFIDC

Output field ID is field ID from scaler input

Output field ID is task status flag, which changes every time an selected task
is activated (not synchronized to input field ID)

Scaler SAV/EAV byte bit D7 and task flag = 1, default

Scaler SAV/EAV byte bit D7 and task flag = 0

2000 Mar 15

118

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

15.5.6

UBADDRESSES

91H

93H

Table 99 X-port formats and configuration; register set A (91H[2:0]) and B (C1H[2:0])

Notes

1. X = don't care.

2. FSC2 and FSC1 only to be used, if X-port input source don't provide chroma information for every input line. X-port

input stream must contain dummy chroma bytes.

Table 100 X-port formats and configuration; register set A (91H[7:3]) and B (C1H[7:3])
X = don't care.

SCALER INPUT FORMAT AND CONFIGURATION FORMAT

CONTROL

CONTROL BITS D2 TO D0

(1)

FSC2

(2)

FSC1

(2)

FSC0

Input is YUV 4 : 2 : 2 like sampling scheme

Input is YUV 4 : 1 : 1 like sampling scheme

Chroma is provided every line, default

Chroma is provided every 2nd line

Chroma is provided every 3rd line

Chroma is provided every 4th line

SCALER INPUT FORMAT AND CONFIGURATION SOURCE

SELECTION

CONTROL BITS D7 TO D3

CONLV

HLDFV

SCSRC1 SCSRC0

SCRQE

Only if XRQT[83H[2]] = 1: scaler input source reacts on
SAA7114H request

Scaler input source is a continuous data stream, which cannot
be interrupted (must be logic 1, if SAA7114H decoder part is
source of scaler or XRQT[83H[2]] = 0)

Scaler input source is data from decoder, data type is
provided according to Table 14

Scaler input source is YUV data from X-port

Scaler input source is raw digital CVBS from selected analog
channel, for backward compatibility only, further use is not
recommended

Scaler input source is raw digital CVBS (or 16-bit Y + UV, if no
16-bit output are active) from X-port

SAV/EAV code bits D6 and D5 (F and V) may change
between SAV and EAV

SAV/EAV code bits D6 and D5 (F and V) are synchronized to
scalers output line start

SAV/EAV code bit D5 (V) and V-gate on pin IGPV as
generated by the internal processing, see Fig.36

SAV/EAV code bit D5 (V) and V-gate are inverted

2000 Mar 15

119

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

Table 101 X-port input reference signal definitions; register set A (92H[3:0]) and B (C2H[3:0])
X = don't care.

Table 102 X-port input reference signal definitions; register set A (92H[7:4]) and B (C2H[7:4])
X = don't care.

X-PORT INPUT REFERENCE SIGNAL DEFINITIONS

CONTROL BITS D3 TO D0

XCODE

XDH

XDQ

XCKS

XCLK input clock and XDQ input qualifier are needed

Data rate is defined by XCLK only, no XDQ signal used

Data are qualified at XDQ input at logic 1

Data are qualified at XDQ input at logic 0

Rising edge of XRH input is horizontal reference

Falling edge of XRH input is horizontal reference

Reference signals are taken from XRH and XRV

Reference signals are decoded from EAV and SAV

SCALER INPUT REFERENCE SIGNAL DEFINITIONS

CONTROL BITS D7 TO D4

XFDV

XFDH

XDV1

XDV0

Rising edge of XRV input and decoder V123 is vertical reference

Falling edge of XRV input and decoder V123 is vertical reference

XRV is a V-sync or V-gate signal

XRV is a frame sync, V-pulses are generated internally on both edges of
FS input

X-port field ID is state of XRH at reference edge on XRV (defined by
XFDV)

Field ID (decoder and X-port field ID) is inverted

Reference edge for field detection is falling edge of XRV

Reference edge for field detection is rising edge of XRV

2000 Mar 15

120

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

Table 103 I-port output format and configuration; register set A (93H[4:0]) and B (C3H[4:0])
X = don't care.

Table 104 I-port output format and configuration; register set A (93H[7:5]) and B (C3H[7:5])
X = don't care.

I-PORT OUTPUT FORMAT AND CONFIGURATION

CONTROL BITS D4 TO D0

FOI1

FOI0

FSI2

FSI1

FSI0

4 : 2 : 2 Dword formatting

4 : 1 : 1 Dword formatting

4 : 2 : 0, only every 2nd line Y + UV output, in between Y only
output

4 : 1 : 0, only every 4th line Y + UV output, in between Y only
output

Y only

Not defined

No leading Y only line, before 1st Y + UV line is output

1 leading Y only line, before 1st Y + UV line is output

2 leading Y only lines, before 1st Y + UV line is output

3 leading Y only lines, before 1st Y + UV line is output

I-PORT OUTPUT FORMAT AND CONFIGURATION

CONTROL BITS D7 TO D5

ICODE

I8_16

FYSK

All lines will be output

Skip the number of leading Y only lines, as defined by FOI1 and FOI0

Dwords are transferred byte wise, see subaddress 85H bits ISWP1 and ISWP0

Dwords are transferred 16-bit word wise via IPD and HPD, see subaddress 85H bits
ISWP1 and ISWP0

No ITU 656 like SAV/EAV codes are available

ITU 656 like SAV/EAV codes are inserted in the output data stream, framed by a
qualifier

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PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

15.5.7

UBADDRESSES

94H

9BH

Table 105 Horizontal input window start; register set A (94H[7:0]; 95H[3:0]) and B (C4H[7:0]; C5H[3:0])

Note

1. Reference for counting are luminance samples.

Table 106 Horizontal input window length; register set A (96H[7:0]; 97H[3:0]) and B (C6H[7:0]; C7H[3:0])

Note

1. Reference for counting are luminance samples.

Table 107 Vertical input window start; register set A (98H[7:0]; 99H[3:0]) and B (C8H[7:0]; C9H[3:0])

Note

1. For trigger condition: STRC[1:0]90H[1:0] = 00; YO + YS > (number of input lines per field

2), will result in field

dropping. Other trigger conditions: YO > (number of input lines per field

2), will result in field dropping.

HORIZONTAL INPUT

ACQUISITION WINDOW
DEFINITION OFFSET IN

X (HORIZONTAL) DIRECTION

(1)

CONTROL BITS

A(95H[3:0]) B(C5H[3:0])

A(94H[7:0]) B(C4H[7:0])

XO11 XO10 XO9 XO8 XO7 XO6 XO5 XO4 XO3 XO2 XO1 XO0

A minimum of `2' should be kept, due
to a line counting mismatch

Odd offsets are changing the
UV sequence in the output stream to
VU sequence

Maximum possible pixel
offset = 4095

HORIZONTAL INPUT

ACQUISITION WINDOW

DEFINITION INPUT WINDOW

LENGTH IN X (HORIZONTAL)

DIRECTION

(1)

CONTROL BITS

A (97H[3:0]) B (C7H[3:0])

A(96H[7:0]) B(C6H[7:0])

XS11

XS10

XS9

XS8

XS7

XS6

XS5

XS4

XS3

XS2

XS1

XS0

No output

Odd lengths are allowed, but will be
rounded up to even lengths

Maximum possible number of input
pixels = 4095

VERTICAL INPUT ACQUISITION

WINDOW DEFINITION OFFSET IN

Y (VERTICAL) DIRECTION

(1)

CONTROL BITS

A(98H[3:0]) B(C8H[3:0])

A(98H[7:0]) B(C8H[7:0])

YO11 YO10 YO9

YO8

YO7

YO6

YO5

YO4

YO3

YO2

YO1

YO0

Line offset = 0

Line offset = 1

Maximum line offset = 4095

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Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

Table 108 Vertical input window length; register set A (9AH[7:0]; 9BH[3:0]) and B (CAH[7:0]; CBH[3:0])

Note

1. For trigger condition: STRC[1:0]90H[1:0] = 00; YO + YS > (number of input lines per field

2), will result in field

dropping. Other trigger conditions: YS > (number of input lines per field

2), will result in field dropping.

15.5.8

UBADDRESSES

9CH

9FH

Table 109 Horizontal output window length; register set A (9CH[7:0]; 9DH[3:0]) and B (CCH[7:0]; CDH[3:0])

Notes

1. Reference for counting are luminance samples.

2. If the desired output length is greater than the number of scaled output pixels, the last scaled pixel is repeated.

Table 110 Vertical output window length; register set A (9EH[7:0]; 9FH[3:0]) and B (CEH[7:0]; CFH[3:0])

Note

1. If the desired output length is greater than the number of scaled output lines, the processing is cut.

VERTICAL INPUT ACQUISITION

WINDOW DEFINITION INPUT

WINDOW LENGTH IN

Y (VERTICAL) DIRECTION

(1)

CONTROL BITS

A(9BH[3:0]) B(CBH[3:0])

A(9AH[7:0]) B(CAH[7:0])

YS11

YS10

YS9

YS8

YS7

YS6

YS5

YS4

YS3

YS2

YS1

YS0

No input lines

1 input line

Maximum possible number of input
lines = 4095

HORIZONTAL OUTPUT

ACQUISITION WINDOW

DEFINITION NUMBER OF

DESIRED OUTPUT PIXEL IN

X (HORIZONTAL) DIRECTION

(1)

CONTROL BITS

A(9DH[3:0]) B(CDH[3:0])

A(9CH[7:0]) B(CCH[7:0])

XD11

XD10

XD9

XD8

XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0

No output

Odd lengths are allowed, but will be
filled up to even lengths

Maximum possible number of input
pixels = 4095; note 2

VERTICAL OUTPUT ACQUISITION

WINDOW DEFINITION NUMBER
OF DESIRED OUTPUT LINES IN

Y (VERTICAL) DIRECTION

CONTROL BITS

A(9FH[3:0]) B(CFH[3:0])

A(9EH[7:0]) B(CEH[7:0])

YD11 YD10 YD9

YD8

YD7

YD6

YD5

YD4

YD3

YD2

YD1

YD0

No output

1 pixel

Maximum possible number of output
lines = 4095; note 1

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Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

15.5.9

UBADDRESSES

A0H

A2H

Table 111 Horizontal prescaling; register set A (A0H[5:0]) and B (D0H[5:0])

Table 112 Accumulation length; register set A (A1H[5:0]) and B (D1H[5:0])

Table 113 Prescaler DC gain and FIR prefilter control; register set A (A2H[3:0]) and B (D2H[3:0])
X = don't care.

HORIZONTAL INTEGER PRESCALING RATIO (XPSC)

CONTROL BITS D5 TO D0

XPSC5 XPSC4 XPSC3 XPSC2 XPSC1 XPSC0

Not allowed

Down-scale = 1

Down-scale =

...

Down-scale =

HORIZONTAL PRESCALER ACCUMULATION

SEQUENCE LENGTH (XACL)

CONTROL BITS D5 TO D0

XACL5 XACL4 XACL3 XACL2 XACL1 XACL0

Accumulation length = 1

Accumulation length = 2

...

Accumulation length = 64

PRESCALER DC GAIN

CONTROL BITS D3 TO D0

XC2_1

XDCG2

XDCG1

XDCG0

Prescaler output is renormalized by gain factor = 1

Prescaler output is renormalized by gain factor =

128

Weighting of all accumulated samples is factor `1';
e.g. XACL = 4

sequence 1 + 1 + 1 + 1 + 1

Weighting of samples inside sequence is factor `2';
e.g. XACL = 4

sequence 1 + 2 + 2 + 2 + 1

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Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

Table 114 Prescaler DC gain and FIR prefilter control; register set A (A2H[7:4]) and B (D2H[7:4])
X = don't care.

15.5.10 S

UBADDRESSES

A4H

A6H

Table 115 Luminance brightness setting; register set A (A4H[7:0]) and B (D4H[7:0])

Table 116 Luminance contrast setting; register set A (A5H[7:0]) and B (D5H[7:0])

Table 117 Chrominance saturation setting; register set A (A6H[7:0]) and B (D6H[7:0])

FIR PREFILTER CONTROL

CONTROL BITS D7 TO D4

PFUV1

PFUV0

PFY1

PFY0

Luminance FIR filter bypassed

H_y(z) =

(1 2 1)

H_y(z) =

(

1 1 1.75 4.5 1.75 1

H_y(z) =

(1 2 2 2 1)

Chrominance FIR filter bypassed

H_uv(z) =

(1 2 1)

H_uv(z) =

(3 8 10 8 3)

H_uv(z) =

(1 2 2 2 1)

LUMINANCE

BRIGHTNESS SETTING

CONTROL BITS D7 TO D0

BRIG7

BRIG6

BRIG5

BRIG4

BRIG3

BRIG2

BRIG1

BRIG0

Value = 0

Nominal value = 128

Value = 255

LUMINANCE CONTRAST

SETTING

CONTROL BITS D7 TO D0

CONT7

CONT6

CONT5

CONT4

CONT3

CONT2

CONT1

CONT0

Gain = 0

Gain =

Nominal gain = 64

Gain =

127

CHROMINANCE

SATURATION SETTING

CONTROL BITS D7 TO D0

SATN7

SATN6

SATN5

SATN4

SATN3

SATN2

SATN1

SATN0

Gain = 0

Gain =

Nominal gain = 64

Gain =

127

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Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

15.5.11 S

UBADDRESSES

A8H

AEH

Table 118 Horizontal luminance scaling increment; register set A (A8H[7:0]; A9H[7:0]) and B (D8H[7:0]; D9H[7:0])

Table 119 Horizontal luminance phase offset; register set A (AAH[7:0]) and B (DAH[7:0])

Table 120 Horizontal chrominance scaling increment; register set A (ACH[7:0]; ADH[7:0]) and B (DCH[7:0]; DDH[7:0])

Note

1. Bits XSCC[15:13] are reserved and are set to logic 0.

Table 121 Horizontal chrominance phase offset; register set A (AEH[7:0]) and B (DEH[7:0])

HORIZONTAL LUMINANCE

SCALING INCREMENT

CONTROL BITS

A(A9H[7:4])
B(D9H[7:4])

A(A9H[3:0])
B(D9H[3:0])

A(A8H[7:4])
B(D8H[7:4])

A(A8H[3:0])
B(D8H[3:0])

XSCY[15:12]

XSCY[11:8]

XSCY[7:4]

XSCY[3:0]

Scale =

1024

(theoretical) zoom

0000

Scale =

1024

294

, lower limit defined by

data path structure

0000

0001

0010

0110

Scale =

1024

1023

zoom

0000

0011

1111

Scale = 1, equals 1024

0000

0100

0000

Scale =

1024

1025

down-scale

0000

0100

0000

0001

Scale =

1024

8191

down-scale

0001

1111

HORIZONTAL LUMINANCE PHASE

OFFSET

CONTROL BITS D7 TO D0

XPHY7

XPHY6

XPHY5

XPHY4

XPHY3

XPHY2

XPHY1

XPHY0

Offset = 0

Offset =

pixel

Offset =

= 1 pixel

Offset =

255

pixel

HORIZONTAL CHROMINANCE

SCALING INCREMENT

CONTROL BITS

A (ADH[7:4])
B (DDH[7:4])

A (ADH[3:0])
B (DDH[3:0])

A (ACH[7:4])
B (DCH[7:4])

A (ACH[3:0])
B (DCH[3:0])

XSCC[15:12]

(1)

XSCC[11:8]

XSCC[7:4]

XSCC[3:0]

This value must be set to the
luminance value

XSCY[15:0]

0000

0001

1111

HORIZONTAL CHROMINANCE

PHASE OFFSET

CONTROL BITS D7 TO D0

XPHC7

XPHC6

XPHC5

XPHC4

XPHC3

XPHC2

XPHC1

XPHC0

This value must be set to

XPHY[7:0]

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126

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

15.5.12 S

UBADDRESSES

B0H

BFH

Table 122 Vertical luminance scaling increment; register set A (B0H[7:0]; B1H[7:0]) and B (E0H[7:0]; E1H[7:0])

Table 123 Vertical chrominance scaling increment; register set A (B2H[7:0]; B3H[7:0]) and B (E2H[7:0]; E3H[7:0])

Table 124 Vertical scaling mode control; register set A (B4H[4 and 0]) and B (E4H[4 and 0])
X = don't care.

Table 125 Vertical chrominance phase offset `00'; register set A (B8H[7:0]) and B (E8H[7:0])

VERTICAL LUMINANCE SCALING

INCREMENT

CONTROL BITS

A (B1H[7:4])
B (E1H[7:4])

A (B1H[3:0])
B (E1H[3:0])

A (B0H[7:4])
B (E0H[7:4])

A (B0H[3:0])
B (E0H[3:0])

YSCY[15:12]

YSCY[11:8]

YSCY[7:4]

YSCY[3:0]

Scale =

1024

(theoretical) zoom

0000

0001

Scale =

1024

1023

zoom

0000

0011

1111

Scale = 1, equals 1024

0000

0100

0000

Scale =

1024

1025

down-scale

0000

0100

0000

0001

Scale =

63.999

down-scale

1111

VERTICAL CHROMINANCE

SCALING INCREMENT

CONTROL BITS

A (B3H[7:4])
B (E3H[7:4])

A (B3H[3:0])
B (E3H[3:0])

A (B2H[7:4])
B (E2H[7:4])

A (B2H[3:0])
B (E2H[3:0])

YSCC[15:12]

YSCC[11:8]

YSCC[7:4]

YSCC[3:0]

This value must be set to the
luminance value YSCY[15:0]

0000

0001

1111

VERTICAL SCALING MODE CONTROL

CONTROL BITS D4 AND D0

YMIR

YMODE

Vertical scaling performs linear interpolation between lines

Vertical scaling performs higher order accumulating interpolation, better alias
suppression

No mirroring

Lines are mirrored

VERTICAL CHROMINANCE PHASE

OFFSET

CONTROL BITS D7 TO D0

YPC07

YPC06

YPC05

YPC04

YPC03

YPC02

YPC01

YPC00

Offset = 0

Offset =

= 1 line

Offset =

255

lines

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Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

Table 126 Vertical luminance phase offset `00'; register set A (BCH[7:0]) and B (ECH[7:0])

16 PROGRAMMING START SET-UP

16.1

Decoder part

The given values force the following behaviour of the SAA7114H decoder part:

�

The analog input AI11 expects an NTSC M, PAL BDGHI or SECAM signal in CVBS format; analog anti-alias filter and
AGC active

�

Automatic field detection enabled

�

Standard ITU 656 output format enabled on expansion (X) port

�

Contrast, brightness and saturation control in accordance with ITU standards

�

Adaptive comb filter for luminance and chrominance activated

�

Pins LLC, LLC2, XTOUT, RTS0, RTS1 and RTCO are set to 3-state.

Table 127 Decoder part start set-up values for the three main standards

VERTICAL LUMINANCE PHASE

OFFSET

CONTROL BITS D7 TO D0

YPY07

YPY06

YPY05

YPY04

YPY03

YPY02

YPY01

YPY00

Offset = 0

Offset =

= 1 line

Offset =

255

lines

SUB

ADDRESS

(HEX)

BIT NAME

(1)

VALUES (HEX)

NTSC M PAL BDGHI

SECAM

chip version

ID07 to ID04

read only

horizontal increment
delay

X, X, X, X, IDEL3 to IDEL0

analog input control 1

FUSE1 and FUSE0, GUDL1 to GUDL0,
MODE3 to MODE0

analog input control 2

X, HLNRS, VBSL, WPOFF, HOLDG,
GAFIX, GAI28 and GAI18

analog input control 3

GAI17 to GAI10

analog input control 4

GAI27 to GAI20

horizontal sync start

HSB7 to HSB0

horizontal sync stop

HSS7 to HSS0

sync control

AUFD, FSEL, FOET, HTC1, HTC0,
HPLL, VNOI1 and VNOI0

luminance control

BYPS, YCOMB, LDEL, LUBW,
LUFI3 to LUFI0

luminance brightness
control

DBRI7 to DBRI0

luminance contrast
control

DCON7 to DCON0

chrominance saturation
control

DSAT7 to DSAT0

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Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

Note

1. All X values must be set to LOW.

chrominance hue control

HUEC7 to HUEC0

chrominance control 1

CDTO, CSTD2 to CSTD0, DCVF, FCTC,
X, CCOMB

chrominance gain control

ACGC, CGAIN6 to CGAIN0

chrominance control 2

OFFU1, OFFU0, OFFV1, OFFV0,
CHBW, LCBW2 to LCBW0

mode/delay control

COLO, RTP1, HDEL1, HDEL0, RTP0,
YDEL2 to YDEL0

RT signal control

RTSE13 to RTSE10,
RTSE03 to RTSE00

RT/X-port output control

RTCE, XRHS, XRVS1, XRVS0, HLSEL,
OFTS2 to OFTS0

analog, ADC,
compatibility control

CM99, UPTCV, AOSL1, AOSL0,
XTOUTE, OLDSB, APCK1 and APCK0

VGATE start, FID change

VSTA7 to VSTA0

VGATE stop

VSTO7 to VSTO0

miscellaneous/VGATE
MSBs

LLCE, LLC2E, X, X, X, VGPS,
VSTO8 and VSTA8

raw data gain

RAWG7 to RAWG0

raw data offset

RAWO7 to RAWO0

1A to 1E

reserved

X, X, X, X, X, X, X, X

decoder status byte
(OLDSB = 0)

INTL, HVLN, FIDT, GLIMT, GLIMB,
WIPA, COPRO, RDCAP

read only

SUB

ADDRESS

(HEX)

BIT NAME

(1)

VALUES (HEX)

NTSC M PAL BDGHI

SECAM

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Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

16.2

Audio clock generation part

The given values force the following behaviour of the SAA7114H audio clock generation part:

�

Used crystal is 24.576 MHz

�

Expected field frequency is 59.94 Hz (e.g. NTSC M standard)

�

Generated audio master clock frequency at pin AMCLK is 256

�

44.1 kHz = 11.2896 MHz

�

AMCLK is externally connected to AMXCLK (short-cut between pins 37 and 41)

�

ASCLK = 32

�

44.1 kHz = 1.4112 MHz

�

ALRCLK is 44.1 kHz.

Table 128 Audio clock part set-up values

Note

1. All X values must be set to LOW.

SUB

ADDRESS

(HEX)

REGISTER FUNCTION

BIT NAME

(1)

START VALUES

7 6 5 4 3 2 1 0 HEX

audio master clock cycles per
field; bits 7 to 0

ACPF7 to ACPF0

1 0 1 1 1 1 0 0

audio master clock cycles per
field; bits 15 to 8

ACPF15 to ACPF8

1 1 0 1 1 1 1 1

audio master clock cycles per
field; bits 17 and 16

X, X, X, X, X, X, ACPF17 and ACPF16 0 0 0 0 0 0 1 0

reserved

X, X, X, X, X, X, X, X

0 0 0 0 0 0 0 0

audio master clock nominal
increment; bits 7 to 0

ACNI7 to ACNI0

1 1 0 0 1 1 0 1

audio master clock nominal
increment; bits 15 to 8

ACNI15 to ACNI8

1 1 0 0 1 1 0 0

audio master clock nominal
increment; bits 21 to 16

X, X, ACNI21 to ACNI16

0 0 1 1 1 0 1 0

reserved

X, X, X, X, X, X, X, X

0 0 0 0 0 0 0 0

clock ratio AMXCLK to ASCLK

X, X, SDIV5 to SDIV0

0 0 0 0 0 0 1 1

clock ratio ASCLK to ALRCLK

X, X, LRDIV5 to LRDIV0

0 0 0 1 0 0 0 0

audio clock generator basic
set-up

X, X, X, X, APLL, AMVR, LRPH,
SCPH

0 0 0 0 0 0 0 0

3B to 3F

reserved

X, X, X, X, X, X, X, X

0 0 0 0 0 0 0 0

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PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

16.3

Data slicer and data type control part

The given values force the following behaviour of the SAA7114H VBI-data slicer part:

�

Closed captioning data are expected at line 21 of field 1 (60 Hz/525 line system)

�

All other lines are processed as active video

�

Sliced data are framed by ITU 656 like SAV/EAV sequence (DID[5:0] = 3EH

MSB of SAV/EAV = 1).

Table 129 Data slicer start set-up values

Notes

1. All X values must be set to LOW.

2. Changes for 50 Hz/625 line systems: subaddress 5AH = 03H and subaddress 5BH = 03H.

SUB

ADDRESS

(HEX)

FUNCTION

BIT NAME

(1)

START VALUES

7 6 5 4 3 2 1 0 HEX

slicer control 1

X, HAM_N, FCE, HUNT_N, X, X, X, X

0 1 0 0 0 0 0 0

41 to 53

line control register 2 to 20

LCRn_7 to LCRn_0 (n = 2 to 20)

1 1 1 1 1 1 1 1

line control register 21

LCR21_7 to LCR21_0

0 1 0 1 1 1 1 1

55 to 57

line control register 22 to 24

LCRn_7 to LCRn_0 (n = 22 to 24)

1 1 1 1 1 1 1 1

programmable framing code

FC7 to FC0

0 0 0 0 0 0 0 0

horizontal offset for slicer

HOFF7 to HOFF0

0 1 0 0 0 1 1 1

vertical offset for slicer

VOFF7 to VOFF0

0 0 0 0 0 1 1 0 06

(2)

field offset and MSBs for
horizontal and vertical offset

FOFF, RECODE, X, VOFF8, X,
HOFF10 to HOFF8

1 0 0 0 0 0 1 1 83

(2)

reserved

X, X, X, X, X, X, X, X

0 0 0 0 0 0 0 0

header and data identification
code control

FVREF, X, DID5 to DID0

0 0 1 1 1 1 1 0

sliced data identification code

X, X, SDID5 to SDID0

0 0 0 0 0 0 0 0

reserved

X, X, X, X, X, X, X, X

0 0 0 0 0 0 0 0

slicer status byte 1

, FC8V, FC7V, VPSV, PPV, CCV,

read-only register

slicer status byte 2

, F21_N, LN8 to LN4

read-only register

LN3 to LN0, DT3 to DT0

read-only register

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Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

16.4

Scaler and interfaces

Table 130 shows some examples for the scaler
programming with:

�

prsc = prescale ratio

�

fisc = fine scale ratio

�

vsc = vertical scale ratio.

The ratio is defined as:

In the following settings the VBI-data slicer is inactive. To
activate the VBI-data slicer, VITX[1:0]86H[7:6] has to be
set to `11'. Dependent on the VBI-data slicer settings, the
sliced VBI-data are inserted after end of scaled video lines,
if the regions of VBI-data slicer and scaler overlaps.

To compensate the running-in of the vertical scaler, the
vertical input window lengths are extended by
2 to 290 lines, respectively 242 lines for XS, but the scaler
increment calculations are done with 288, respectively
240 lines.

16.4.1

RIGGER CONDITION

For trigger condition STRC[1:0]90H[1:0] not equal `00'.

If the value of (YO + YS) is greater equal 262 (NTSC),
respectively 312 (PAL) the output field rate is reduced to
30 Hz, respectively 25 Hz.

Horizontal and vertical offsets (XO and YO) have to be
used to adjust the displayed video in the display window.
As this adjustment is application dependent, the listed
values are only dummy values.

16.4.2

AXIMUM ZOOM FACTOR

The maximum zoom factor is dependent on the back-end
data rate and therefore back-end clock and data format
dependent (8 or 16-bit output). The maximum horizontal
zoom is limited to about 3.5, due to internal data path
restrictions.

number of input pixel

number of output pixel

-----------------------------------------------------------

16.4.3

XAMPLES

Table 130 Example configurations

EXAMPLE

NUMBER

SCALER SOURCE AND REFERENCE EVENTS

INPUT

WINDOW

OUTPUT

WINDOW

SCALE

RATIOS

analog input to 8-bit I-port output, with SAV/EAV codes, 8-bit
serial byte stream decoder output at X-port; acquisition trigger
at falling edge vertical and rising edge horizontal reference
signal; H and V-gates on IGPH and IGPV, IGP0 = VBI sliced
data flag, IGP1 = FIFO almost full, level

24, IDQ qualifier

logic 1 active

720

�

240 720

�

240 prsc = 1;

fisc = 1;
vsc = 1

analog input to 16-bit output, without SAV/EAV codes, Y on
I-port, UV on H-port and decoder output at X-port; acquisition
trigger at falling edge vertical and rising edge horizontal
reference signal; H and V-pulses on IGPH and IGPV, output
FID on IGP0, IGP1 fixed to logic 1, IDQ qualifier logic 0 active

704

�

288 768

�

288 prsc = 1;

fisc = 0.91667;
vsc = 1

X-port input 8 bit with SAV/EAV codes, no reference signals on
XRH and XRV, XCLK as gated clock; field detection and
acquisition trigger on different events; acquisition triggers at
rising edge vertical and rising edge horizontal; I-port output
8 bit with SAV/EAV codes like example number 1

720

�

240 352

�

288 prsc = 2;

fisc = 1.022;
vsc = 0.8333

X-port and H-port for 16-bit YUV 4 : 2 : 2 input (if no 16-bit
output selected); XRH and XRV as references; field detection
and acquisition trigger at falling edge vertical and rising edge
horizontal; I-port output 8 bit with SAV/EAV codes, but Y only
output

720

�

288 200

�

prsc = 2;
fisc = 1.8;
vsc = 3.6

2000 Mar 15

132

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

Table 131 Scaler and interface configuration example

C-BUS

ADDRESS

(HEX)

MAIN FUNCTIONALITY

EXAMPLE 1 EXAMPLE 2 EXAMPLE 3 EXAMPLE 4

HEX

DEC

HEX

DEC

HEX

DEC

HEX

DEC

Global settings

task enable, IDQ and back-end clock
definition

XCLK output phase and X-port output enable

IGPH, IGPV, IGP0 and IGP1 output definition

signal polarity control and I-port byte
swapping

FIFO flag thresholds and video/text
arbitration

ICLK and IDQ output phase and I-port enable

power save control and software reset

Task A: scaler input configuration and output format settings

task handling

scaler input source and format definition

reference signal definition at scaler input

I-port output formats and configuration

Input and output window definition

horizontal input offset (XO)

horizontal input (source) window length (XS)

720

704

720

vertical input offset (YO)

vertical input (source) window length (YS)

242

290

242

290

horizontal output (destination) window length
(XD)

720

768

352

200

vertical output (destination) window length
(YD)

240

288

Prefiltering and prescaling

integer prescale (value `00' not allowed)

accumulation length for prescaler

FIR prefilter and prescaler DC normalization

scaler brightness control

128

scaler contrast control

scaler saturation control

2000 Mar 15

133

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

Horizontal phase scaling

horizontal scaling increment for luminance

1024

938

1048

1844

horizontal phase offset luminance

horizontal scaling increment for chrominance

512

469

524

922

horizontal phase offset chrominance

Vertical scaling

vertical scaling increment for luminance

1024

853

3686

vertical scaling increment for chrominance

1024

853

3686

vertical scaling mode control

B8 to BF

vertical phase offsets luminance and
chrominance (need to be used for interlace
correct scaled output)

start with B8 to BF at 00H, if there are no problems with
the interlaced scaled output optimize according to
Section 8.3.3.2

C-BUS

ADDRESS

(HEX)

MAIN FUNCTIONALITY

EXAMPLE 1 EXAMPLE 2 EXAMPLE 3 EXAMPLE 4

HEX

DEC

HEX

DEC

HEX

DEC

HEX

DEC

2000 Mar 15

135

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

18 SOLDERING

18.1

Introduction to soldering surface mount
packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"Data Handbook IC26; Integrated Circuit Packages"

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

18.2

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250

�

C. The top-surface temperature of the

packages should preferable be kept below 230

�

18.3

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

�

Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

�

For packages with leads on two sides and a pitch (e):

� larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

� smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

�

For packages with leads on four sides, the footprint must
be placed at a 45

�

angle to the transport direction of the

printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250

�

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

18.4

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300

�

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320

�

2000 Mar 15

136

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

18.5

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

"Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods".

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45

�

angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

PACKAGE

SOLDERING METHOD

WAVE

REFLOW

(1)

BGA, SQFP

not suitable

suitable

HLQFP, HSQFP, HSOP, SMS

not suitable

(2)

suitable

PLCC

(3)

, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended

(3)(4)

suitable

SSOP, TSSOP, VSO

not recommended

(5)

suitable

2000 Mar 15

137

Philips Semiconductors

Preliminary specification

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler

SAA7114H

19 DEFINITIONS

20 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

21 PURCHASE OF PHILIPS I

C COMPONENTS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I

C components conveys a license under the Philips' I

C patent to use the

components in the I

C system provided the system conforms to the I

C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

� Philips Electronics N.V.

SCA

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

2000

Philips Semiconductors � a worldwide company

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Printed in The Netherlands

753505/01/pp

140

Date of release:

2000 Mar 15

Document order number:

9397 750 05976

Электронный компонент: SAA7114