1999 May 31

Philips Semiconductors

Product specification

Digital video encoder

SAA7126H; SAA7127H

FEATURES

Monolithic CMOS 3.3 V device, 5 V I

C-bus optionally

Digital PAL/NTSC encoder

System pixel frequency 13.5 MHz

54 MHz double-speed multiplexed D1 interface capable
of splitting data into two separate channels (encoded
and baseband)

Four Digital-to-Analog Converters (DACs) for CVBS
(CSYNC, VBS), RED (Cr, C), GREEN (Y, VBS) and
BLUE (Cb, CVBS) two times oversampled (signals in
parenthesis are optionally). RED (Cr), GREEN (Y) and
BLUE (Cb) signal outputs with 9-bit resolution, whereas
all other signal outputs have 10-bit resolution; CSYNC is
an advanced composite sync on the CVBS output for
RGB display centring.

Real-time control of subcarrier

Cross-colour reduction filter

Closed captioning encoding and World Standard
Teletext (WST) and North-American Broadcast Text
System (NABTS) teletext encoding including sequencer
and filter

Copy Generation Management System (CGMS)
encoding (CGMS described by standard CPR-1204 of
EIAJ); 20 bits in lines 20/283 (NTSC) can be loaded via
the I

C-bus

Fast I

C-bus control port (400 kHz)

Line 23 Wide Screen Signalling (WSS) encoding

Video Programming System (VPS) data encoding in
line 16 (CCIR line count)

Encoder can be master or slave

Programmable horizontal and vertical input
synchronization phase

Programmable horizontal sync output phase

Internal Colour Bar Generator (CBG)

Macrovision Pay-per-View copy protection system
rev. 7.01 and rev. 6.1 as option; `handsfree' Macrovision
pulse support through on-chip timer for pulse amplitude
modulation; this applies to SAA7126H only. The device
is protected by USA patent numbers 4631603, 4577216
and 4819098 and other intellectual property rights.
Use of the Macrovision anti-copy process in the device
is licensed for non-commercial home use only. Reverse
engineering or disassembly is prohibited. Please
contact your nearest Philips Semiconductors sales
office for more information.

Controlled rise/fall times of output syncs and blanking

On-chip crystal oscillator (3rd-harmonic or fundamental
crystal)

Down mode (low output voltage) or power-save mode of
DACs

QFP44 package.

GENERAL DESCRIPTION

The SAA7126H; SAA7127H encodes digital Cb-Y-Cr
video data to an NTSC or PAL CVBS or S-video signal.
Simultaneously, RGB or bypassed but interpolated
Cb-Y-Cr signals are available via three additional
Digital-to-Analog Converters (DACs). The circuit at a
54 MHz multiplexed digital D1 input port accepts two CCIR
compatible Cb-Y-Cr data streams with 720 active pixels
per line in 4 : 2 : 2 multiplexed formats, for example MPEG
decoded data with overlay and MPEG decoded data
without overlay, whereas one data stream is latched at the
rising, the other one at the falling clock edge.

It includes a sync/clock generator and on-chip DACs.

ORDERING INFORMATION

TYPE NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

SAA7126H

QFP44

plastic quad flat package; 44 leads (lead length 1.3 mm);
body 10

1.75 mm

SOT307-2

SAA7127H

1999 May 31

Philips Semiconductors

Product specification

Digital video encoder

SAA7126H; SAA7127H

QUICK REFERENCE DATA

BLOCK DIAGRAM

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

DDA

analog supply voltage

3.15

3.3

3.45

DDD

digital supply voltage

3.0

3.3

3.6

DDA

analog supply current

100

DDD

digital supply current

input signal voltage levels

TTL compatible

o(p-p)

analog output signal voltages Y, C and CVBS
without load (peak-to-peak value)

1.30

1.45

1.55

load resistance

300

lf(i)

low frequency integral linearity error

LSB

lf(d)

low frequency differential linearity error

LSB

amb

ambient temperature

Fig.1 Block diagram.

handbook, full pagewidth

C-BUS

INTERFACE

DATA

MANAGER

ENCODER

SYNC/CLOCK

OUTPUT

INTERFACE

MP7

MP0

TTX

VDD(I2C)

RESET SDA SCL

RCV1

RCV2

TTXRQ

XCLK

XTAL

XTALI

LLC1

CVBS

RED

GREEN

BLUE

C-bus

control

C-bus

control

C-bus

control

C-bus

control

C-bus

control

VSSD1

VSSD2

VSSD3

VDDD1

VDDD2

VDDD3

VSSA1

VSSA2

VSSA3

VDDA1

VDDA2

VDDA3

VDDA4

RTCI

clock

and timing

RGB

PROCESSOR

C-bus

control

CbCr

RES

n.c.

24, 27

9 to 16

MP1

MP2

MHB498

SAA7126H
SAA7127H

1999 May 31

Philips Semiconductors

Product specification

Digital video encoder

SAA7126H; SAA7127H

PINNING

SYMBOL TYPE PIN

DESCRIPTION

RES

reserved pin; do not connect

test pin; connected to digital ground for normal operation

LLC1

line-locked clock input; this is the 27 MHz master clock

SSD1

digital ground 1

DDD1

digital supply voltage 1

RCV1

I/O

raster control 1 for video port; this pin receives/provides a VS/FS/FSEQ signal

RCV2

I/O

raster control 2 for video port; this pin provides an HS pulse of programmable length or
receives an HS pulse

MP7

double-speed 54 MHz MPEG port; it is an input for

"CCIR 656" style multiplexed Cb-Y-Cr

data; data is sampled on the rising and falling clock edge; data sampled on the rising edge is
then sent to the encoding part of the device; data sampled on the falling edge is sent to the
RGB part of the device (or vice versa, depending on programming)

MP6

MP5

MP4

MP3

MP2

MP1

MP0

DDD2

digital supply voltage 2

SSD2

digital ground 2

RTCI

real-time control input (I

C-bus register SRES = 0): if the LLC1 clock is provided by an

SAA7111 or SAA7151B, RTCI should be connected to the RTCO pin of the respective
decoder to improve the signal quality. Sync reset input (I

C-bus register SRES = 1): a HIGH

impulse resets synchronization of the encoder (first field, first line).

DD(I2C)

sense input for I

C-bus voltage; connect to I

C-bus supply

select I

C-bus address; LOW selects slave address 88H, HIGH selects slave address 8CH

SSA1

analog ground 1 for RED (Cr) (C) and GREEN (Y) (VBS) outputs

RED

analog output of RED (Cr) or (C) signal

n.c.

not connected

DDA1

analog supply voltage 1 for RED (Cr) (C) output

GREEN

analog output of GREEN (Y) or (VBS) signal

n.c.

not connected

DDA2

analog supply voltage 2 for GREEN (Y) (VBS) output

BLUE

analog output of BLUE (Cb) or (CVBS) signal

CVBS

analog output of CVBS (CSYNC) or (VBS) signal

DDA3

analog supply voltage 3 for BLUE (Cb) (CVBS) and CVBS (CSYNC) (VBS) outputs

SSA2

analog ground 2 for BLUE (Cb) (CVBS) and CVBS (CSYNC) (VBS) outputs

SSA3

analog ground 3 for the DAC reference ladder and the oscillator

XTAL

crystal oscillator output

XTALI

crystal oscillator input; if the oscillator is not used, this pin should be connected to ground

DDA4

analog supply voltage 4 for the DAC reference ladder and the oscillator

1999 May 31

Philips Semiconductors

Product specification

Digital video encoder

SAA7126H; SAA7127H

XCLK

clock output of the crystal oscillator

SSD3

digital ground 3

DDD3

digital supply voltage 3

RESET

reset input, active LOW. After reset is applied, all digital I/Os are in input mode; PAL black
burst on CVBS, VBS and C; RGB outputs set to lowest voltage. The I

C-bus receiver waits

for the START condition.

SCL

C-bus serial clock input

SDA

I/O

C-bus serial data input/output

TTXRQ

teletext request output, indicating when text bits are requested

TTX

teletext bit stream input

SYMBOL TYPE PIN

DESCRIPTION

Fig.2 Pin configuration.

handbook, full pagewidth

SAA7126H
SAA7127H

MHB499

VSSA3

VSSA2

VDDA3

CVBS

VDDA2

n.c.

GREEN

VDDA1

n.c.

RED

RES

LLC1

VSSD1

VDDD1

RCV2

MP7

MP5

BLUE

TTXRQ

SDA

SCL

RESET

DDD3

SSD3

DDA4

XTALI

XTAL

TTX

XCLK

MP3

MP2

MP1

MP0

DDD2

SSD2

DD(I2C)

SSA1

MP4

RTCI

RCV1

MP6

1999 May 31

Philips Semiconductors

Product specification

Digital video encoder

SAA7126H; SAA7127H

FUNCTIONAL DESCRIPTION

The digital video encoder encodes digital luminance and
colour difference signals into analog CVBS, S-video and
simultaneously RGB or Cr-Y-Cb signals. NTSC-M, PAL
B/G and sub-standards are supported.

Both interlaced and non-interlaced operation is possible
for all standards.

The basic encoder function consists of subcarrier
generation, colour modulation and insertion of
synchronization signals. Luminance and chrominance
signals are filtered in accordance with the standard
requirements of

"RS-170-A" and "ITU-R BT.470-3".

For ease of analog post filtering the signals are twice
oversampled with respect to the pixel clock before
digital-to-analog conversion.

The total filter transfer characteristics are illustrated in
Figs 3 to 8. The DACs for Y, C and CVBS are realized with
full 10-bit resolution; 9-bit resolution for RGB output.
The Cr-Y-Cb to RGB dematrix can be bypassed optionally
in order to provide the upsampled Cr-Y-Cb input signals.

The 8-bit multiplexed Cb-Y-Cr formats are

"CCIR 656"

(D1 format) compatible, but the SAV and EAV codes can
be decoded optionally; when the device is operated in
slave mode. Two independent data streams can be
processed, one latched by the rising edge of LLC1, the
other latched by the falling edge of LLC1. The purpose of
that is e.g. to forward one of the data streams containing
both video and On Screen Display (OSD) information to
the RGB outputs, and the other stream containing video
only to the encoded outputs CVBS and S-video.

For optimum display of RGB signals through a
euro-connector TV set, an early composite sync pulse (up
to 31LLC1 clock periods) can be provided optionally on the
CVBS output.

It is also possible to connect a Philips digital video decoder
(SAA7111, SAA7711A, SAA7112 or SAA7151B) to the
SAA7126H; SAA7127H. Information concerning the actual
subcarrier, PAL-ID and (with SAA7111 and newer types)
definite subcarrier phase can be inserted via the RTCI pin,
connected to the RTCO pin of a decoder.

The SAA7126H; SAA7127H synthesizes all necessary
internal signals, colour subcarrier frequency and
synchronization signals from that clock.

Wide screen signalling data can be loaded via the I

C-bus

and is inserted into line 23 for standards using a 50 Hz
field rate.

VPS data for program dependent automatic start and stop
of such featured VCR's is loadable via the I

C-bus.

The IC also contains closed caption and extended data
services encoding (line 21), and supports anti-taping
signal generation in accordance with Macrovision. It is also
possible to load data for copy generation management
system into line 20 of every field (525/60 line counting).

A number of possibilities are provided for setting different
video parameters such as:

Black and blanking level control

Colour subcarrier frequency

Variable burst amplitude etc.

During reset (RESET = LOW) and after reset is released,
all digital I/O stages are set to the input mode and the
encoder is set to PAL mode and outputs a `black burst'
signal on CVBS and S-video outputs, while RGB outputs
are set to their lowest output voltages. A reset forces the
I

C-bus interface to abort any running bus transfer.

Data manager

In the data manager, alternatively to the external video
data, a pre-defined colour look-up table located in this
block can be read out in a pre-defined sequence (8 steps
per active video line), achieving a colour bar test pattern
generator without need for an external data source.

Encoder

IDEO PATH

The encoder generates out of Y, U and V baseband
signals luminance and colour subcarrier output signals,
suitable for use as CVBS or separate Y and C signals.

Luminance is modified in gain and in offset (latter
programmable in a certain range to enable different black
level set-ups). After insertion of a fixed synchronization
pulse tip level, in accordance with standard composite
synchronization schemes, a blanking level can be set.
Other manipulations used for the Macrovision anti-taping
process such as additional insertion of AGC super-white
pulses (programmable in height) are supported by
SAA7126H only.

In order to enable easy analog post filtering, luminance is
interpolated from 13.5 MHz data rate to 27 MHz data rate,
providing luminance in 10-bit resolution. The transfer
characteristic of the luminance interpolation filter are
illustrated in Figs 5 and 6. Appropriate transients at
start/end of active video and for synchronization pulses
are ensured.

1999 May 31

Philips Semiconductors

Product specification

Digital video encoder

SAA7126H; SAA7127H

Chrominance is modified in gain (programmable
separately for U and V), standard dependent burst is
inserted, before baseband colour signals are interpolated
from a 6.75 MHz data rate to a 27 MHz data rate. One of
the interpolation stages can be bypassed, thus providing a
higher colour bandwidth, which can be made use of for
Y and C output. The transfer characteristics of the
chrominance interpolation filter are illustrated in
Figs 3 and 4.

The amplitude, beginning and ending of the inserted burst,
is programmable in a certain range that is suitable for
standard signals and for special effects. Behind the
succeeding quadrature modulator, colour in 10-bit
resolution is provided on the subcarrier.

The numeric ratio between the Y and C outputs is in
accordance with set standards.

ELETEXT INSERTION AND ENCODING

Pin TTX receives a WST or NABTS teletext bitstream
sampled at the LLC clock. Two protocols are provided: at
each rising edge of output signal (TTXRQ) a single teletext
bit has to be provided after a programmable delay at input
pin TTX. Or: the signal TTXRQ performs only a single
LOW-to-HIGH transition and remains at HIGH level for
360, 296 or 288 teletext bits, depending on the chosen
standard.

Phase variant interpolation is achieved on this bitstream in
the internal teletext encoder, providing sufficient small
phase jitter on the output text lines.

TTXRQ provides a fully programmable request signal to
the teletext source, indicating the insertion period of
bitstream at lines which are selectable independently for
both fields. The internal insertion window for text is set
to 360 (PAL-WST), 296 (NTSC-WST) or 288 (NABTS)
teletext bits including clock run-in bits. The protocol and
timing are illustrated in Fig.14.

IDEO

ROGRAMMING

YSTEM

(VPS)

ENCODING

Five bytes of VPS information can be loaded via the
I

C-bus and will be encoded in the appropriate format into

line 16.

LOSED CAPTION ENCODER

Using this circuit, data in accordance with the specification
of closed caption or extended data service, delivered by
the control interface, can be encoded (line 21).
Two dedicated pairs of bytes (two bytes per field), each
pair preceded by run-in clocks and framing code, are
possible.

The actual line number where data is to be encoded in, can
be modified in a certain range.

The data clock frequency is in accordance with the
definition for NTSC-M standard 32 times horizontal line
frequency.

Data LOW at the output of the DACs corresponds to 0 IRE,
data HIGH at the output of the DACs corresponds to
approximately 50 IRE.

It is also possible to encode closed caption data for 50 Hz
field frequencies at 32 times the horizontal line frequency.

NTI

TAPING

(SAA7126H

ONLY

)

For more information contact your nearest Philips
Semiconductors sales office.

RGB processor

This block contains a dematrix in order to produce red,
green and blue signals to be fed to a SCART plug.

Before Y, Cb and Cr signals are de-matrixed, individual
gain adjustment for Y and colour difference signals and
2 times oversampling for luminance and 4 times
oversampling for colour difference signals is performed.
The transfer curves of luminance and colour difference
components of RGB are illustrated in Figs 7 and 8.

Output interface/DACs

In the output interface, encoded Y and C signals are
converted from digital-to-analog in a 10-bit resolution.
Y and C signals are also combined to a 10-bit CVBS
signal.

The CVBS output occurs with the same processing delay
(equal to 51 LLC clock periods, measured from MP input
to the analog outputs) as the Y, C and RGB outputs.
Absolute amplitude at the input of the DAC for CVBS is
reduced by

with respect to Y and C DACs to make

maximum use of conversion ranges.

Red, green and blue signals are also converted from
digital-to-analog, each providing a 9-bit resolution.

Outputs of the DACs can be set together via software
control to minimum output voltage (approximately 0.2 V
DC) for either purpose. Alternatively, the buffers can be
switched into 3-state output condition; this allows for `wired
AND'ing with other 3-state outputs and can also be used
as a power-save mode.

1999 May 31

Philips Semiconductors

Product specification

Digital video encoder

SAA7126H; SAA7127H

Synchronization

The synchronization of the SAA7126H; SAA7127H is able
to operate in two modes; slave mode and master mode.

In master mode (see Fig.10), the circuit generates all
necessary timings in the video signal itself, and it can
provide timing signals at the RCV1 and RCV2 ports.
In slave mode, it accepts timing information either from the
RCV pins or from the embedded timing data of the
CCIR 656 data stream.

For the SAA7126H; SAA7127H, the only difference
between master and slave mode is that it ignores the
timing information at its inputs in master mode. Thus, if in
slave mode, any timing information is missing, the IC will
continue running free without a visible effect. But there
must not be any additional pulses (with wrong phase)
because the circuit will not ignore them.

In slave mode (see Fig.9), an interface circuit decides,
which signal is expected at the RCV1 port and which
information is taken from its active slope. The polarity can
be chosen, if PRCV1 is logic 0 the rising slope will be
active.

The signal can be:

A Vertical Sync (VS) pulse; the active slope sets the
vertical phase

An odd/even signal; the active slope sets the vertical
phase, the internal field flag to odd and optionally sets
the horizontal phase

A Field Sequence (FSEQ) signal; it marks the first field
of the 4 (NTSC) or 8 (PAL) field sequence. In addition to
the odd/even signal, it also sets the PAL phase and
optionally defines the subcarrier phase.

On the RCV2 port, the IC can provide a horizontal pulse
with programmable start and stop phase; this pulse can be
inhibited in the vertical blanking period to build up, for
example, a composite blanking signal.

The horizontal phase can be set via a separate input
RCV2. In the event of VS pulses at RCV1, this is
mandatory. It is also possible to set the signal path to blank
via this input.

From the CCIR 656 data stream, the SAA7126H;
SAA7127H decodes only the start of the first line in the odd
field. All other information is ignored and may miss. If this
kind of slave mode is active, the RCV pins may be
switched to output mode.

In slave mode, the horizontal trigger phase can be
programmed to any point in the line, the vertical phase

from line 0 to line 15 counted from the first serration pulse
in half line steps.

Whenever a synchronization information cannot be
derived directly from the inputs, the SAA7126H;
SAA7127H will calculate it from the internal horizontal,
vertical and PAL phase. This gives good flexibility with
respect to external synchronization but the circuit does not
suppress illegal settings. In such an event, e.g the
odd/even information may vanish as it does in the
non-interlaced modes.

In master mode, the line lengths are fixed to 1728 clocks
at 50 Hz and 1716 clocks at 60 Hz. To allow
non-interlaced frames, the field lengths can be varied by

0.5 lines. In the event of non-interlace, the SAA7126H;

SAA7127H does not provide odd/even information and the
output signal does not contain the PAL `Bruch sequence'.

At the RCV1 pin the IC can provide:

A Vertical Sync (VS) signal with 2.5 (50 Hz) or 3 (60 Hz)
lines duration

An odd/even signal which is LOW in odd fields

A Field Sequence (FSEQ) signal which is HIGH in the
first field of the 4 or 8 field sequence.

At the RCV2 pin, there is a horizontal pulse of
programmable phase and duration available. This pulse
can be suppressed in the programmable inactive part of a
field giving a composite blank signal.

The directions and polarities of the RCV ports can be
chosen independently. Timing references can be found in
Tables 29 and 37.

Clock

The input at LLC1 can either be an external clock source
or the buffered on-chip clock XCLK. The internal crystal
oscillator can be run with either a 3rd-harmonic or a
fundamental crystal.

C-bus interface

The I

C-bus interface is a standard slave transceiver,

supporting 7-bit slave addresses and 400 kbits/s
guaranteed transfer rate. It uses 8-bit subaddressing with
an auto-increment function. All registers are write and
readable, except one read only status byte.

The I

C-bus slave address is defined as 88H with pin 21

(SA) tied LOW and as 8CH with pin 21 (SA) tied HIGH.

1999 May 31

Philips Semiconductors

Product specification

Digital video encoder

SAA7126H; SAA7127H

Input levels and formats

The SAA7126H; SAA7127H expects digital Y, Cb, Cr data
with levels (digital codes) in accordance with

"CCIR 601".

For C and CVBS outputs, deviating amplitudes of the
colour difference signals can be compensated by
independent gain control setting, while gain for luminance
is set to predefined values, distinguishable for 7.5 IRE
set-up or without set-up.

The RGB, respectively Cr-Y-Cb path features a gain
setting individually for luminance (GY) and colour
difference signals (GCD).

Reference levels are measured with a colour bar,
100% white, 100% amplitude and 100% saturation.

Table 1

"CCIR 601" signal component levels

Notes

1. Transformation:

a) R = Y + 1.3707

(Cr

128)

b) G = Y

0.3365

(Cb

128)

0.6982

(Cr

128)

c) B = Y + 1.7324

(Cb

128).

2. Representation of R, G and B (or Cr, Y and Cb) at the output is 9 bits at 27 MHz.

Table 2

8-bit multiplexed format (similar to

"CCIR 601")

COLOUR

SIGNALS

(1)

(2)

White

235

128

235

Yellow

210

146

235

Cyan

170

166

235

Green

145

235

Magenta

106

202

222

235

Red

240

235

Blue

240

110

235

Black

128

TIME

BITS

Sample

Luminance pixel number

Colour pixel number

1999

May

Philips Semiconductors

Product specification

Digital video encoder

SAA7126H; SAA7127H

This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...

Bit allocation map

Table 3

Slave receiver (slave address 88H)

REGISTER FUNCTION

SUB ADDR

(HEX)

DATA BYTE

(1)

Status byte (read only)

00H

VER2

VER1

VER0

CCRDO

CCRDE

FSEQ

O_E

Null

01H to 25H

Wide screen signal

26H

WSS7

WSS6

WSS5

WSS4

WSS3

WSS2

WSS1

WSS0

Wide screen signal

27H

WSSON

WSS13

WSS12

WSS11

WSS10

WSS9

WSS8

Real-time control, burst start

28H

DECCOL

DECFIS

BS5

BS4

BS3

BS2

BS1

BS0

Sync reset enable, burst end

29H

SRES

BE5

BE4

BE3

BE2

BE1

BE0

Copy generation 0

2AH

CG07

CG06

CG05

CG04

CG03

CG02

CG01

CG00

Copy generation 1

2BH

CG15

CG14

CG13

CG12

CG11

CG10

CG09

CG08

CG enable, copy generation 2

2CH

CGEN

CG19

CG18

CG17

CG16

Output port control

2DH

VBSEN1

VBSEN0

CVBSEN

CEN

CVBSTRI

RTRI

GTRI

BTRI

Null

2EH to 37H

Gain luminance for RGB

38H

GY4

GY3

GY2

GY1

GY0

Gain colour difference for RGB

39H

GCD4

GCD3

GCD2

GCD1

GCD0

Input port control 1

3AH

CBENB

SYMP

DEMOFF

CSYNC

MP2C2

MP2C1

VPS enable, input control 2

54H

VPSEN

CCIRS

EDGE2

EDGE1

VPS byte 5

55H

VPS57

VPS56

VPS55

VPS54

VPS53

VPS52

VPS51

VPS50

VPS byte 11

56H

VPS117

VPS116

VPS115

VPS114

VPS113

VPS112

VPS111

VPS110

VPS byte 12

57H

VPS127

VPS126

VPS125

VPS124

VPS123

VPS122

VPS121

VPS120

VPS byte 13

58H

VPS137

VPS136

VPS135

VPS134

VPS133

VPS132

VPS131

VPS130

VPS byte 14

59H

VPS147

VPS146

VPS145

VPS144

VPS143

VPS142

VPS141

VPS140

Chrominance phase

5AH

CHPS7

CHPS6

CHPS5

CHPS4

CHPS3

CHPS2

CHPS1

CHPS0

Gain U

5BH

GAINU7

GAINU6

GAINU5

GAINU4

GAINU3

GAINU2

GAINU1

GAINU0

Gain V

5CH

GAINV7

GAINV6

GAINV5

GAINV4

GAINV3

GAINV2

GAINV1

GAINV0

Gain U MSB, real-time control,
black level

5DH

GAINU8

DECOE

BLCKL5

BLCKL4

BLCKL3

BLCKL2

BLCKL1

BLCKL0

Gain V MSB, real-time
control, blanking level

5EH

GAINV8

DECPH

BLNNL5

BLNNL4

BLNNL3

BLNNL2

BLNNL1

BLNNL0

CCR, blanking level VBI

5FH

CCRS1

CCRS0

BLNVB5

BLNVB4

BLNVB3

BLNVB2

BLNVB1

BLNVB0

Null

60H

Standard control

61H

DOWNB

DOWNA

INPI

YGS

SCBW

PAL

FISE

1999

May

Philips Semiconductors

Product specification

Digital video encoder

SAA7126H; SAA7127H

This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...

Note

1. All bits labelled `0' are reserved. They must be programmed with logic 0.

RTC enable, burst amplitude

62H

RTCE

BSTA6

BSTA5

BSTA4

BSTA3

BSTA2

BSTA1

BSTA0

Subcarrier 0

63H

FSC07

FSC06

FSC05

FSC04

FSC03

FSC02

FSC01

FSC00

Subcarrier 1

64H

FSC15

FSC14

FSC13

FSC12

FSC11

FSC10

FSC09

FSC08

Subcarrier 2

65H

FSC23

FSC22

FSC21

FSC20

FSC19

FSC18

FSC17

FSC16

Subcarrier 3

66H

FSC31

FSC30

FSC29

FSC28

FSC27

FSC26

FSC25

FSC24

Line 21 odd 0

67H

L21O07

L21O06

L21O05

L21O04

L21O03

L21O02

L21O01

L21O00

Line 21 odd 1

68H

L21O17

L21O16

L21O15

L21O14

L21O13

L21O12

L21O11

L21O10

Line 21 even 0

69H

L21E07

L21E06

L21E05

L21E04

L21E03

L21E02

L21E01

L21E00

Line 21 even 1

6AH

L21E17

L21E16

L21E15

L21E14

L21E13

L21E12

L21E11

L21E10

RCV port control

6BH

SRCV11

SRCV10

TRCV2

ORCV1

PRCV1

CBLF

ORCV2

PRCV2

Trigger control

6CH

HTRIG7

HTRIG6

HTRIG5

HTRIG4

HTRIG3

HTRIG2

HTRIG1

HTRIG0

Trigger control

6DH

HTRIG10

HTRIG9

HTRIG8

VTRIG4

VTRIG3

VTRIG2

VTRIG1

VTRIG0

Multi control

6EH

SBLBN

BLCKON

PHRES1

PHRES0

LDEL1

LDEL0

FLC1

FLCO

Closed caption, teletext enable

6FH

CCEN1

CCEN0

TTXEN

SCCLN4

SCCLN3

SCCLN2

SCCLN1

SCCLN0

RCV2 output start

70H

RCV2S7

RCV2S6

RCV2S5

RCV2S4

RCV2S3

RCV2S2

RCV2S1

RCV2S0

RCV2 output end

71H

RCV2E7

RCV2E6

RCV2E5

RCV2E4

RCV2E3

RCV2E2

RCV2E1

RCV2E0

MSBs RCV2 output

72H

RCV2E10

RCV2E9

RCV2E8

RCV2S10

RCV2S9

RCV2S8

TTX request H start

73H

TTXHS7

TTXHS6

TTXHS5

TTXHS4

TTXHS3

TTXHS2

TTXHS1

TTXHS0

TTX request H delay, length

74H

TTXHL3

TTXHL2

TTXHL1

TTXHL0

TTXHD3

TTXHD2

TTXHD1

TTXHD0

CSYNC advance, Vsync shift

75H

CSYNCA4 CSYNCA3 CSYNCA2 CSYNCA1 CSYNCA0

VS_S2

VS_S1

VS_S0

TTX odd request vertical start

76H

TTXOVS7

TTXOVS6

TTXOVS5

TTXOVS4

TTXOVS3

TTXOVS2

TTXOVS1

TTXOVS0

TTX odd request vertical end

77H

TTXOVE7

TTXOVE6

TTXOVE5

TTXOVE4

TTXOVE3

TTXOVE2

TTXOVE1

TTXOVE0

TTX even request vertical start

78H

TTXEVS7

TTXEVS6

TTXEVS5

TTXEVS4

TTXEVS3

TTXEVS2

TTXEVS1

TTXEVS0

TTX even request vertical end

79H

TTXEVE7

TTXEVE6

TTXEVE5

TTXEVE4

TTXEVE3

TTXEVE2

TTXEVE1

TTXEVE0

First active line

7AH

FAL7

FAL6

FAL5

FAL4

FAL3

FAL2

FAL1

FAL0

Last active line

7BH

LAL7

LAL6

LAL5

LAL4

LAL3

LAL2

LAL1

LAL0

TTX mode, MSB vertical

7CH

TTX60

LAL8

TTXO

FAL8

TTXEVE8

TTXOVE8

TTXEVS8

TTXOVS8

Null

7DH

Disable TTX line

7EH

LINE12

LINE11

LINE10

LINE9

LINE8

LINE7

LINE6

LINE5

Disable TTX line

7FH

LINE20

LINE19

LINE18

LINE17

LINE16

LINE15

LINE14

LINE13

REGISTER FUNCTION

SUB ADDR

(HEX)

DATA BYTE

(1)

1999 May 31

Philips Semiconductors

Product specification

Digital video encoder

SAA7126H; SAA7127H

C-bus format

Table 4

C-bus address; see Table 5

Table 5

Explanation of Table 4

Notes

1. X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read.

2. If more than 1 byte of DATA is transmitted, then auto-increment of the subaddress is performed.

Slave receiver

Table 6

Subaddresses 26H and 27H

Table 7

Subaddress 28H

SLAVE ADDRESS

ACK

SUBADDRESS

ACK

DATA 0

ACK

--------

DATA n

ACK

PART

DESCRIPTION

START condition

Slave address

1 0 0 0 1 0 0 X or 1 0 0 0 1 1 0 X; note 1

ACK

acknowledge, generated by the slave

Subaddress; note 2

subaddress byte

DATA

data byte

--------

continued data bytes and ACKs

STOP condition

DATA BYTE

LOGIC

LEVEL

DESCRIPTION

WSS

wide screen signalling bits

3 to 0 = aspect ratio

7 to 4 = enhanced services

10 to 8 = subtitles

13 to 11 = reserved

WSSON

wide screen signalling output is disabled; default after reset

wide screen signalling output is enabled

DATA BYTE

LOGIC

LEVEL

DESCRIPTION

REMARKS

starting point of burst in clock cycles

PAL: BS = 33 (21H); default after reset

NTSC: BS = 25 (19H)

DECCOL

disable colour detection bit of RTCI input

enable colour detection bit of RTCI input

bit RTCE must be set to logic 1 (see Fig.13)

DECFIS

field sequence as FISE in subaddress 61

field sequence as FISE bit in RTCI input

bit RTCE must be set to logic 1 (see Fig.13)

1999 May 31

Philips Semiconductors

Product specification

Digital video encoder

SAA7126H; SAA7127H

Table 8

Subaddress 29H

Table 9

Subaddresses 2AH to 2CH

Table 10 Subaddress 2DH

DATA BYTE

LOGIC

LEVEL

DESCRIPTION

REMARKS

ending point of burst in clock cycles

PAL: BE = 29 (1DH); default after reset

NTSC: BE = 29 (1DH)

SRES

pin 19 is Real-Time Control Input (RTCI)

pin 19 is Sync Reset input (SRES)

a HIGH impulse resets synchronization of the
encoder (first field, first line)

DATA BYTE

LOGIC

LEVEL

DESCRIPTION

LSB of the respective bytes are encoded immediately after run-in, the MSBs of the
respective bytes have to carry the CRCC bits, in accordance with the definition of copy
generation management system encoding format.

CGEN

copy generation data output is disabled; default after reset

copy generation data output is enabled

DATA BYTE

LOGIC

LEVEL

DESCRIPTION

BTRI

DAC for BLUE output in 3-state mode (high-impedance)

DAC for BLUE output in normal operation mode; default after reset

GTRI

DAC for GREEN output in 3-state mode (high-impedance)

DAC for GREEN output in normal operation mode; default after reset

RTRI

DAC for RED output in 3-state mode (high-impedance)

DAC for RED output in normal operation mode; default after reset

CVBSTRI

DAC for CVBS output in 3-state mode (high-impedance)

DAC for CVBS output in normal operation mode; default after reset

CEN

RED output signal is switched to R DAC; default after reset

chrominance output signal is switched to R DAC

CVBSEN

BLUE output signal is switched to B DAC; default after reset

CVBS output signal is switched to B DAC

VBSEN0

if CSYNC = 0, CVBS output signal is switched to CVBS DAC; default after reset

if CSYNC = 0, luminance (VBS) output signal is switched to CVBS DAC

VBSEN1

GREEN output signal is switched to G DAC; default after reset

luminance (VBS) output signal is switched to G DAC

1999 May 31

Philips Semiconductors

Product specification

Digital video encoder

SAA7126H; SAA7127H

Table 11 Subaddresses 38H and 39H

Table 12 Subaddress 3AH

Table 13 Subaddress 54H

DATA BYTE

DESCRIPTION

GY0 to GY4

gain luminance of RGB (Cr, Y and Cb) output, ranging from (1

) to (1 +

Suggested nominal value =

6 (11010b), depending on external application.

GCD0 to GCD4

gain colour difference of RGB (Cr, Y and Cb) output, ranging from (1

) to (1 +

Suggested nominal value =

6 (11010b), depending on external application.

DATA BYTE

LOGIC

LEVEL

DESCRIPTION

MP2C1

input data is twos complement from MP1 input port (encoder path)

input data is straight binary from MP1 input port; default after reset

MP2C2

input data is twos complement from MP2 input port (RGB path)

input data is straight binary from MP2 input port; default after reset

CSYNC

If VBSEN0 = 0, CVBS output signal is switched to CVBS DAC.
If VBSEN0 = 1, luminance output signal is switched to CVBS DAC; default after reset.

advanced composite sync is switched to CVBS DAC

DEMOFF

Y, Cb and Cr for RGB dematrix is active; default after reset

Y, Cb and Cr for RGB dematrix is bypassed

SYMP

horizontal and vertical trigger is taken from RCV2 and RCV1 respectively; default after reset

horizontal and vertical trigger is decoded out of

"CCIR 656" compatible data at MP port

CBENB

data from input ports is encoded; default after reset

colour bar with fixed colours is encoded

DATA BYTE

LOGIC

LEVEL

DESCRIPTION

EDGE1

MP1 data is sampled on the rising clock edge; default after reset

MP1 data is sampled on the falling clock edge

EDGE2

MP2 data is sampled on the rising clock edge; default after reset

MP2 data is sampled on the falling clock edge

CCIRS

If SYMP = 1, horizontal and vertical trigger is decoded out of

"CCIR 656" compatible data at

MP2 port; default after reset.

If SYMP = 1, horizontal and vertical trigger is decoded out of

"CCIR 656" compatible data at

MP1 port.

VPSEN

video programming system data insertion is disabled; default after reset

video programming system data insertion in line 16 is enabled

1999 May 31

Philips Semiconductors

Product specification

Digital video encoder

SAA7126H; SAA7127H

Table 14 Subaddresses 55H to 59H

Table 15 Subaddress 5AH

Table 16 Subaddresses 5BH and 5DH

Table 17 Subaddresses 5CH and 5EH

DATA BYTE

DESCRIPTION

REMARKS

VPS5

fifth byte of video programming system data

LSBs of the respective bytes are encoded
immediately after run-in and framing code in
line 16; all other bytes are not relevant for
VPS

VPS11

eleventh byte of video programming system data

VPS12

twelfth byte of video programming system data

VPS13

thirteenth byte of video programming system data

VPS14

fourteenth byte of video programming system data

DATA BYTE

DESCRIPTION

VALUE

RESULT

CHPS

phase of encoded colour subcarrier
(including burst) relative to horizontal
sync; can be adjusted in steps of
360/256 degrees

6BH

PAL-B/G and data from input ports

95H

PAL-B/G and data from look-up table

A3H

NTSC-M and data from input ports

46H

NTSC-M and data from look-up table

DATA BYTE

DESCRIPTION

CONDITIONS

REMARKS

GAINU

variable gain for
Cb signal; input
representation in
accordance with
"CCIR 601"

white-to-black = 92.5 IRE

GAINU =

2.17

nominal to +2.16

nominal

GAINU = 0

output subcarrier of U contribution = 0

GAINU = 118 (76H)

output subcarrier of U contribution = nominal

white-to-black = 100 IRE

GAINU =

2.05

nominal to +2.04

nominal

GAINU = 0

output subcarrier of U contribution = 0

GAINU = 125 (7DH)

output subcarrier of U contribution = nominal

DATA BYTE

DESCRIPTION

CONDITIONS

REMARKS

GAINV

variable gain for
Cr signal; input
representation in
accordance with
"CCIR 601"

white-to-black = 92.5 IRE

GAINV =

1.55

nominal to +1.55

nominal

GAINV = 0

output subcarrier of V contribution = 0

GAINV = 165 (A5H)

output subcarrier of V contribution = nominal

white-to-black = 100 IRE

GAINV =

1.46

nominal to +1.46

nominal

GAINV = 0

output subcarrier of V contribution = 0

GAINV = 175 (AFH)

output subcarrier of V contribution = nominal

1999 May 31

Philips Semiconductors

Product specification

Digital video encoder

SAA7126H; SAA7127H

Table 18 Subaddress 5DH

Notes

1. Output black level/IRE = BLCKL

2/6.29 + 28.9.

2. Output black level/IRE = BLCKL

2/6.18 + 26.5.

Table 19 Subaddress 5EH

Notes

1. Output black level/IRE = BLNNL

2/6.29 + 25.4.

2. Output black level/IRE = BLNNL

2/6.18 + 25.9; default after reset: 35H.

Table 20 Subaddress 5FH

DATA BYTE

DESCRIPTION

CONDITIONS

REMARKS

BLCKL

variable black level; input
representation in
accordance with
"CCIR 601"

white-to-sync = 140 IRE;
note 1

recommended value: BLCKL = 58 (3AH)

BLCKL = 0; note 1

output black level = 29 IRE

BLCKL = 63 (3FH); note 1

output black level = 49 IRE

white-to-sync = 143 IRE;
note 2

recommended value: BLCKL = 51 (33H)

BLCKL = 0; note 2

output black level = 27 IRE

BLCKL = 63 (3FH); note 2

output black level = 47 IRE

DECOE

real-time control

logic 0

disable odd/even field control bit from RTCI

logic 1

enable odd/even field control bit from RTCI
(see Fig.13)

DATA BYTE

DESCRIPTION

CONDITIONS

REMARKS

BLNNL

variable blanking level

white-to-sync = 140 IRE;
note 1

recommended value: BLNNL = 46 (2EH)

BLNNL = 0; note 1

output blanking level = 25 IRE

BLNNL = 63 (3FH); note 1

output blanking level = 45 IRE

white-to-sync = 143 IRE;
note 2

recommended value: BLNNL = 53 (35H)

BLNNL = 0; note 2

output blanking level = 26 IRE

BLNNL = 63 (3FH); note 2

output blanking level = 46 IRE

DECPH

real-time control

logic 0

disable subcarrier phase reset bit from RTCI

logic 1

enable subcarrier phase reset bit from RTCI
(see Fig.13)

DATA BYTE

DESCRIPTION

BLNVB

variable blanking level during vertical blanking interval is typically identical to value of BLNNL

CCRS

select cross-colour reduction filter in luminance; see Table 21

1999 May 31

Philips Semiconductors

Product specification

Digital video encoder

SAA7126H; SAA7127H

Table 21 Logic levels and function of CCRS

Table 22 Subaddress 61H

Table 23 Subaddress 62AH

CCRS1

CCRS0

DESCRIPTION

no cross-colour reduction; for overall transfer characteristic of luminance see Fig.5

cross-colour reduction #1 active; for overall transfer characteristic see Fig.5

cross-colour reduction #2 active; for overall transfer characteristic see Fig.5

cross-colour reduction #3 active; for overall transfer characteristic see Fig.5

DATA BYTE

LOGIC

LEVEL

DESCRIPTION

FISE

864 total pixel clocks per line; default after reset

858 total pixel clocks per line

PAL

NTSC encoding (non-alternating V component)

PAL encoding (alternating V component); default after reset

SCBW

enlarged bandwidth for chrominance encoding (for overall transfer characteristic of
chrominance in baseband representation see Figs 3 and 4)

standard bandwidth for chrominance encoding (for overall transfer characteristic of
chrominance in baseband representation see Figs 3 and 4); default after reset

YGS

luminance gain for white

black 100 IRE; default after reset

luminance gain for white

black 92.5 IRE including 7.5 IRE set-up of black

INPI

PAL switch phase is nominal; default after reset

PAL switch phase is inverted compared to nominal if RTC is enabled (see Table 23)

DOWNA

DAC for CVBS in normal operational mode; default after reset

DAC for CVBS forced to lowest output voltage

DOWNB

DACs for R, G and B in normal operational mode

DACs for R, G and B forced to lowest output voltage; default after reset

DATA BYTE

LOGIC

LEVEL

DESCRIPTION

RTCE

no real-time control of generated subcarrier frequency; default after reset

real-time control of generated subcarrier frequency through SAA7151B or SAA7111; for
timing see Fig.13

1999 May 31

Philips Semiconductors

Product specification

Digital video encoder

SAA7126H; SAA7127H

Table 24 Subaddress 62BH

Table 25 Subaddresses 63H to 66H (four bytes to program subcarrier frequency)

Note

1. Examples:

a) NTSC-M: f

fsc

= 227.5, f

llc

= 1716

FSC = 569408543 (21F07C1FH).

b) PAL-B/G: f

fsc

= 283.7516, f

llc

= 1728

FSC = 705268427 (2A098ACBH).

Table 26 Subaddresses 67H to 6AH

DATA BYTE

DESCRIPTION

CONDITIONS

REMARKS

BSTA

amplitude of colour burst;
input representation in
accordance with
"CCIR 601"

white-to-black = 92.5 IRE;
burst = 40 IRE; NTSC encoding

recommended value:
BSTA = 63 (3FH)

BSTA = 0 to 2.02

nominal

white-to-black = 92.5 IRE;
burst = 40 IRE; PAL encoding

recommended value:
BSTA = 45 (2DH)

BSTA = 0 to 2.82

nominal

white-to-black = 100 IRE;
burst = 43 IRE; NTSC encoding

recommended value:
BSTA = 67 (43H)

BSTA = 0 to 1.90

nominal

white-to-black = 100 IRE;
burst = 43 IRE; PAL encoding

recommended value:
BSTA = 47 (2FH); default after
reset

BSTA = 0 to 3.02

nominal

DATA BYTE

DESCRIPTION

CONDITIONS

REMARKS

FSC0 to FSC3

fsc

= subcarrier frequency

(in multiples of line
frequency); f

llc

= clock

frequency (in multiples of
line frequency)

;

note 1

FSC3 = most significant byte;
FSC0 = least significant byte

DATA BYTE

DESCRIPTION

REMARKS

L21O0

first byte of captioning data, odd field

LSBs of the respective bytes are encoded
immediately after run-in and framing code, the
MSBs of the respective bytes have to carry the
parity bit, in accordance with the definition of
line 21 encoding format.

L21O1

second byte of captioning data, odd field

L21E0

first byte of extended data, even field

L21E1

second byte of extended data, even field

FSC

round

fsc

llc

--------

1999 May 31

Philips Semiconductors

Product specification

Digital video encoder

SAA7126H; SAA7127H

Table 27 Subaddress 6BH

Table 28 Logic levels and function of SRCV1

Table 29 Subaddresses 6CH and 6DH

DATA BYTE

LOGIC

LEVEL

DESCRIPTION

PRCV2

polarity of RCV2 as output is active HIGH, rising edge is taken when input, respectively;
default after reset

polarity of RCV2 as output is active LOW, falling edge is taken when input, respectively

ORCV2

pin RCV2 is switched to input; default after reset

pin RCV2 is switched to output

CBLF

If ORCV2 = HIGH, pin RCV2 provides an HREF signal (horizontal reference pulse that is
defined by RCV2S and RCV2E, also during vertical blanking interval); default after reset.
If ORCV2 = LOW and bit SYMP = LOW, the signal input to RCV2 is used for horizontal
synchronization only (if TRCV2 = 1); default after reset.

If ORCV2 = HIGH, pin RCV2 provides a `composite-blanking-not' signal, for example a
reference pulse that is defined by RCV2S and RCV2E, excluding vertical blanking interval,
which is defined by FAL and LAL. If ORCV2 = LOW and bit SYMP = LOW, the signal input
to RCV2 is used for horizontal synchronization (if TRCV2 = 1) and as an internal blanking
signal.

PRCV1

polarity of RCV1 as output is active HIGH, rising edge is taken when input; default after
reset

polarity of RCV1 as output is active LOW, falling edge is taken when input

ORCV1

pin RCV1 is switched to input; default after reset

pin RCV1 is switched to output

TRCV2

horizontal synchronization is taken from RCV1 port (at bit SYMP = LOW) or from decoded
frame sync of

"CCIR 656" input (at bit SYMP = HIGH); default after reset

horizontal synchronization is taken from RCV2 port (at bit SYMP = LOW)

SRCV1

defines signal type on pin RCV1; see Table 28

DATA BYTE

AS OUTPUT

AS INPUT

FUNCTION

SRCV11

SRCV10

vertical sync each field; default after reset

frame sync (odd/even)

FSEQ

field sequence, vertical sync every fourth field (PAL = 0)
or eighth field (PAL = 1)

not applicable

DATA BYTE

DESCRIPTION

HTRIG

sets the horizontal trigger phase related to signal on RCV1 or RCV2 input

values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; increasing HTRIG
decreases delays of all internally generated timing signals; reference mark: analog output
horizontal sync (leading slope) coincides with active edge of RCV used for triggering at
HTRIG = 39H

1999 May 31

Philips Semiconductors

Product specification

Digital video encoder

SAA7126H; SAA7127H

Table 30 Subaddress 6DH

Table 31 Subaddress 6EH

Table 32 Logic levels and function of PHRES

Table 33 Logic levels and function of LDEL

Table 34 Logic levels and function of FLC

DATA BYTE

DESCRIPTION

VTRIG

sets the vertical trigger phase related to signal on RCV1 input

increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines;
variation range of VTRIG = 0 to 31 (1FH)

DATA BYTE

LOGIC

LEVEL

DESCRIPTION

SBLBN

vertical blanking is defined by programming of FAL and LAL; default after reset

vertical blanking is forced in accordance with

"CCIR 624" (50 Hz) or RS170A (60 Hz)

BLCKON

encoder in normal operation mode

output signal is forced to blanking level; default after reset

PHRES

selects the phase reset mode of the colour subcarrier generator; see Table 32

LDEL

selects the delay on luminance path with reference to chrominance path; see Table 33

FLC

field length control; see Table 34

DATA BYTE

DESCRIPTION

PHRES1

PHRES0

no reset or reset via RTCI from SAA7111 if bit RTCE = 1; default after reset

reset every two lines

reset every eight fields

reset every four fields

DATA BYTE

DESCRIPTION

LDEL1

LDEL0

no luminance delay; default after reset

1 LLC luminance delay

2 LLC luminance delay

3 LLC luminance delay

DATA BYTE

DESCRIPTION

FLC1

FLC0

interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default after reset

non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz

non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz

1999 May 31

Philips Semiconductors

Product specification

Digital video encoder

SAA7126H; SAA7127H

Table 35 Subaddress 6FH

Table 36 Logic levels and function of CCEN

Table 37 Subaddresses 70H to 72H

Table 38 Subaddress 73H

Table 39 Subaddress 74H

DATA BYTE

LOGIC

LEVEL

DESCRIPTION

CCEN

enables individual line 21 encoding; see Table 36

TTXEN

disables teletext insertion; default after reset

enables teletext insertion

SCCLN

selects the actual line, where closed caption or extended data are encoded;
line = (SCCLN + 4) for M-systems; line = (SCCLN + 1) for other systems

DATA BYTE

DESCRIPTION

CCEN1

CCEN0

line 21 encoding off; default after reset

enables encoding in field 1 (odd)

enables encoding in field 2 (even)

enables encoding in both fields

DATA BYTE

DESCRIPTION

RCV2S

start of output signal on RCV2 pin

values above 1715 (FISE = 1) or [1727 (FISE = 0)] are not allowed; first active pixel at analog
outputs (corresponding input pixel coinciding with RCV2) at RCV2S = 11AH [0FDH]

RCV2E

end of output signal on RCV2 pin

values above 1715 (FISE = 1) or [1727 (FISE = 0)] are not allowed; last active pixel at analog
outputs (corresponding input pixel coinciding with RCV2) at RCV2E = 694H (687H)

DATA BYTE

DESCRIPTION

REMARKS

TTXHS

start of signal on pin TTXRQ; see Fig.14

PAL: TTXHS = 42H

NTSC: TTXHS = 54H

DATA BYTE

DESCRIPTION

REMARKS

TTXHL

length of TTXRQ window; only active at old TTX protocol:
bit TTXO = 1

TTXHL = 0: TTXRQ = 1398LLC;
TTXHL = 15: TTXRQ = 1413LLC

TTXHD

indicates the delay in clock cycles between rising edge of TTXRQ
output and valid data at pin TTX

minimum value: TTXHD = 2

1999 May 31

Philips Semiconductors

Product specification

Digital video encoder

SAA7126H; SAA7127H

Table 40 Subaddress 75H

Table 41 Subaddresses 76H, 77H and 7CH

Table 42 Subaddresses 78H, 79H and 7CH

Table 43 Subaddress 7CH

Table 44 Subaddresses 7AH to 7CH

DATA BYTE

DESCRIPTION

VS_S

vertical sync shift between RCV1 and RCV2 (switched to output); in master mode it is possible to shift
H-sync (RCV2; CBLF = 0) against V-sync (RCV1; SRCV1 = 00)

standard value: VS_S = 3

CSYNCA

advanced composite sync against RGB output from 0LLC to 31LLC

DATA BYTE

DESCRIPTION

REMARKS

TTXOVS

first line of occurrence of signal on pin TTXRQ in odd field

PAL: TTXOVS = 05H;
NTSC: TTXOVS = 06H

line = (TTXOVS + 4) for M-systems

line = (TTXOVS + 1) for other systems

TTXOVE

last line of occurrence of signal on pin TTXRQ in odd field

PAL: TTXOVE = 16H;
NTSC: TTXOVE = 10H

line = (TTXOVE + 3) for M-systems

line = TTXOVE for other systems

DATA BYTE

DESCRIPTION

REMARKS

TTXEVS

first line of occurrence of signal on pin TTXRQ in even field

PAL: TTXEVS = 04H;
NTSC: TTXEVS = 05H

line = (TTXEVS + 4) for M-systems

line = (TTXEVS + 1) for other systems

TTXEVE

last line of occurrence of signal on pin TTXRQ in even field

PAL: TTXEVS = 16H;
NTSC: TTXEVS = 10H

line = (TTXEVE + 3) for M-systems

line = TTXEVE for other systems

DATA BYTE

LOGIC

LEVEL

DESCRIPTION

TTXO

new TTX protocol selected: at each rising edge of TTXRQ a single TTX bit is requested
see Fig.14; default after reset

old TTX protocol selected: the encoder provides a window of TTXRQ going HIGH; the
length of the window depends on the chosen TTX standard see Fig.14

TTX60

enables NABTS (FISE = 1) or European TTX (FISE = 0); default after reset

enables world standard teletext 60 Hz (FISE = 1)

DATA BYTE

DESCRIPTION

FAL

first active line = FAL + 4 for M-systems, = FAL + 1 for other systems, measured in lines

FAL = 0 coincides with the first field synchronization pulse

LAL

last active line = LAL + 3 for M-systems, = LAL for other system, measured in lines

LAL = 0 coincides with the first field synchronization pulse

1999 May 31

Philips Semiconductors

Product specification

Digital video encoder

SAA7126H; SAA7127H

Table 45 Subaddresses 7EH and 7FH

In subaddresses 5BH, 5CH, 5DH, 5EH and 62H all IRE values are rounded up.

Slave transmitter

Table 46 Slave transmitter (slave address 89H)

Table 47 Subaddress 00H

DATA BYTE

DESCRIPTION

LINE

individual lines in both fields (PAL counting) can be disabled for insertion of teletext by the respective
bits, disabled line = LINExx (50 Hz field rate)

this bit mask is effective only, if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE

SUBADDRESS

DATA BYTE

Status byte

00H

VER2

VER1

VER0

CCRDO

CCRDE

FSEQ

O_E

DATA BYTE

LOGIC

LEVEL

DESCRIPTION

VER

version identification of the device: it will be changed with all versions of the IC that have
different programming models; current version is 000 binary

CCRDO

closed caption bytes of the odd field have been encoded

the bit is reset after information has been written to the subaddresses 67H and 68H; it is
set immediately after the data has been encoded

CCRDE

closed caption bytes of the even field have been encoded

the bit is reset after information has been written to the subaddresses 69H and 6AH; it is
set immediately after the data has been encoded

FSEQ

during first field of a sequence (repetition rate: NTSC = 4 fields, PAL = 8 fields)

not first field of a sequence

O_E

during even field

during odd field

1999 May 31

Philips Semiconductors

Product specification

Digital video encoder

SAA7126H; SAA7127H

CHARACTERISTICS

DDD

= 3.0 to 3.6 V; T

amb

= 0 to 70

C; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

Supplies

DDA

analog supply voltage

3.15

3.45

DDD

digital supply voltage

3.0

3.6

DDA

analog supply current

note 1

100

DDD

digital supply current

DDD

= 3.3 V; note 1

Inputs

LOW-level input voltage (pins LLC1, RCV1,
RCV2, MP7 to MP0, RTCI, SA, RESET
and TTX)

0.5

+0.8

HIGH-level input voltage (pins LLC1, RCV1,
RCV2, MP7 to MP0, RTCI, SA, RESET
and TTX)

2.0

DDD

+ 0.3

input leakage current

input capacitance

clocks

data

I/Os at high-impedance

Outputs; pins RCV1, RCV2 and TTXRQ

LOW-level output voltage

= 2 mA

0.4

HIGH-level output voltage

= 2 mA

2.4

C-bus; SDA and SCL

LOW-level input voltage

0.5

0.3V

DD(I2C)

HIGH-level input voltage

0.7V

DD(I2C)

+ 0.3 V

input current

= LOW or HIGH

+10

LOW-level output voltage (pin SDA)

= 3 mA

0.4

output current

during acknowledge

Clock timing (pins LLC1 and XCLK)

LLC1

cycle time

note 2

duty factor t

HIGH

LLC1

LLC1 input

duty factor t

HIGH

XCLK

XCLK output typical
50%

rise time

note 2

fall time

note 2

Input timing; pins LLC1, RCV1, RCV2, MP7 to MP0, RTCI, SA and TTX

SU;DAT

input data set-up time

HD;DAT

input data hold time

Crystal oscillator

nominal frequency (usually 27 MHz)

3rd-harmonic

MHz

f/f

permissible deviation of nominal frequency

note 3

+50

1999 May 31

Philips Semiconductors

Product specification

Digital video encoder

SAA7126H; SAA7127H

Notes

1. At maximum supply voltage with highly active input signals.

2. The data is for both input and output direction.

3. If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of

subcarrier frequency and line/field frequency.

4. For full digital range, without load, V

DDA

= 3.3 V. The typical voltage swing is 1.45 V, the typical minimum output

voltage (digital zero at DAC) is 0.2 V.

RYSTAL SPECIFICATION

amb

ambient temperature

load capacitance

series resistance

motional capacitance (typical)

1.5

20% 1.5 + 20%

parallel capacitance (typical)

3.5

20% 3.5 + 20%

Data and reference signal output timing

output load capacitance

7.5

output hold time

output delay time

CVBS and RGB outputs

o(p-p)

output signal voltage (peak-to-peak value)

note 4

1.30

1.55

inequality of output signal voltages

s(int)

internal serial resistance

output load resistance

300

output signal bandwidth of DACs

3 dB

MHz

lf(i)

low frequency integral linearity error of DACs

LSB

lf(d)

low frequency differential linearity error of
DACs

LSB

d(pipe)(MP)

total pipeline delay from MP port

27 MHz

LLC

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

1999 May 31

Philips Semiconductors

Product specification

Digital video encoder

SAA7126H; SAA7127H

Explanation of RTCI data bits

1. The HPLL increment is not evaluated by SAA7126H; SAA7127H.

2. The SAA7126H; SAA7127H generates the subcarrier frequency from the FSCPLL increment if enabled (see item 7.).

3. The PAL bit indicates the line with inverted (R

Y) component of colour difference signal.

4. If the reset bit is enabled (RTCE = 1; DECPH = 1; PHRES = 00), the phase of the subcarrier is reset in each line

whenever the reset bit of RTCI input is set to logic 1.

5. If the FISE bit is enabled (RTCE = 1; DECFIS = 1), the SAA7126H; SAA7127H takes this bit instead of the FISE bit

in subaddress 61H.

6. If the odd/even bit is enabled (RTCE = 1; DECOE = 1), the SAA7126H; SAA7127H ignores it's internally generated

odd/even flag and takes the odd/even bit from RTCI input.

7. If the colour detection bit is enabled (RTCE = 1; DECCOL = 1) and no colour was detected (colour detection bit = 0),

the subcarrier frequency is generated by the SAA7126H; SAA7127H. In the other case (colour detection bit = 1) the
subcarrier frequency is evaluated out of FSCPLL increment.

If the colour detection bit is disabled (RTCE = 1; DECCOL = 0), the subcarrier frequency is evaluated out of FSCPLL
increment, independent of the colour detection bit of RTCI input.

Fig.13 RTCI timing.

(1) SAA7111/12 provides 14 to 0 bits, resulting in 2 reserved bits before FSCPLL increment.

(2) SAA7151 provides 21 to 0 bits only, resulting in 5 reserved bits before sequence bit.

(3) Sequence bit: PAL: 0 = (R

Y) line normal, 1 = (R

Y) line inverted; NTSC: 0 = no change.

(4) Reset bit: only from SAA7111 and SAA7112 decoder.

(5) FISE bit: 0 = 50 Hz, 1 = 60 Hz.

(6) Odd/even bit: odd_even from external.

(7) Colour detection: 0 = no colour detected, 1 = colour detected.

(8) Reserved bits: 229 with 50 Hz systems, 226 with 60 Hz systems.

handbook, full pagewidth

128

69 72 74

0 1

RTCI

HPLL

increment

(1)

FSCPLL increment

(2)

H/L transition

count start

4 bits

reserved

valid

sample

invalid

sample

not used in SAA7126H/27H

3 bits

reserved

8/LLC

MHB503

LOW

time slot:

(3)

(4)

(6)

(7)

(8)

(5)

1999 May 31

Philips Semiconductors

Product specification

Digital video encoder

SAA7126H; SAA7127H

Teletext timing

Time t

is the time needed to interpolate input data TTX

and insert it into the CVBS and VBS output signal, such
that it appears at t

TTX

= 9.78

s (PAL) or t

TTX

= 10.5

(NTSC) after the leading edge of the horizontal
synchronization pulse.

Time t

d(pipe)(MP)

is the pipeline delay time introduced by the

source that is gated by TTXRQ in order to deliver TTX
data. This delay is programmable by register TTXHD. For
every active HIGH state at output pin TTXRQ, a new
teletext bit must be provided by the source (new protocol)
or a window of TTXRQ going HIGH is provided and the
number of teletext bits, depending on the chosen TTX
standard, is requested at input pin TTX (old protocol).

Since the beginning of the pulses representing the TTXRQ
signal and the delay between the rising edge of TTXRQ
and valid teletext input data are fully programmable
(TTXHS and TTXHD), the TTX data is always inserted at
the correct position after the leading edge of outgoing
horizontal synchronization pulse.

Time t

i(TTXW)

is the internally used insertion window for

TTX data; it has a constant length that allows insertion of
360 teletext bits at a text data rate of 6.9375 Mbits/s
(PAL), 296 teletext bits at a text data rate of 5.7272 Mbits/s
(world standard TTX) or 288 teletext bits at a text data rate
of 5.7272 Mbits/s (NABTS). The insertion window is not
opened if the control bit TTXEN is zero.

Using appropriate programming, all suitable lines of the
odd field (TTXOVS and TTXOVE) plus all suitable lines of
the even field (TTXEVS and TTXEVE) can be used for
teletext insertion.

Fig.14 Teletext timing.

handbook, full pagewidth

ti(TTXW)

tTTX

tPD

tFD

CVBS/Y

TTX

TTXRQ (new)

TTXRQ (old)

text bit #:

10 11

18 19 20

MHB504

1999

May

Philips Semiconductors

Product specification

Digital video encoder

SAA7126H; SAA7127H

This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...

APPLICA

TION INFORMA

TION

ok, full pagewidth

(1)

AGND

RED

DAC1

DAC2

DAC3

UR
0.70 V (p-p)

(2)

AGND

GREEN

UG
0.70 V (p-p)

(2)

MHB505

AGND

DGND

BLUE

UB
0.70 V (p-p)

(2)

AGND

22, 32, 33

5, 18, 38

VDDA1 to VDDA3

3.3 V analog

3.3 V digital

VSSD1 to VSSD3

VDDD1 to VDDD3

VSSA1 to VSSA3

25, 28, 31

6, 17, 39

XTALI

XTAL

10 pF

use one capacitor
for each VDDD

use one capacitor
for each VDDA

(1)

VDDA4

(1)

DAC4

4.7

AGND

CVBS

UCVBS
1.23 V (p-p)

(2)

(1)

0.1

AGND

0.1

DGND

0.1

1 nF

3rd harmonic

27.0 MHz

digital

inputs and

outputs

SAA7126H
SAA7127H

Fig.15 Application circuit.

(1) Typical value.

(2) For

100

colour bar.

1999 May 31

Philips Semiconductors

Product specification

Digital video encoder

SAA7126H; SAA7127H

SOLDERING

Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"Data Handbook IC26; Integrated Circuit Packages"

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250

C. The top-surface temperature of the

packages should preferable be kept below 230

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

For packages with leads on two sides and a pitch (e):

larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

For packages with leads on four sides, the footprint must
be placed at a 45

angle to the transport direction of the

printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320

1999 May 31

Philips Semiconductors

Product specification

Digital video encoder

SAA7126H; SAA7127H

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

"Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods".

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45

angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

PACKAGE

SOLDERING METHOD

WAVE

REFLOW

(1)

BGA, SQFP

not suitable

suitable

HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable

(2)

suitable

PLCC

(3)

, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended

(3)(4)

suitable

SSOP, TSSOP, VSO

not recommended

(5)

suitable

1999 May 31

Philips Semiconductors

Product specification

Digital video encoder

SAA7126H; SAA7127H

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PURCHASE OF PHILIPS I

C COMPONENTS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I

C components conveys a license under the Philips' I

C patent to use the

components in the I

C system provided the system conforms to the I

C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

SCA

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

1999

Philips Semiconductors a worldwide company

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811

Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341

Pakistan: see Singapore

Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327

Portugal: see Spain

Romania: see Italy

Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919

Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Tel. +65 350 2538, Fax. +65 251 6500

Slovakia: see Austria

Slovenia: see Italy

South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. +27 11 471 5401, Fax. +27 11 471 5398

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382

Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793

Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087

Uruguay: see South America

Vietnam: see Singapore

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 62 5344, Fax.+381 11 63 5777

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

Argentina: see South America

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210

Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773

Belgium: see The Netherlands

Brazil: see South America

Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 68 9211, Fax. +359 2 68 9102

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381, Fax. +1 800 943 0087

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700

Colombia: see South America

Czech Republic: see Austria

Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,
Tel. +45 33 29 3333, Fax. +45 33 29 3905

Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615 800, Fax. +358 9 6158 0920

France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 4099 6161, Fax. +33 1 4099 6427

Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 2353 60, Fax. +49 40 2353 6300

Hungary: see Austria

India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966

Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 02 67 52 2531, Fax. +39 02 67 52 2557

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087

Middle East: see Italy

Printed in The Netherlands

545006/01/pp40

Date of release: 1999 May 31

Document order number:

9397 750 05278

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SAA7127

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SAA7127