2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

CONTENTS

FEATURES

GENERAL DESCRIPTION

ORDERING INFORMATION

QUICK REFERENCE DATA

BLOCK DIAGRAM

PINNING

FUNCTIONAL DESCRIPTION

7.1

Versatile fader

7.2

Data manager

7.3

Encoder

7.4

RGB processor

7.5

SECAM processor

7.6

Output interface/DACs

7.7

Synchronization

7.8

Clock

7.9

C-bus interface

7.10

Input levels and formats

7.11

Bit allocation map

7.12

C-bus format

7.13

Slave receiver

7.14

Slave transmitter

CHARACTERISTICS

8.1

Explanation of RTCI data bits

8.2

Teletext timing

APPLICATION INFORMATION

9.1

Analog output voltages

PACKAGE OUTLINE

SOLDERING

11.1

Introduction to soldering surface mount
packages

11.2

Reflow soldering

11.3

Wave soldering

11.4

Manual soldering

11.5

Suitability of surface mount IC packages for
wave and reflow soldering methods

REVISION HISTORY

DATA SHEET STATUS

DEFINITIONS

DISCLAIMERS

PURCHASE OF PHILIPS I

C COMPONENTS

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

FEATURES

Monolithic CMOS 3.3 V device, 5 V I

C-bus optional

Digital PAL/NTSC/SECAM encoder

System pixel frequency 13.5 MHz

54 MHz double-speed multiplexed D1 interface capable
of splitting data into two separate channels (encoded
and baseband)

Three Digital-to-Analog Converters (DACs) for CVBS
(CSYNC), VBS (CVBS) and C (CVBS) two times
oversampled with 10-bit resolution (signals in brackets
optional)

Three DACs for RED (C

), GREEN (Y) and BLUE (C

)

two times oversampled with 9-bit resolution (signals in
brackets optional)

Alternatively, an advanced composite sync is available
on the CVBS output for RGB display centring

Real-time control of subcarrier

Cross-colour reduction filter

Closed captioning encoding and World Standard
Teletext (WST) and North-American Broadcast Text
System (NABTS) teletext encoding including sequencer
and filter

Copy Generation Management System (CGMS)
encoding (CGMS described by standard CPR-1204 of
EIAJ); 20 bits in lines 20/283 (NTSC) can be loaded via
I

C-bus

Fast I

C-bus control port (400 kHz)

Line 23 Wide Screen Signalling (WSS) encoding

Video Programming System (VPS) data encoding in
line 16 (50/625 lines counting)

Encoder can be master or slave

Programmable horizontal and vertical input
synchronization phase

Programmable horizontal sync output phase

Internal Colour Bar Generator (CBG)

Macrovision

(1)

Pay-per-View copy protection system

rev. 7.01 and rev. 6.1 as option; this applies to
SAA7128H only. The device is protected by USA patent
numbers 4631603, 4577216 and 4819098 and other
intellectual property rights. Use of the Macrovision
anti-copy process in the device is licensed for
non-commercial home use only. Reverse engineering or
disassembly is prohibited. Please contact your nearest
Philips Semiconductors sales office for more information

Controlled rise/fall times of output syncs and blanking

On-chip crystal oscillator (3rd-harmonic or fundamental
crystal)

Down mode (low output voltage) or power-save mode of
DACs

QFP44 package.

GENERAL DESCRIPTION

The SAA7128H; SAA7129H encodes digital C

-Y-C

video data to an NTSC, PAL or SECAM CVBS or S-video
signal. Simultaneously, RGB or bypassed but interpolated
C

-Y-C

signals are available via three additional DACs.

The circuit at a 54 MHz multiplexed digital D1 input port
accepts two ITU-R BT.656 compatible C

-Y-C

data

streams with 720 active pixels per line in
4 : 2 : 2 multiplexed formats, for example MPEG decoded
data with overlay and MPEG decoded data without
overlay, whereas one data stream is latched at the rising,
the other one at the falling clock edge.

It includes a sync/clock generator and on-chip DACs.

(1) Macrovision

is a trademark of the Macrovision Corporation.

ORDERING INFORMATION

TYPE NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

SAA7128H

QFP44

plastic quad flat package; 44 leads (lead length 1.3 mm);
body 10

1.75 mm

SOT307-2

SAA7129H

2002

Oct

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

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BLOCK DIA

GRAM

f
ull pagewidth

MHB572

C-BUS

INTERFACE

SYNC/CLOCK

C-bus control

SCL

VDDA4

SDA

9 to 16

MP7 to MP0

TTX

VDD(I2C)

VDDA3

VDDA2

VDDA1

clock and timing

XTALI

C-bus control

XTALO

RCV1

RCV2

TTXRQ

XCLK

LLC1

RTCI

CVBS
(CSYNC)

VBS
(CVBS)

C
(CVBS)

OUTPUT

INTERFACE

ENCODER

FADER

VSSA1

VSSA2

VSSA3

C-bus

control

VDDD3

VDDD2

VDDD1

VSSD3

VSSD2

VSSD1

MPA

MPB

MPpos

MPneg

SWITCH

C-bus control

RESET

CB-CR

RED

GREEN

BLUE

RGB

PROCESSOR

C-bus control

SAA7128H
SAA7129H

Fig.1 Block diagram.

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

PINNING

SYMBOL

PIN

TYPE

DESCRIPTION

RES

reserved pin; do not connect

test pin; connected to digital ground for normal operation

LLC1

line-locked clock input; this is the 27 MHz master clock

SSD1

supply

digital ground 1

DDD1

supply

digital supply voltage 1

RCV1

I/O

raster control 1 for video port; this pin receives/provides a VS/FS/FSEQ signal

RCV2

I/O

raster control 2 for video port; this pin provides an HS pulse of programmable
length or receives an HS pulse

MP7

double-speed 54 MHz MPEG port; it is an input for

"ITU-R BT.656" style

multiplexed C

-Y-C

data; data is sampled on the rising and falling clock edge;

data sampled on the rising edge is then sent to the encoding part of the device;
data sampled on the falling edge is sent to the RGB part of the device (or vice
versa, depending on programming)

MP6

MP5

MP4

MP3

MP2

MP1

MP0

DDD2

supply

digital supply voltage 2

SSD2

supply

digital ground 2

RTCI

real-time control input; if the LLC1 clock is provided by an SAA7111 or SAA7151B,
RTCI should be connected to the RTCO pin of the respective decoder to improve
the signal quality

DD(I2C)

supply

sense input for I

C-bus voltage; connect to I

C-bus supply

select I

C-bus address; LOW selects slave address 88H, HIGH selects slave

address 8CH

SSA1

supply

analog ground 1 for RED (C

), C (CVBS) and GREEN (Y) outputs

RED

analog output of RED (C

) signal

analog output of chrominance (CVBS) signal

DDA1

supply

analog supply voltage 1 for RED (C

) and C (CVBS) outputs

GREEN

analog output of GREEN (Y) signal

VBS

analog output of VBS (CVBS) signal

DDA2

supply

analog supply voltage 2 for VBS (CVBS) and GREEN (Y) outputs

BLUE

analog output of BLUE (C

) signal

CVBS

analog output of CVBS (CSYNC) signal

DDA3

supply

analog supply voltage 3 for BLUE (C

) and CVBS (CSYNC) outputs

SSA2

supply

analog ground 2 for VBS (CVBS), BLUE (C

) and CVBS (CSYNC) outputs

SSA3

supply

analog ground 3 for the DAC reference ladder and the oscillator

XTALO

crystal oscillator output

XTALI

crystal oscillator input; if the oscillator is not used, this pin should be connected to
ground

DDA4

supply

analog supply voltage 4 for the DAC reference ladder and the oscillator

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

XCLK

clock output of the crystal oscillator

SSD3

supply

digital ground 3

DDD3

supply

digital supply voltage 3

RESET

Reset input, active LOW. After reset is applied, all digital I/Os are in input mode;
PAL black burst on CVBS, VBS and C; RGB outputs set to lowest voltage. The
I

C-bus receiver waits for the START condition.

SCL

C-bus serial clock input

SDA

I/O

C-bus serial data input/output

TTXRQ

teletext request output, indicating when text bits are requested

TTX

teletext bit stream input

SYMBOL

PIN

TYPE

DESCRIPTION

handbook, full pagewidth

SAA7128H
SAA7129H

MHB573

VSSA3

VSSA2

VDDA3

CVBS

VDDA2

VBS

GREEN

VDDA1

RED

RES

LLC1

VSSD1

VDDD1

RCV2

MP7

MP5

BLUE

TTXRQ

SDA

SCL

DDD3

SSD3

DDA4

XTALI

XTALO

TTX

XCLK

MP3

MP2

MP1

MP0

DDD2

SSD2

DD(I2C)

SSA1

MP4

RTCI

RCV1

MP6

RESET

Fig.2 Pin configuration.

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

FUNCTIONAL DESCRIPTION

The digital video encoder encodes digital luminance and
colour difference signals into analog CVBS, S-video and
simultaneously RGB or C

-Y-C

signals. NTSC-M,

PAL-B/G, SECAM and sub-standards are supported.

Both interlaced and non-interlaced operation is possible
for all standards.

The basic encoder function consists of subcarrier
generation and colour modulation and insertion of
synchronization signals. Luminance and chrominance
signals are filtered in accordance with the standard
requirements of

"RS-170-A" and "ITU-R BT.470-3".

For ease of analog post filtering the signals are twice
oversampled with respect to the pixel clock before
digital-to-analog conversion.

The total filter transfer characteristics are illustrated in
Figs 8 to 13. The DACs for Y, C and CVBS are realized
with full 10-bit resolution; 9-bit resolution for RGB output.
The C

-Y-C

to RGB dematrix can be bypassed optionally

in order to provide the upsampled C

-Y-C

input signals.

The 8-bit multiplexed C

-Y-C

formats are

"ITU-R BT.656"

(D1 format) compatible, but the SAV and EAV codes can
be decoded optionally, when the device is operated in
slave mode. Two independent data streams can be
processed, one latched by the rising edge of LLC1, the
other latched by the falling edge of LLC1. The purpose of
that is e.g. to forward one of the data streams containing
both video and On-Screen Display (OSD) information to
the RGB outputs, and the other stream containing video
only to the encoded outputs CVBS and S-video.

For optimum display of RGB signals through a
euro-connector TV set, optionally on the CVBS output an
early composite sync pulse (up to 31 LLC1 clock periods)
can be provided.

As a further alternative, the VBS and C outputs may
provide a second and third CVBS signal.

It is also possible to connect a Philips digital video decoder
(SAA7111, SAA7711A, SAA7112 or SAA7151B) to the
SAA7128H; SAA7129H. Via the RTCI pin, connected to
RTCO of a decoder, information concerning actual
subcarrier, PAL-ID and (with SAA7111 and newer types)
definite subcarrier phase can be inserted.

The device synthesizes all necessary internal signals,
colour subcarrier frequency and synchronization signals
from that clock.

Wide screen signalling data can be loaded via the I

C-bus

and is inserted into line 23 for standards using 50 Hz field
rate.

VPS data for program dependent automatic start and stop
of such featured VCR's is loadable via I

C-bus.

The IC also contains closed caption and extended data
services encoding (line 21), and supports anti-taping
signal generation in accordance with Macrovision. It is also
possible to load data for copy generation management
system into line 20 of every field (525/60 line counting).

A number of possibilities are provided for setting different
video parameters, such as:

Black and blanking level control

Colour subcarrier frequency

Variable burst amplitude, etc.

During reset (RESET = LOW) and after reset is released,
all digital I/O stages are set to input mode and the encoder
is set to PAL mode and outputs a `black burst' signal on
CVBS and S-video outputs, while RGB outputs are set to
their lowest output voltages. A reset forces the I

C-bus

interface to abort any running bus transfer.

7.1

Versatile fader

Important note: whenever the fader is activated with the
SYMP bit set to a logic 1 (enabling the detection of
embedded Start of Active Video (SAV) and End of Active
Video (EAV)), codes 00H and FFH are not allowed within
the actual video data (as prescribed by

"ITU-R BT.656",

anyway). If SAV (00H) has been detected, the fader
automatically passes 100% of the respective signal until
SAV will be detected.

Within the digital video encoder, two data streams can be
faded against each other; these data streams can be input
to the double speed MPEG port, which is able to separate
two independent 27 MHz data streams MP

and MP

via

a cross switch controlled by EDGE1 and EDGE2.

handbook, halfpage

MHB574

MPA

MPB

MPpos

MPneg

EDGE1 = 0

EDGE1 = 1

EDGE2 = 1

EDGE2 = 0

Fig.3 Cross switch.

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

7.1.1

ONFIGURATION EXAMPLES

Figs 4 to 7 show examples on how to configure the fader
between the input ports and the outputs, separated into
the composite (and S-video) encoder and the RGB
encoder.

7.1.1.1

Configuration 1

Input MP

can be faded into MP

. The resulting output of

the fader is then encoded simultaneously to composite
(and S-video) and RGB output (RGBIN = ENCIN = 1).
In this example, either MP

or MP

could be an overlay

(menu) signal to be faded smoothly in and out.

7.1.1.2

Configuration 2

Input MP

can be faded into MP

. The resulting output of

the fader is then encoded to RGB output, while the signal
coming from MP

is fed directly to composite (and S-video)

output (RGBIN = 1, ENCIN = 0). Also in this example,
either MP

or MP

could be an overlay (menu) signal to be

faded smoothly in and out, whereas the overlay appears
only in the RGB output connected to the TV set.

7.1.1.3

Configuration 3

Input MP

is passed directly to the RGB output, assuming

e.g. it contains video including overlay. MP

is equivalently

passed through the inactive fader to the composite (and
S-video) output, assuming e.g. it contains video excluding
overlay (RGBIN = 0, ENCIN = 1).

7.1.1.4

Configuration 4

Only MP

input is in use; its signal appears both composite

(and S-video) and RGB encoded (RGBIN = ENCIN = 0).

MHB575

ENCODER

PATH

RGB PATH

FADER

OUTPUT

MPA

MPB

e.g.
video
recorder

e.g. TV

Fig.4 Configuration 1.

MHB576

ENCODER

PATH

RGB PATH

FADER

OUTPUT

MPA

MPB

e.g. TV

e.g.
video
recorder

Fig.5 Configuration 2.

MHB577

ENCODER

PATH

RGB PATH

FADER BYPASS

MPA

MPB

e.g. TV

e.g.
video
recorder

Fig.6 Configuration 3.

handbook, halfpage

MHB578

ENCODER

PATH

RGB PATH

MPA

MPB

e.g. video recorder

e.g. TV

Fig.7 Configuration 4.

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

7.1.2

ARAMETERS OF THE FADER

Basically, there are three independent fade factors
available, allowing for the equation:

Where x = 1, 2 or 3

Factor FADE1 is effective, when a colour in the data
stream fed to the MPEG port fader input is recognized as
being between KEY1L and KEY1U. That means, the
colour is not identified by a single numeric value, but an
upper and lower threshold in a 24-bit YUV colour space
can be defined. FADE1 = 00H results in 100% signal at the
MPEG port fader input and 0% signal at the fader Video
port input. Variation of 63 steps is possible up to
FADE1 = 3FH, resulting in 0% signal at the MPEG port
fader input and 100% signal at the fader Video port input.

Factor FADE2 is effective, when a colour in the data
stream fed to the MPEG port fader input is recognized as
being between KEY2L and KEY2U. FADE2 is to be seen
in conjunction with a colour that is defined by a 24-bit
internal Colour Look-Up Table (CLUT). FADE2 = 00H
results in 100% of the internally defined LUT colour and
0% signal at the fader Video port input. Variation of
63 steps is possible up to FADE2 = 3FH, resulting in 0% of
the internally defined LUT colour and 100% signal at the
fader Video port input.

Finally, factor FADE3 is effective, when a colour in the data
stream fed to the MPEG port fader input is recognized as
neither being between KEY1L and KEY1U nor being
between KEY2L and KEY2H. FADE3 = 00H results in
100% signal at the MPEG port fader input and 0% signal
at the fader Video port input. Variation of 63 steps is
possible up to FADE3 = 3FH, resulting in 0% signal at the
MPEG port fader input and 100% signal at the fader Video
port input.

Optionally, all upper and lower thresholds can be ignored,
enabling to fade signals only against the LUT colour.

If bit CFADM is set HIGH, all data at the MPEG port fader
are faded against the LUT colour, if bit CFADV is set
HIGH, all data at the Video port fader are faded against the
LUT colour.

7.2

Data manager

In the data manager, alternatively to the external video
data, a pre-defined colour look-up table located in this
block can be read out in a pre-defined sequence (8 steps
per active video line), achieving a colour bar test pattern
generator without the need for an external data source.

7.3

Encoder

7.3.1

IDEO PATH

The encoder generates out of Y, U and V baseband
signals luminance and colour subcarrier output signals,
suitable for use as CVBS or separate Y and C signals.

Luminance is modified in gain and in offset (latter
programmable in a certain range to enable different black
level set-ups). A blanking level can be set after insertion of
a fixed synchronization pulse tip level in accordance with
standard composite synchronization schemes. Other
manipulations used for the Macrovision anti-taping
process such as additional insertion of AGC super-white
pulses (programmable in height) are supported by the
SAA7128H only.

In order to enable easy analog post filtering, luminance is
interpolated from a 13.5 MHz data rate to a 27 MHz data
rate, providing luminance in 10-bit resolution. The transfer
characteristics of the luminance interpolation filter are
illustrated in Figs 10 and 11. Appropriate transients at
start/end of active video and for synchronization pulses
are ensured.

Chrominance is modified in gain (programmable
separately for U and V), standard dependent burst is
inserted, before baseband colour signals are interpolated
from a 6.75 MHz data rate to a 27 MHz data rate. One of
the interpolation stages can be bypassed, thus providing a
higher colour bandwidth, which can be made use of for
Y and C output. The transfer characteristics of the
chrominance interpolation filter are illustrated in
Figs 8 and 9.

The amplitude, beginning and ending of the inserted burst,
is programmable in a certain range that is suitable for
standard signals and for special effects. Behind the
succeeding quadrature modulator, colour in a 10-bit
resolution is provided on the subcarrier.

The numeric ratio between Y and C outputs is in
accordance with the respective standards.

Output

FADEx

ln1

(

)

FADEx

(

)

ln2

[

]

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

7.3.2

ELETEXT INSERTION AND ENCODING

Pin TTX receives a WST or NABTS teletext bitstream
sampled at the LLC clock. Two protocols are provided:

At each rising edge of output signal (TTXRQ) a single
teletext bit has to be provided after a programmable
delay at input pin TTX

The signal TTXRQ performs only a single LOW-to-HIGH
transition and remains at HIGH level for 360, 296 or 288
teletext bits, depending on the chosen standard.

Phase variant interpolation is achieved on this bitstream in
the internal teletext encoder, providing sufficient small
phase jitter on the output text lines.

TTXRQ provides a fully programmable request signal to
the teletext source, indicating the insertion period of
bitstream at lines which are selectable independently for
both fields. The internal insertion window for text is set to
360 (PAL-WST), 296 (NTSC-WST) or 288 (NABTS)
teletext bits including clock run-in bits. The protocol and
timing are illustrated in Fig.23.

7.3.3

IDEO

ROGRAMMING

YSTEM

(VPS)

ENCODING

Five bytes of VPS information can be loaded via the
I

C-bus and will be encoded in the appropriate format into

line 16.

7.3.4

LOSED CAPTION ENCODER

Using this circuit, data in accordance with the specification
of closed caption or extended data service, delivered by
the control interface, can be encoded (line 21). Two
dedicated pairs of bytes (two bytes per field), each pair
preceded by run-in clocks and framing code, are possible.

The actual line number where data is to be encoded in, can
be modified in a certain range.

The data clock frequency is in accordance with the
definition for NTSC-M standard 32 times horizontal line
frequency.

Data LOW at the output of the DACs corresponds to 0 IRE,
data HIGH at the output of the DACs corresponds to
approximately 50 IRE.

It is also possible to encode closed caption data for 50 Hz
field frequencies at 32 times horizontal line frequency.

7.3.5

NTI

TAPING

(SAA7128H

ONLY

)

For more information contact your nearest Philips
Semiconductors sales office.

7.4

RGB processor

This block contains a dematrix in order to produce red,
green and blue signals to be fed to a SCART plug.

Before Y, C

and C

signals are de-matrixed, individual

gain adjustment for Y and colour difference signals and
2 times oversampling for luminance and 4 times
oversampling for colour difference signals is performed.
The transfer curves of luminance and colour difference
components of RGB are illustrated in Figs 12 and 13.

7.5

SECAM processor

SECAM specific pre-processing is achieved by a
pre-emphasis of colour difference signals (for gain and
phase see Figs 14 and 15).

A baseband frequency modulator with a reference
frequency shifted from 4.286 MHz to DC carries out
SECAM modulation in accordance with appropriate
standard or optionally wide clipping limits.

After the HF pre-emphasis, also applied on a DC reference
carrier (anti-Cloche filter; see Figs 16 and 17), line-by-line
sequential carriers with black reference of 4.25 MHz (Db)
and 4.40625 MHz (Dr) are generated using specified
values for FSC programming bytes.

Alternating phase reset in accordance with SECAM
standard is carried out automatically. During vertical
blanking, the so-called "bottle pulses" are not provided.

7.6

Output interface/DACs

In the output interface, encoded Y and C signals are
converted from digital-to-analog in a 10-bit resolution.
Y and C signals are also combined to a 10-bit CVBS
signal.

The CVBS output occurs with the same processing delay
(equal to 82 LLC clock periods, measured from MP input
to the analog outputs) as the Y, C and RGB outputs.
Absolute amplitude at the input of the DAC for CVBS is
reduced by

with respect to Y and C DACs to make

maximum use of conversion ranges.

Red, green and blue signals are also converted from
digital-to-analog, each providing a 9-bit resolution.

Outputs of the DACs can be set together via software
control to minimum output voltage (approximately 0.2 V
DC) for either purpose. Alternatively, the buffers can be
switched into 3-state output condition; this allows for a
`wired AND' configuration with other 3-state outputs and
can also be used as a power-save mode.

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

7.7

Synchronization

The synchronization of the SAA7128H; SAA7129H is able
to operate in two modes; slave mode and master mode.

In master mode (see Fig.19), the circuit generates all
necessary timings in the video signal itself, and it can
provide timing signals at the RCV1 and RCV2 ports.
In slave mode, it accepts timing information either from the
RCV pins or from the embedded timing data of the
ITU-R BT.656 data stream.

For the SAA7128H; SAA7129H, the only difference
between master and slave mode is that it ignores the
timing information at its inputs in master mode. Thus, if in
slave mode, any timing information is missing, the IC will
continue running free without a visible effect. But there
must not be any additional pulses (with wrong phase)
because the circuit will not ignore them.

In slave mode (see Fig.18), an interface circuit decides,
which signal is expected at the RCV1 port and which
information is taken from its active slope. The polarity can
be chosen. If PRCV1 is logic 0, the rising slope will be
active.

The signal can be:

A Vertical Sync (VS) pulse; the active slope sets the
vertical phase

An odd/even signal; the active slope sets the vertical
phase, the internal field flag to odd and optionally sets
the horizontal phase

A Field Sequence (FSEQ) signal; it marks the first field
of the 4 (NTSC), 8 (PAL) respectively 12 (SECAM) field
sequences. In addition to the odd/even signal, it also
sets the PAL phase and optionally defines the subcarrier
phase.

On the RCV2 port, the IC can provide a horizontal pulse
with programmable start and stop phase; this pulse can be
inhibited in the vertical blanking period to build up, for
example, a composite blanking signal.

The horizontal phase can be set via a separate input
RCV2. In the event of VS pulses at RCV1, this is
mandatory. It is also possible to set the signal path to blank
via this input.

From the ITU-R BT.656 data stream, the SAA7128H;
SAA7129H decodes only the start of the first line in the odd
field. All other information is ignored and may miss. If this
kind of slave mode is active, the RCV pins may be
switched to output mode.

In slave mode, the horizontal trigger phase can be
programmed to any point in the line, the vertical phase
from line 0 to line 15 counted from the first serration pulse
in half line steps.

Whenever synchronization information cannot be derived
directly from the inputs, the SAA7128H; SAA7129H will
calculate it from the internal horizontal, vertical and PAL
phase. This gives good flexibility with respect to external
synchronization, but the circuit does not suppress illegal
settings. In such an event, the odd/even information may
vanish as it does in the non-interlaced modes.

In master mode, the line lengths are fixed to 1728 clocks
at 50 Hz and 1716 clocks at 60 Hz. To allow
non-interlaced frames, the field lengths can be varied by

0.5 lines. In the event of non-interlace, the SAA7128H;

SAA7129H does not provide odd/even information and the
output signal does not contain the PAL `Bruch sequence'.

At the RCV1 pin the IC can provide:

A Vertical Sync (VS) signal with 2.5 (50 Hz) or 3 (60 Hz)
lines duration

An odd/even signal which is LOW in odd fields

A Field Sequence (FSEQ) signal which is HIGH in the
first field of the 4, 8 respectively 12 field sequences.

At the RCV2 pin, there is a horizontal pulse of
programmable phase and duration available. This pulse
can be suppressed in the programmable inactive part of a
field, giving a composite blank signal.

The directions and polarities of the RCV ports can be
chosen independently. Timing references can be found in
Tables 52 and 60.

7.8

Clock

The input to LLC1 can either be an external clock source
or the buffered on-chip clock XCLK. The internal crystal
oscillator can be run with either a 3rd-harmonic or a
fundamental crystal frequency.

7.9

C-bus interface

The I

C-bus interface is a standard slave transceiver,

supporting 7-bit slave addresses and 400 kbits/s
guaranteed transfer rate. It uses 8-bit subaddressing with
an auto-increment function. All registers are write and
readable, except one read only status byte.

The I

C-bus slave address is defined as 88H with pin 21

(SA) tied LOW and as 8CH with pin 21 (SA) tied HIGH.

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

7.10

Input levels and formats

The SAA7128H; SAA7129H expects digital Y, C

and C

data with levels (digital codes) in accordance with
"ITU-R BT.601".

For C and CVBS outputs, deviating amplitudes of the
colour difference signals can be compensated by
independent gain control setting, while gain for luminance
is set to predefined values, distinguishable for 7.5 IRE
set-up or without set-up.

The RGB, respectively C

-Y-C

path features a gain

setting individually for luminance (GY) and colour
difference signals (GCD).

Reference levels are measured with a colour bar,
100% white, 100% amplitude and 100% saturation.

Table 1

"ITU-R BT.601" signal component levels

Notes

1. Transformation:

a) R = Y + 1.3707

128)

b) G = Y

0.3365

128)

0.6982

128)

c) B = Y + 1.7324

128).

2. Representation of R, G and B (or C

, Y and C

) at the output is 9 bits at 27 MHz.

Table 2

8-bit multiplexed format (similar to

"ITU-R BT.601")

COLOUR

SIGNALS

(1)

(2)

White

235

128

235

Yellow

210

146

235

Cyan

170

166

235

Green

145

235

Magenta

106

202

222

235

Red

240

235

Blue

240

110

235

Black

128

TIME

BITS

Sample

Luminance pixel number

Colour pixel number

2002

Oct

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

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7.11

Bit allocation map

Table 3

Slave receiver (slave address 88H)

REGISTER FUNCTION

SUBADDR

DATA BYTE

(1)

Status byte (read only)

00H

VER2

VER1

VER0

CCRDO

CCRDE

FSEQ

O_E

Null

01H to 25H

Wide screen signal

26H

WSS7

WSS6

WSS5

WSS4

WSS3

WSS2

WSS1

WSS0

Wide screen signal

27H

WSSON

WSS13

WSS12

WSS11

WSS10

WSS9

WSS8

Real-time control, burst start

28H

DECCOL

DECFIS

BS5

BS4

BS3

BS2

BS1

BS0

Burst end

29H

BE5

BE4

BE3

BE2

BE1

BE0

Copy generation 0

2AH

CG07

CG06

CG05

CG04

CG03

CG02

CG01

CG00

Copy generation 1

2BH

CG15

CG14

CG13

CG12

CG11

CG10

CG09

CG08

CG enable, copy generation 2

2CH

CGEN

CG19

CG18

CG17

CG16

Output port control

2DH

CVBSEN1

CVBSEN0

CVBSTRI

YTRI

CTRI

RTRI

GTRI

BTRI

Null

2EH to 37H

Gain luminance for RGB

38H

GY4

GY3

GY2

GY1

GY0

Gain colour difference for RGB

39H

GCD4

GCD3

GCD2

GCD1

GCD0

Input port control 1

3AH

CBENB

SYMP

DEMOFF

CSYNC

MP2C

VP2C

Key colour 1 lower limit U

42H

KEY1LU7

KEY1LU6

KEY1LU5

KEY1LU4

KEY1LU3

KEY1LU2

KEY1LU1

KEY1LU0

Key colour 1 lower limit V

43H

KEY1LV7

KEY1LV6

KEY1LV5

KEY1LV4

KEY1LV3

KEY1LV2

KEY1LV1

KEY1LV0

Key colour 1 lower limit Y

44H

KEY1LY7

KEY1LY6

KEY1LY5

KEY1LY4

KEY1LY3

KEY1LY2

KEY1LY1

KEY1LY0

Key colour 2 lower limit U

45H

KEY2LU7

KEY2LU6

KEY2LU5

KEY2LU4

KEY2LU3

KEY2LU2

KEY2LU1

KEY2LU0

Key colour 2 lower limit V

46H

KEY2LV7

KEY2LV6

KEY2LV5

KEY2LV4

KEY2LV3

KEY2LV2

KEY2LV1

KEY2LV0

Key colour 2 lower limit Y

47H

KEY2LY7

KEY2LY6

KEY2LY5

KEY2LY4

KEY2LY3

KEY2LY2

KEY2LY1

KEY2LY0

Key colour 1 upper limit U

48H

KEY1UU7

KEY1UU6

KEY1UU5

KEY1UU4

KEY1UU3

KEY1UU2

KEY1UU1

KEY1UU0

Key colour 1 upper limit V

49H

KEY1UV7

KEY1UV6

KEY1UV5

KEY1UV4

KEY1UV3

KEY1UV2

KEY1UV1

KEY1UV0

Key colour 1 upper limit Y

4AH

KEY1UY7

KEY1UY6

KEY1UY5

KEY1UY4

KEY1UY3

KEY1UY2

KEY1UY1

KEY1UY0

Key colour 2 upper limit U

4BH

KEY2UU7

KEY2UU6

KEY2UU5

KEY2UU4

KEY2UU3

KEY2UU2

KEY2UU1

KEY2UU0

Key colour 2 upper limit V

4CH

KEY2UV7

KEY2UV6

KEY2UV5

KEY2UV4

KEY2UV3

KEY2UV2

KEY2UV1

KEY2UV0

Key colour 2 upper limit Y

4DH

KEY2UY7

KEY2UY6

KEY2UY5

KEY2UY4

KEY2UY3

KEY2UY2

KEY2UY1

KEY2UY0

Fade factor key colour 1

4EH

FADE15

FADE14

FADE13

FADE12

FADE11

FADE10

CFade, Fade factor key
colour 2

4FH

CFADEM

CFADEV

FADE25

FADE24

FADE23

FADE22

FADE21

FADE20

2002

Oct

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

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Fade factor other

50H

FADE35

FADE34

FADE33

FADE32

FADE31

FADE30

Look-up table key colour 2 U

51H

LUTU7

LUTU6

LUTU5

LUTU4

LUTU3

LUTU2

LUTU1

LUTU0

Look-up table key colour 2 V

52H

LUTV7

LUTV6

LUTV5

LUTV4

LUTV3

LUTV2

LUTV1

LUTV0

Look-up table key colour 2 Y

53H

LUTY7

LUTY6

LUTY5

LUTY4

LUTY3

LUTY2

LUTY1

LUTY0

VPS enable, input control 2

54H

VPSEN

ENCIN

RGBIN

DELIN

VPSEL

EDGE2

EDGE1

VPS byte 5

55H

VPS57

VPS56

VPS55

VPS54

VPS53

VPS52

VPS51

VPS50

VPS byte 11

56H

VPS117

VPS116

VPS115

VPS114

VPS113

VPS112

VPS111

VPS110

VPS byte 12

57H

VPS127

VPS126

VPS125

VPS124

VPS123

VPS122

VPS121

VPS120

VPS byte 13

58H

VPS137

VPS136

VPS135

VPS134

VPS133

VPS132

VPS131

VPS130

VPS byte 14

59H

VPS147

VPS146

VPS145

VPS144

VPS143

VPS142

VPS141

VPS140

Chrominance phase

5AH

CHPS7

CHPS6

CHPS5

CHPS4

CHPS3

CHPS2

CHPS1

CHPS0

Gain U

5BH

GAINU7

GAINU6

GAINU5

GAINU4

GAINU3

GAINU2

GAINU1

GAINU0

Gain V

5CH

GAINV7

GAINV6

GAINV5

GAINV4

GAINV3

GAINV2

GAINV1

GAINV0

Gain U MSB, real-time control,
black level

5DH

GAINU8

DECOE

BLCKL5

BLCKL4

BLCKL3

BLCKL2

BLCKL1

BLCKL0

Gain V MSB, real-time control,
blanking level

5EH

GAINV8

DECPH

BLNNL5

BLNNL4

BLNNL3

BLNNL2

BLNNL1

BLNNL0

CCR, blanking level VBI

5FH

CCRS1

CCRS0

BLNVB5

BLNVB4

BLNVB3

BLNVB2

BLNVB1

BLNVB0

Null

60H

Standard control

61H

DOWNB

DOWNA

INPI

YGS

SECAM

SCBW

PAL

FISE

RTC enable, burst amplitude

62H

RTCE

BSTA6

BSTA5

BSTA4

BSTA3

BSTA2

BSTA1

BSTA0

Subcarrier 0

63H

FSC07

FSC06

FSC05

FSC04

FSC03

FSC02

FSC01

FSC00

Subcarrier 1

64H

FSC15

FSC14

FSC13

FSC12

FSC11

FSC10

FSC09

FSC08

Subcarrier 2

65H

FSC23

FSC22

FSC21

FSC20

FSC19

FSC18

FSC17

FSC16

Subcarrier 3

66H

FSC31

FSC30

FSC29

FSC28

FSC27

FSC26

FSC25

FSC24

Line 21 odd 0

67H

L21O07

L21O06

L21O05

L21O04

L21O03

L21O02

L21O01

L21O00

Line 21 odd 1

68H

L21O17

L21O16

L21O15

L21O14

L21O13

L21O12

L21O11

L21O10

Line 21 even 0

69H

L21E07

L21E06

L21E05

L21E04

L21E03

L21E02

L21E01

L21E00

Line 21 even 1

6AH

L21E17

L21E16

L21E15

L21E14

L21E13

L21E12

L21E11

L21E10

RCV port control

6BH

SRCV11

SRCV10

TRCV2

ORCV1

PRCV1

CBLF

ORCV2

PRCV2

Trigger control

6CH

HTRIG7

HTRIG6

HTRIG5

HTRIG4

HTRIG3

HTRIG2

HTRIG1

HTRIG0

REGISTER FUNCTION

SUBADDR

DATA BYTE

(1)

2002

Oct

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

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Note

1. All bits labelled `0' are reserved. They must be programmed with logic 0.

Trigger control

6DH

HTRIG10

HTRIG9

HTRIG8

VTRIG4

VTRIG3

VTRIG2

VTRIG1

VTRIG0

Multi control

6EH

SBLBN

BLCKON

PHRES1

PHRES0

LDEL1

LDEL0

FLC1

FLC0

Closed caption, teletext enable

6FH

CCEN1

CCEN0

TTXEN

SCCLN4

SCCLN3

SCCLN2

SCCLN1

SCCLN0

RCV2 output start

70H

RCV2S7

RCV2S6

RCV2S5

RCV2S4

RCV2S3

RCV2S2

RCV2S1

RCV2S0

RCV2 output end

71H

RCV2E7

RCV2E6

RCV2E5

RCV2E4

RCV2E3

RCV2E2

RCV2E1

RCV2E0

MSBs RCV2 output

72H

RCV2E10

RCV2E9

RCV2E8

RCV2S10

RCV2S9

RCV2S8

TTX request H start

73H

TTXHS7

TTXHS6

TTXHS5

TTXHS4

TTXHS3

TTXHS2

TTXHS1

TTXHS0

TTX request H delay

74H

TTXHD7

TTXHD6

TTXHD5

TTXHD4

TTXHD3

TTXHD2

TTXHD1

TTXHD0

CSYNC advance, Vsync shift

75H

CSYNCA4 CSYNCA3 CSYNCA2 CSYNCA1 CSYNCA0 VS_S2

VS_S1

VS_S0

TTX odd request vertical start

76H

TTXOVS7

TTXOVS6

TTXOVS5

TTXOVS4

TTXOVS3

TTXOVS2

TTXOVS1

TTXOVS0

TTX odd request vertical end

77H

TTXOVE7

TTXOVE6

TTXOVE5

TTXOVE4

TTXOVE3

TTXOVE2

TTXOVE1

TTXOVE0

TTX even request vertical start

78H

TTXEVS7

TTXEVS6

TTXEVS5

TTXEVS4

TTXEVS3

TTXEVS2

TTXEVS1

TTXEVS0

TTX even request vertical end

79H

TTXEVE7

TTXEVE6

TTXEVE5

TTXEVE4

TTXEVE3

TTXEVE2

TTXEVE1

TTXEVE0

First active line

7AH

FAL7

FAL6

FAL5

FAL4

FAL3

FAL2

FAL1

FAL0

Last active line

7BH

LAL7

LAL6

LAL5

LAL4

LAL3

LAL2

LAL1

LAL0

TTX mode, MSB vertical

7CH

TTX60

LAL8

TTXO

FAL8

TTXEVE8

TTXOVE8

TTXEVS8

TTXOVS8

Null

7DH

Disable TTX line

7EH

LINE12

LINE11

LINE10

LINE9

LINE8

LINE7

LINE6

LINE5

Disable TTX line

7FH

LINE20

LINE19

LINE18

LINE17

LINE16

LINE15

LINE14

LINE13

REGISTER FUNCTION

SUBADDR

DATA BYTE

(1)

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

7.12

C-bus format

Table 4

C-bus address; see Table 5

Table 5

Explanation of Table 4

Notes

1. X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read.

2. If more than 1 byte DATA is transmitted, then auto-increment of the subaddress is performed.

7.13

Slave receiver

Table 6

Subaddress 26H

Table 7

Subaddress 27H

SLAVE ADDRESS

ACK

SUBADDRESS

ACK

DATA 0

ACK

--------

DATA n

ACK

PART

DESCRIPTION

START condition

SLAVE ADDRESS

1000 100X or 1000 110X; note 1

ACK

acknowledge, generated by the slave

SUBADDRESS; note 2

subaddress byte

DATA

data byte

--------

continued data bytes and ACKs

STOP condition

BIT

SYMBOL

DESCRIPTION

WSS7

Wide screen signalling bits: enhanced services field.

WSS6

WSS5

WSS4

WSS3

Wide screen signalling bits: aspect ratio field.

WSS2

WSS1

WSS0

BIT

SYMBOL

DESCRIPTION

WSSON

0 = wide screen signalling output is disabled; default state after reset
1 = wide screen signalling output is enabled

This bit is reserved and must be set to logic 0.

WSS13

Wide screen signalling bits: reserved field.

WSS12

WSS11

WSS10

Wide screen signalling bits: subtitles field.

WSS9

WSS8

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

Table 8

Subaddress 28H

Table 9

Subaddress 29H

Table 10 Subaddress 2AH

Table 11 Subaddress 2BH

BIT

SYMBOL

DESCRIPTION

DECCOL

0 = disable colour detection bit of RTCI input
1 = enable colour detection bit of RTCI input; bit RTCE must be set to logic 1 (see
Fig.22)

DECFIS

0 = field sequence as FISE in subaddress 61
1 = field sequence as FISE bit in RTCI input; bit RTCE must be set to logic 1 (see
Fig.22)

BS5

starting point of burst in clock cycles

BS4

PAL: BS[5:0] = 33 (21H); default value after reset

NTSC: BS[5:0] = 25 (19H)

BS3

BS2

BS1

BS0

BIT

SYMBOL

DESCRIPTION

These 2 bits are reserved; each must be set to logic 0.

BE5

ending point of burst in clock cycles

PAL: BE[5:0] = 29 (1DH); default value after reset

NTSC: BE[5:0] = 29 (1DH)

BE4

BE3

BE2

BE1

BE0

BIT

SYMBOL

DESCRIPTION

7 to 0

CG[07:00]

LSB of the byte is encoded immediately after run-in, the MSB of the byte has to carry
the CRCC bit, in accordance with the definition of copy generation management system
encoding format.

BIT

SYMBOL

DESCRIPTION

7 to 0

CG[15:08]

Second byte; the MSB of the byte has to carry the CRCC bit, in accordance with the
definition of copy generation management system encoding format.

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

Table 12 Subaddress 2CH

Table 13 Subaddress 2DH

Table 14 Subaddress 38H

Table 15 Subaddress 39H

BIT

SYMBOL

DESCRIPTION

CGEN

0 = copy generation data output is disabled; default state after reset
1 = copy generation data output is enabled

These 3 bits are reserved; each must be set to logic 0.

CG19

Remaining bits of copy generation code.

CG18

CG17

CG16

BIT

SYMBOL

DESCRIPTION

CVBSEN1

0 = luminance output signal is switched to Y DAC; default state after reset
1 = CVBS output signal is switched to Y DAC

CVBSEN0

0 = chrominance output signal is switched to C DAC; default state after reset
1 = CVBS output signal is switched to C DAC

CVBSTRI

0 = DAC for CVBS output in 3-state mode (high-impedance)
1 = DAC for CVBS output in normal operation mode; default state after reset

YTRI

0 = DAC for Y output in 3-state mode (high-impedance)
1 = DAC for Y output in normal operation mode; default state after reset

CTRI

0 = DAC for C output in 3-state mode (high-impedance)
1 = DAC for C output in normal operation mode; default state after reset

RTRI

0 = DAC for RED output in 3-state mode (high-impedance)
1 = DAC for RED output in normal operation mode; default state after reset

GTRI

0 = DAC for GREEN output in 3-state mode (high-impedance)
1 = DAC for GREEN output in normal operation mode; default state after reset

BTRI

0 = DAC for BLUE output in 3-state mode (high-impedance)
1 = DAC for BLUE output in normal operation mode; default state after reset

BIT

SYMBOL

DESCRIPTION

7 to 5

These 3 bits are reserved; each must be set to logic 0.

4 to 0

GY[4:0]

Gain luminance of RGB (C

, Y and C

) output, ranging from (1

) to (1 +

Suggested nominal value =

6 (11010b), depending on external application.

BIT

SYMBOL

DESCRIPTION

7 to 5

These 3 bits are reserved; each must be set to logic 0.

4 to 0

GCD[4:0]

Gain colour difference of RGB (C

, Y and C

) output, ranging from

) to (1 +

). Suggested nominal value =

6 (11010b), depending on external

application.

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

Table 16 Subaddress 3AH

Table 17 Subaddresses 42H to 44H and 48H to 4AH

Table 18 Subaddresses 45H to 47H and 4BH to 4DH

BIT

SYMBOL

DESCRIPTION

CBENB

0 = data from input ports is encoded; default state after reset
1 = colour bar with fixed colours is encoded

These 2 bits are reserved; each must be set to a logic 0.

SYMP

0 = horizontal and vertical trigger is taken from RCV2 and RCV1 respectively; default
state after reset
1 = horizontal and vertical trigger is decoded out of

"ITU-R BT.656" compatible data at

MPEG port

DEMOFF

0 = YC

-to-RGB dematrix is active; default state after reset

1 = YC

-to-RGB dematrix is bypassed

CSYNC

0 = CVBS output signal is switched to CVBS DAC; default state after reset
1 = advanced composite sync is switched to CVBS DAC

MP2C

0 = input data is twos complement from MPEG port fader input
1 = input data is straight binary from MPEG port fader input; default state after reset

VP2C

0 = input data is twos complement from Video port fader input
1 = input data is straight binary from Video port fader input; default state after reset

ADDRESS

BYTE

DESCRIPTION

42H
48H

KEY1LU

KEY1UU

Key colour 1 lower and upper limits for U, V and Y. If MPEG input signal is within the
limits of key colour 1 the incoming signals at the Video port and MPEG port are added
together according to the equation:

FADE1

video signal + (1

FADE1)

MPEG signal

Default value of all bytes after reset = 80H.

43H
49H

KEY1LV

KEY1UV

44H

4AH

KEY1LY

KEY1UY

ADDRESS

BYTE

DESCRIPTION

45H

4BH

KEY2LU

KEY2UU

Key colour 2 lower and upper limits for U,V and Y. If MPEG input signal is within the
limits of key colour 2 the incoming signals at the Video port and MPEG port are added
together according to the equation:

FADE2

video signal + (1

FADE2)

LUT values

Default value of all bytes after reset = 80H.

46H

4CH

KEY2LV

KEY2UV

47H

4DH

KEY2LY

KEY2UY

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

Table 19 Subaddress 4EH

Table 20 Subaddress 4FH

Table 21 Subaddress 50H

BIT

SYMBOL

DESCRIPTION

7 to 6

These 2 bits are reserved; each must be set to logic 0.

5 to 0

FADE1[5:0]

These 6 bits form factor FADE1 which determines the ratio between the MPEG and
video input signal in the resulting video data stream if the key colour 1 is detected in the
MPEG input signal.

FADE1 = 00H: 100% MPEG, 0% video

FADE1 = 3FH: 100% video, 0% MPEG; this is the default value after reset

BIT

SYMBOL

DESCRIPTION

CFADEM

0 = fader operates in normal mode; default state after reset
1 = the entire video input stream is faded with the colour stored in the LUT
(subaddresses 51H to 53H) regardless of the MPEG input signal. The colour keys are
disabled.

CFADEV

0 = fader operates in normal mode; default state after reset
1 = the entire MPEG input stream is faded with the colour stored in the LUT
(subaddresses 51H to 53H) regardless of the video input signal. The colour keys are
disabled.

5 to 0

FADE2[5:0]

These 6 bits form factor FADE2 which determines the ratio between the LUT colour
values (subaddresses 51H to 53H) and the video input signal in the resulting video data
stream if the key colour 2 is detected in the MPEG input signal.

FADE2 = 00H: 100% LUT colour, 0% video

FADE2 = 3FH: 100% video, 0% LUT colour; this is the default value after reset

BIT

SYMBOL

DESCRIPTION

7 to 6

These 2 bits are reserved; each must be a logic 0.

5 to 0

FADE3[5:0]

These 6 bits form factor FADE3 which determines the ratio between the MPEG and
video input signal in the resulting video data stream if neither the key colour 1 nor the
key colour 2 is detected in the MPEG input signal.

FADE3 = 00H: 100% MPEG, 0% video

FADE3 = 3FH: 100% video, 0% MPEG; this is the default value after reset

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

Table 22 Subaddress 51H

Table 23 Subaddress 52H

Table 24 Subaddress 53H

Table 25 Subaddress 54H

BIT

SYMBOL

DESCRIPTION

7 to 0

LUTU[7:0]

LUT for the colour values inserted in case of key colour 2 U detection in the MPEG input
data stream.

LUTU[7:0] = 80H; default value after reset

BIT

SYMBOL

DESCRIPTION

7 to 0

LUTV[7:0]

LUT for the colour values inserted in case of key colour 2 V detection in the MPEG input
data stream.

LUTV[7:0] = 80H; default value after reset

BIT

SYMBOL

DESCRIPTION

7 to 0

LUTY[7:0]

LUT for the colour values inserted in case of key colour 2 Y detection in the MPEG input
data stream.

LUTY[7:0] = 80H; default value after reset

BIT

SYMBOL

DESCRIPTION

VPSEN

0 = video programming system data insertion is disabled; default state after reset
1 = video programming system data insertion in line 16 is enabled

This bit is not used and should be set to logic 0.

ENCIN

0 = encoder path is fed with MP

input data; fader is bypassed; default state after reset

1 = encoder path is fed with output signal of fader; see Section 7.1

RGBIN

0 = RGB path is fed with MP

input data; fader is bypassed; default state after reset

1 = RGB path is fed with output signal of fader; see Section 7.1

DELIN

0 = not supported in current version; do not use
1 = recommended value; default state after reset

VPSEL

0 = not supported in current version; do not use
1 = recommended value; default state after reset

EDGE2

0 = MP

data is sampled on the rising clock edge; default state after reset

1 = MP

data is sampled on the falling clock edge

EDGE1

0 = MP

data is sampled on the rising clock edge; default state after reset

1 = MP

data is sampled on the falling clock edge

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

Table 26 Subaddress 55H

Table 27 Subaddress 56H

Table 28 Subaddress 57H

Table 29 Subaddress 58H

Table 30 Subaddress 59H

Table 31 Subaddress 5AH

BIT

SYMBOL

DESCRIPTION

7 to 0

VPS5[7:0]

Fifth byte of video programming system data in line 16; LSB first.

BIT

SYMBOL

DESCRIPTION

7 to 0

VPS11[7:0]

Eleventh byte of video programming system data in line 16; LSB first.

BIT

SYMBOL

DESCRIPTION

7 to 0

VPS12[7:0]

Twelfth byte of video programming system data in line 16; LSB first.

BIT

SYMBOL

DESCRIPTION

7 to 0

VPS13[7:0]

Thirteenth byte of video programming system data in line 16; LSB first.

BIT

SYMBOL

DESCRIPTION

7 to 0

VPS14[7:0]

Fourteenth byte of video programming system data in line 16; LSB first.

BIT

SYMBOL

DESCRIPTION

7 to 0

CHPS[7:0]

Phase of encoded colour subcarrier (including burst) relative to horizontal sync; can be
adjusted in steps of 360/256 degrees.

0FH = PAL-B/G and data from input ports

3AH = PAL-B/G and data from look-up table

35H = NTSC-M and data from input ports

57H = NTSC-M and data from look-up table

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

Table 32 Subaddress 5BH

Table 33 GAINU values

Note

1. All IRE values are rounded up

Table 34 Subaddress 5CH

Table 35 GAINV values

Note

1. All IRE values are rounded up.

BIT

SYMBOL

DESCRIPTION

7 to 0

GAINU[7:0]

These are the 8 LSBs of the 9-bit code that selects the variable gain for the C

signal;

input representation in accordance with

"ITU-R BT.601"; see Table 33. The MSB is held

in subaddress 5DH; see Table 36.

CONDITIONS

(1)

ENCODING

white-to-black = 92.5 IRE

GAINU =

2.17

nominal to +2.16

nominal

GAINU[8:0] = 0

output subcarrier of U contribution = 0

GAINU[8:0] = 118 (76H)

output subcarrier of U contribution = nominal

white-to-black = 100 IRE

GAINU =

2.05

nominal to +2.04

nominal

GAINU[8:0] = 0

output subcarrier of U contribution = 0

GAINU[8:0] = 125 (7DH)

output subcarrier of U contribution = nominal

GAINU[8:0] = 106 (6AH)

nominal GAINU for SECAM encoding

BIT

SYMBOL

DESCRIPTION

7 to 0

GAINV[7:0]

These are the 8 LSBs of the 9-bit code that selects the variable gain for the C

signal;

input representation in accordance with

"ITU-R BT.601"; see Table 35. The MSB is held

in subaddress 5EH; see Table 38.

CONDITIONS

(1)

ENCODING

white-to-black = 92.5 IRE

GAINV =

1.55

nominal to +1.55

nominal

GAINV[8:0] = 0

output subcarrier of V contribution = 0

GAINV[8:0] = 165 (A5H)

output subcarrier of V contribution = nominal

white-to-black = 100 IRE

GAINV =

1.46

nominal to +1.46

nominal

GAINV[8:0] = 0

output subcarrier of V contribution = 0

GAINV[8:0] = 175 (AFH)

output subcarrier of V contribution = nominal

GAINV[8:0] = 129 (81H)

nominal GAINV for SECAM encoding

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

Table 36 Subaddress 5DH

Table 37 BLCKL values

Notes

1. All IRE values are rounded up.

2. Output black level/IRE = BLCKL

2/6.29 + 28.9.

3. Output black level/IRE = BLCKL

2/6.18 + 26.5.

Table 38 Subaddress 5EH

BIT

SYMBOL

DESCRIPTION

GAINU8

MSB of the 9-bit code that sets the variable gain for the C

signal; see Table 32.

DECOE

real-time control:

0 = disable odd/even field control bit from RTCI

1 = enable odd/even field control bit from RTCI (see Fig.22)

5 to 0

BLCKL[5:0]

variable black level; input representation in accordance with

"ITU-R BT.601";

see Table 37

CONDITIONS

(1)

ENCODING

(1)

white-to-sync = 140 IRE; note 2 recommended value: BLCKL = 58 (3AH)

BLCKL = 0; note 2

output black level = 29 IRE

BLCKL = 63 (3FH); note 2

output black level = 49 IRE

white-to-sync = 143 IRE; note 3 recommended value: BLCKL = 51 (33H)

BLCKL = 0; note 3

output black level = 27 IRE

BLCKL = 63 (3FH); note 3

output black level = 47 IRE

BIT

SYMBOL

DESCRIPTION

GAINV8

MSB of the 9-bit code that sets the variable gain for the C

signal; see Table 34.

DECPH

real-time control:

0 = disable subcarrier phase reset bit from RTCI

1 = enable subcarrier phase reset bit from RTCI (see Fig.22)

5 to 0

BLNNL[5:0]

variable blanking level; see Table 39

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

Table 39 BLNNL values

Notes

1. All IRE values are rounded up.

2. Output black level/IRE = BLNNL

2/6.29 + 25.4.

3. Output black level/IRE = BLNNL

2/6.18 + 25.9; default after reset: 35H.

Table 40 Subaddress 5FH

Table 41 Selection of cross-colour reduction filter

CONDITIONS

(1)

ENCODING

(1)

white-to-sync = 140 IRE; note 2 recommended value: BLNNL = 46 (2EH)

BLNNL = 0; note 2

output blanking level = 25 IRE

BLNNL = 63 (3FH); note 2

output blanking level = 45 IRE

white-to-sync = 143 IRE; note 3 recommended value: BLNNL = 53 (35H)

BLNNL = 0; note 3

output blanking level = 26 IRE

BLNNL = 63 (3FH); note 3

output blanking level = 46 IRE

BIT

SYMBOL

DESCRIPTION

CCRS1

These 2 bits select the cross-colour reduction filter in luminance; see Table 41
and Fig.10.

CCRS0

BLNVB5

These 6 bits select the variable blanking level during vertical blanking interval is
typically identical to value of BLNNL.

BLNVB4

BLNVB3

BLNVB2

BLNVB1

BLNVB0

CCRS1

CCRS0

DESCRIPTION

no cross-colour reduction

cross-colour reduction #1 active

cross-colour reduction #2 active

cross-colour reduction #3 active

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

Table 42 Subaddress 61H

Table 43 Subaddress 62H

BIT

SYMBOL

DESCRIPTION

DOWNB

0 = DACs for R, G and B in normal operational mode
1 = DACs for R, G and B forced to lowest output voltage; default state after reset

DOWNA

0 = DACs for CVBS, Y and C in normal operational mode; default state after reset
1 = DACs for CVBS, Y and C forced to lowest output voltage

INPI

0 = PAL switch phase is nominal; default state after reset
1 = PAL switch phase is inverted compared to nominal if RTC is enabled; see Table 43

YGS

0 = luminance gain for white

black 100 IRE; default state after reset

1 = luminance gain for white

black 92.5 IRE including 7.5 IRE set-up of black

SECAM

0 = no SECAM encoding; default state after reset
1 = SECAM encoding activated; bit PAL has to be set to logic 0

SCBW

0 = enlarged bandwidth for chrominance encoding (for overall transfer characteristic of
chrominance in baseband representation see Figs 8 and 9)
1 = standard bandwidth for chrominance encoding (for overall transfer characteristic of
chrominance in baseband representation see Figs 8 and 9); default state after reset

PAL

0 = NTSC encoding (non-alternating V component)
1 = PAL encoding (alternating V component); default state after reset

FISE

0 = 864 total pixel clocks per line; default state after reset
1 = 858 total pixel clocks per line

BIT

SYMBOL

DESCRIPTION

RTCE

0 = no real-time control of generated subcarrier frequency; default state after reset
1 = real-time control of generated subcarrier frequency through SAA7151B or
SAA7111; for timing see Fig.22

6 to 0

BSTA[6:0]

amplitude of colour burst; input representation in accordance with

"ITU-R BT.601";

see Table 44

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

Table 44 BSTA values

Note

1. All IRE values are rounded up.

Table 45 Subaddresses 63H to 66H

Note

1. Examples:

a) NTSC-M: f

= 227.5, f

llc

= 1716

FSC = 569408543 (21F07C1FH).

b) PAL-B/G: f

= 283.7516, f

llc

= 1728

FSC = 705268427 (2A098ACBH).

c) SECAM: f

= 274.304, f

llc

= 1728

FSC = 681786290 (28A33BB2H).

CONDITIONS

(1)

ENCODING

white-to-black = 92.5 IRE;
burst = 40 IRE; NTSC encoding

recommended value: BSTA = 63 (3FH)

BSTA = 0 to 2.02

nominal

white-to-black = 92.5 IRE;
burst = 40 IRE; PAL encoding

recommended value: BSTA = 45 (2DH)

BSTA = 0 to 2.82

nominal

white-to-black = 100 IRE;
burst = 43 IRE; NTSC encoding

recommended value: BSTA = 67 (43H)

BSTA = 0 to 1.90

nominal

white-to-black = 100 IRE;
burst = 43 IRE; PAL encoding

recommended value: BSTA = 47 (2FH); default value after reset

BSTA = 0 to 3.02

nominal

fixed burst amplitude with SECAM encoding

ADDRESS

BYTE

DESCRIPTION

63H

FSC[07:00]

These 4 bytes are used to program the subcarrier frequency. FSC[31:24] is the most
significant byte, FSC[07:00] is the least significant byte.

64H

FSC[15:08]

= subcarrier frequency (in multiples of line frequency)

llc

= clock frequency (in multiples of line frequency)

65H

FSC[23:16]

note 1

66H

FSC[31:24]

FSC

round

llc

------

;

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

Table 46 Subaddress 67H

Table 47 Subaddress 68H

Table 48 Subaddress 69H

Table 49 Subaddress 6AH

BIT

SYMBOL

DESCRIPTION

7 to 0

L21O[07:00]

First byte of captioning data, odd field.

LSB of the byte is encoded immediately after run-in and framing code, the MSB of the
byte has to carry the parity bit, in accordance with the definition of line 21 encoding
format.

BIT

SYMBOL

DESCRIPTION

7 to 0

L21O[17:10]

Second byte of captioning data, odd field.

The MSB of the byte has to carry the parity bit, in accordance with the definition of
line 21 encoding format.

BIT

SYMBOL

DESCRIPTION

7 to 0

L21E[07:00]

First byte of extended data, even field.

LSB of the byte is encoded immediately after run-in and framing code, the MSB of the
byte has to carry the parity bit, in accordance with the definition of line 21 encoding
format.

BIT

SYMBOL

DESCRIPTION

7 to 0

L21E[17:10]

Second byte of extended data, even field.

The MSB of the byte has to carry the parity bit, in accordance with the definition of
line 21 encoding format.

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

Table 50 Subaddress 6BH

Table 51 Selection of the signal type on pin RCV1

BIT

SYMBOL

DESCRIPTION

SRCV11

These 2 bits define signal type on pin RCV1; see Table 51

SRCV10

TRCV2

0 = horizontal synchronization is taken from RCV1 port (at bit SYMP = LOW) or from
decoded frame sync of

"ITU-R BT.656" input (at bit SYMP = HIGH); default state after

reset
1 = horizontal synchronization is taken from RCV2 port (at bit SYMP = LOW)

ORCV1

0 = pin RCV1 is switched to input; default state after reset
1 = pin RCV1 is switched to output

PRCV1

0 = polarity of RCV1 as output is active HIGH, rising edge is taken when input; default
state after reset
1 = polarity of RCV1 as output is active LOW, falling edge is taken when input

CBLF

When CBLF = 0.

If ORCV2 = 1, pin RCV2 provides an HREF signal (horizontal reference pulse that is
defined by RCV2S and RCV2E, also during vertical blanking interval); default state
after reset.

If ORCV2 = 0 and bit SYMP = 0, signal input to RCV2 is used for horizontal
synchronization only (if TRCV2 = 1); default state after reset.

When CBLF = 1.

If ORCV2 = 1, pin RCV2 provides a `composite-blanking-not' signal, for example a
reference pulse that is defined by RCV2S and RCV2E, excluding vertical blanking
interval, which is defined by FAL and LAL.

If ORCV2 = 0 and bit SYMP = 0, signal input to RCV2 is used for horizontal
synchronization (if TRCV2 = 1) and as an internal blanking signal.

ORCV2

0 = pin RCV2 is switched to input; default state after reset
1 = pin RCV2 is switched to output

PRCV2

0 = polarity of RCV2 as output is active HIGH, rising edge is taken when input,
respectively; default state after reset
1 = polarity of RCV2 as output is active LOW, falling edge is taken when input,
respectively

SRCV11

SRCV10

RCV1

FUNCTION

Vertical Sync each field; default state after reset

Frame Sync (odd/even)

FSEQ

Field Sequence, vertical sync every fourth field (PAL = 0), eighth field
(PAL = 1) or twelfth field (SECAM = 1)

not applicable

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

Table 52 Subaddress 6CH

Table 53 Subaddress 6DH

Table 54 Subaddress 6EH

Table 55 Selection of phase reset mode

BIT

SYMBOL

DESCRIPTION

7 to 0

HTRIG[7:0]

These are the 8 LSBs of the 11-bit code that sets the horizontal trigger phase related to
the signal on RCV1 or RCV2 input. The 3 MSBs are held in subaddress 6DH;
see Table 53. Values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed.
Increasing HTRIG[10:0] decreases delays of all internally generated timing signals.
Reference mark: analog output horizontal sync (leading slope) coincides with active
edge of RCV used for triggering at HTRIG[10:0] = 4FH (79).

BIT

SYMBOL

DESCRIPTION

HTRIG10

These are the 3 MSBs of the horizontal trigger phase code; see Table 52.

HTRIG9

HTRIG8

VTRIG4

Sets the vertical trigger phase related to signal on RCV1 input. Increasing VTRIG
decreases delays of all internally generated timing signals, measured in half lines;
variation range of VTRIG[4:0] = 0 to 31 (1FH).

VTRIG3

VTRIG2

VTRIG1

VTRIG0

BIT

SYMBOL

DESCRIPTION

SBLBN

0 = vertical blanking is defined by programming of FAL and LAL; default state after reset
1 = vertical blanking is forced in accordance with

"ITU-R BT.624" (50 Hz) or RS170A

(60 Hz)

BLCKON

0 = encoder in normal operation mode
1 = output signal is forced to blanking level; default state after reset

PHRES1

These 2 bits select the phase reset mode of the colour subcarrier generator;
see Table 55.

PHRES0

LDEL1

These 2 bits select the delay on luminance path with reference to chrominance path;
see Table 56.

LDEL0

FLC1

These 2 bits select field length control; see Table 57.

FLC0

PHRES1

PHRES0

DESCRIPTION

no reset or reset via RTCI from SAA7111 if bit RTCE = 1; default value after reset

reset every two lines or SECAM specific if bit SECAM = 1

reset every eight fields

reset every four fields

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

Table 56 Selection of luminance path delay

Table 57 Selection of field length control

Table 58 Subaddress 6FH

Table 59 Selection of line 21 encoding

Table 60 Subaddress 70H

LDEL1

LDEL0

LUMINANCE PATH DELAY

no luminance delay; default value after reset

1 LLC luminance delay

2 LLC luminance delay

3 LLC luminance delay

FLC1

FLC0

DESCRIPTION

interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default value after reset

non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz

non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz

BIT

SYMBOL

DESCRIPTION

CCEN1

These 2 bits enable individual line 21 encoding; see Table 59.

CCEN0

TTXEN

0 = disables teletext insertion; default state after reset
1 = enables teletext insertion

SCCLN4

These 5 bits select the actual line where closed caption or extended data are encoded.

SCCLN3

line = (SCCLN[4:0] + 4) for M-systems

line = (SCCLN[4:0] + 1) for other systems

SCCLN2

SCCLN1

SCCLN0

CCEN1

CCEN0

LINE 21 ENCODING

line 21 encoding off; default value after reset

enables encoding in field 1 (odd)

enables encoding in field 2 (even)

enables encoding in both fields

BIT

SYMBOL

DESCRIPTION

7 to 0

RCV2S[7:0]

These are the 8 LSBs of the 11-bit code that determines the start of the output signal
on the RCV2 pin; the 3 MSBs of the 11-bit code are held at subaddress 72H; see
Table 62. Values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed. Leading
sync slope at CVBS output coincides with leading slope of RCV2 out at RCV2S = 49H.

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

Table 61 Subaddress 71H

Table 62 Subaddress 72H

Table 63 Subaddress 73H

Table 64 Subaddress 74H

Table 65 Subaddress 75H

BIT

SYMBOL

DESCRIPTION

7 to 0

RCV2E[7:0]

These are the 8 LSBs of the 11-bit code that determines the end of the output signal
on the RCV2 pin; the 3 MSBs of the 11-bit code are held at subaddress 72H; see
Table 62. Values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed. Leading
sync slope at CVBS output coincides with trailing slope of RCV2 out at RCV2E = 49H.

BIT

SYMBOL

DESCRIPTION

This bit is reserved and must be set to a logic 0.

RCV2E10

These are the 3 MSBs of end of output signal code; see Table 61.

RCV2E9

RCV2E8

This bit is reserved and must be set to a logic 0.

RCV2S10

These are the 3 MSBs of start of output signal code; see Table 60.

RCV2S9

RCV2S8

BIT

SYMBOL

DESCRIPTION

7 to 0

TTXHS[7:0]

Start of signal on pin TTXRQ; see Fig.23.

PAL: TTXHS[7:0] = 42H

NTSC: TTXHS[7:0] = 54H

BIT

SYMBOL

DESCRIPTION

7 to 0

TTXHD[7:0]

Indicates the delay in clock cycles between rising edge of TTXRQ output and valid
data at pin TTX.

minimum value: TTXHD[7:0] = 2

BIT

SYMBOL

DESCRIPTION

CSYNCA4

Advanced composite sync against RGB output from 0 to 31 LLC clock periods.

CSYNCA3

CSYNCA2

CSYNCA1

CSYNCA0

VS_S2

Vertical sync shift between RCV1 and RCV2 (switched to output); in master mode it is
possible to shift Hsync (RCV2; CBLF = 0) against Vsync (RCV1; SRCV1 = 00).

VS_S1

standard value: VS_S[2:0] = 3

VS_S0

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

Table 66 Subaddress 76H

Table 67 Subaddress 77H

Table 68 Subaddress 78H

Table 69 Subaddress 79H

Table 70 Subaddress 7AH

BIT

SYMBOL

DESCRIPTION

REMARKS

7 to 0

TTXOVS[7:0]

These are the 8 LSBs of the 9-bit code that determines the
first line of occurrence of signal on pin TTXRQ in odd field.
The MSB is held in subaddress 7CH; see Table 72.

PAL: TTXOVS = 05H;
NTSC: TTXOVS = 06H

line = (TTXOVS[8:0] + 4) for M-systems

line = (TTXOVS[8:0] + 1) for other systems

BIT

SYMBOL

DESCRIPTION

REMARKS

7 to 0

TTXOVE[7:0]

These are the 8 LSBs of the 9-bit code that determines the
last line of occurrence of signal on pin TTXRQ in odd field.
The MSB is held in subaddress 7CH; see Table 72.

PAL: TTXOVE = 16H;
NTSC: TTXOVE = 10H

last line = (TTXOVE[8:0] + 3) for M-systems

last line = TTXOVE[8:0] for other systems

BIT

SYMBOL

DESCRIPTION

REMARKS

7 to 0

TTXEVS[7:0]

These are the 8 LSBs of the 9-bit code that determines the
first line of occurrence of signal on pin TTXRQ in even field.
The MSB is held in subaddress 7CH; see Table 72.

PAL: TTXEVS = 04H;
NTSC: TTXEVS = 05H

first line = (TTXEVS[8:0] + 4) for M-systems

first line = (TTXEVS[8:0] + 1) for other systems

BIT

SYMBOL

DESCRIPTION

REMARKS

7 to 0

TTXEVE[7:0]

These are the 8 LSBs of the 9-bit code that determines the
last line of occurrence of signal on pin TTXRQ in even field.
The MSB is held in subaddress 7CH; see Table 72.

PAL: TTXEVE = 16H;
NTSC: TTXEVE = 10H

last line = (TTXEVE[8:0] + 3) for M-systems

last line = TTXEVE[8:0] for other systems

BIT

SYMBOL

DESCRIPTION

7 to 0

FAL[7:0]

These are the 8 LSBs of the 9-bit code that determines the first active line. The MSB
is held in subaddress 7CH; see Table 72. FAL[8:0] = 0 coincides with the first field
synchronization pulse.

first active line = (FAL[8:0] + 4) for M-systems

first active line = (FAL[8:0] + 1) for other systems

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

Table 71 Subaddress 7BH

Table 72 Subaddress 7CH

Table 73 Subaddress 7EH

Table 74 Subaddress 7FH

BIT

SYMBOL

DESCRIPTION

7 to 0

LAL[7:0]

These are the 8 LSBs of the 9-bit code that determines the last active line. The MSB is
held in subaddress 7CH; see Table 72. LAL[8:0] = 0 coincides with the first field
synchronization pulse.

last active line = (LAL[8:0] + 3) for M-systems

last active line = LAL[8:0] for other systems

BIT

SYMBOL

DESCRIPTION

TTX60

0 = enables NABTS (FISE = 1) or European teletext (FISE = 0); default state after
reset
1 = enables World Standard Teletext 60 Hz (FISE = 1)

LAL8

MSB of the last active line code; see Table 71.

TTXO

0 = new teletext protocol selected: at each rising edge of TTXRQ a single teletext bit is
requested (see Fig.23); default state after reset
1 = old teletext protocol selected: the encoder provides a window of TTXRQ going
HIGH; the length of the window depends on the chosen teletext standard (see Fig.23)

FAL8

MSB of the first active line code; see Table 70.

TTXEVE8

MSB of the 9-bit code that selects the last line of occurrence of signal on pin TTXRQ in
even field; see Table 69.

TTXOVE8

MSB of the 9-bit code that selects the last line of occurrence of signal on pin TTXRQ in
odd field; see Table 67.

TTXEVS8

MSB of the 9-bit code that selects the first line of occurrence of signal on pin TTXRQ in
even field; see Table 68.

TTXOVS8

MSB of the 9-bit code that selects the first line of occurrence of signal on pin TTXRQ in
odd field; see Table 66.

BIT

SYMBOL

DESCRIPTION

7 to 0

LINE[12:5]

Individual lines in both fields (PAL counting) can be disabled for insertion of teletext by
the respective LINE bits. Disabled line = LINEnn (50 Hz field rate). This bit mask is
effective only, if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE.

BIT

SYMBOL

DESCRIPTION

7 to 0

LINE[20:13]

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

7.14

Slave transmitter

The slave transmitter slave address is 89H.

Table 75 Subaddress 00H

BIT

SYMBOL

DESCRIPTION

VER2

These 3 bits form the version identification number of the device: it will be changed with
all versions of the IC that have different programming models; current version is
000 binary.

VER1

VER0

CCRDO

1 = closed caption bytes of the odd field have been encoded
0 = the bit is reset after information has been written to the subaddresses 67H and 68H;
it is set immediately after the data has been encoded

CCRDE

1 = closed caption bytes of the even field have been encoded
0 = the bit is reset after information has been written to the subaddresses 69H and 6AH;
it is set immediately after the data has been encoded

not used; set to logic 0

FSEQ

1 = during first field of a sequence (repetition rate: NTSC = 4 fields, PAL = 8 fields,
SECAM = 12 fields)
0 = not first field of a sequence

O_E

1 = during even field
0 = during odd field

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

CHARACTERISTICS

DDD

= 3.0 to 3.6 V; T

amb

= 0 to 70

C; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

Supply

DDA

analog supply voltage

3.15

3.45

DDD

digital supply voltage

3.0

3.6

DDA

analog supply current

note 1

150

DDD

digital supply current

DDD

= 3.3 V; note 1

100

Inputs: LLC1, RCV1, RCV2, MP7 to MP0, RTCI, SA, RESET and TTX

LOW-level input voltage

0.5

+0.8

HIGH-level input voltage

2.0

DDD

+ 0.3

input leakage current

input capacitance

clocks

data

I/Os at
high-impedance

Outputs: RCV1, RCV2 and TTXRQ

LOW-level output voltage

= 2 mA

0.4

HIGH-level output voltage

2 mA

2.4

C-bus: SDA and SCL

LOW-level input voltage

0.5

+0.3V

DD(I2C)

HIGH-level input voltage

0.7V

DD(I2C)

+ 0.3 V

input current

= LOW or HIGH

+10

LOW-level output voltage (pin SDA)

= 3 mA

0.4

output current

during acknowledge

Clock timing: LLC1 and XCLK

LLC1

cycle time

note 2

duty factor t

HIGH

LLC1

LLC1 input

duty factor t

HIGH

XCLK

XCLK output typical
50%

rise time

note 2

fall time

note 2

Input timing: RCV1, RCV2, MP7 to MP0, RTCI, SA and TTX

SU;DAT

input data set-up time

HD;DAT

input data hold time

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

Notes

1. At maximum supply voltage with highly active input signals.

2. The data is for both input and output direction.

3. If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of

subcarrier frequency and line/field frequency.

4. For full digital range, without load, V

DDA

= 3.3 V. The typical voltage swing is 1.35 V, the typical minimum output

voltage (digital zero at DAC) is 0.2 V.

5. Referring to peak-to-peak analog voltages resulting from identical peak-to-peak digital codes.

Crystal oscillator

nominal frequency (usually 27 MHz)

3rd harmonic

MHz

f/f

permissible deviation of nominal
frequency

note 3

+50

RYSTAL SPECIFICATION

amb

ambient temperature

load capacitance

series resistance

mot

motional capacitance (typical)

1.5

20%

1.5 + 20%

par

parallel capacitance (typical)

3.5

20%

3.5 + 20%

Data and reference signal output timing

output load capacitance

7.5

output hold time

output delay time

Outputs: C, VBS, CVBS and RGB

o(p-p)

output signal voltage (peak-to-peak value) note 4

1.25

1.50

inequality of output signal voltages

note 5

int

internal serial resistance

output load resistance

300

output signal bandwidth of DACs

3 dB

MHz

lf(i)

low frequency integral linearity error of
DACs

LSB

lf(d)

low frequency differential linearity error of
DACs

LSB

d(pipe)(MP)

total pipeline delay from MP port

27 MHz

LLC

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

8.1

Explanation of RTCI data bits

1. The HPLL increment is not evaluated by the

SAA7128H; SAA7129H.

2. The SAA7128H; SAA7129H generates the subcarrier

frequency from the FSCPLL increment if enabled
(see item 7.).

3. The PAL bit indicates the line with inverted (R

component of colour difference signal.

4. If the reset bit is enabled (RTCE = 1; DECPH = 1;

PHRES = 00), the phase of the subcarrier is reset in
each line whenever the reset bit of RTCI input is set to
logic 1.

5. If the FISE bit is enabled (RTCE = 1; DECFIS = 1), the

SAA7128H; SAA7129H takes this bit instead of the
FISE bit in subaddress 61H.

6. If the odd/even bit is enabled (RTCE = 1; DECOE = 1),

the SAA7128H; SAA7129H ignores its internally
generated odd/even flag and takes the odd/even bit
from RTCI input.

7. If the colour detection bit is enabled (RTCE = 1;

DECCOL = 1) and no colour was detected (colour
detection bit = 0), the subcarrier frequency is
generated by the SAA7128H; SAA7129H. In the other
case (colour detection bit = 1) the subcarrier
frequency is evaluated out of FSCPLL increment.

If the colour detection bit is disabled (RTCE = 1;
DECCOL = 0), the subcarrier frequency is evaluated
out of FSCPLL increment, independent of the colour
detection bit of RTCI input.

handbook, full pagewidth

128

72 74

0 1

RTCI

HPLL

increment

(1)

FSCPLL increment

(2)

HIGH-to-LOW transition

count start

4 bits

reserved

valid

sample

invalid

sample

not used in SAA7128H/29H

3 bits

reserved

8/LLC

MGL934

LOW

time slot:

(3)

(4)

(6)

(7)

(8)

(5)

Fig.22 RTCI timing.

(1) SAA7111/12 provides 14 to 0 bits, resulting in 2 reserved bits before FSCPLL increment.

(2) SAA7151 provides 21 to 0 bits only, resulting in 5 reserved bits before sequence bit.

(3) Sequence bit: PAL: 0 = (R

Y) line normal, 1 = (R

Y) line inverted; NTSC: 0 = no change.

(4) Reset bit: only from SAA7111 and SAA7112 decoder.

(5) FISE bit: 0 = 50 Hz, 1 = 60 Hz.

(6) Odd/even bit: odd_even from external.

(7) Colour detection: 0 = no colour detected, 1 = colour detected.

(8) Reserved bits: 229 with 50 Hz systems, 226 with 60 Hz systems.

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

8.2

Teletext timing

Time t

is the time needed to interpolate input data TTX

and insert it into the CVBS and VBS output signal, such
that it appears at t

TTX

= 9.78

s (PAL) or t

TTX

= 10.5

(NTSC) after the leading edge of the horizontal
synchronization pulse.

Time t

is the pipeline delay time introduced by the

source that is gated by TTXRQ in order to deliver TTX
data. This delay is programmable by register TTXHD.
For every active HIGH state at output pin TTXRQ, a new
teletext bit must be provided by the source (new protocol)
or a window of TTXRQ going HIGH is provided and the
number of teletext bits, depending on the chosen teletext
standard, is requested at input pin TTX (old protocol).

Since the beginning of the pulses representing the TTXRQ
signal and the delay between the rising edge of TTXRQ
and valid teletext input data are fully programmable
(TTXHS and TTXHD), the TTX data is always inserted at
the correct position after the leading edge of outgoing
horizontal synchronization pulse.

Time t

i(TTXW)

is the internally used insertion window for

TTX data; it has a constant length that allows insertion of
360 teletext bits at a text data rate of 6.9375 Mbits/s (PAL),
296 teletext bits at a text data rate of 5.7272 Mbits/s (WST)
or 288 teletext bits at a text data rate of 5.7272 Mbits/s
(NABTS). The insertion window is not opened if the control
bit TTXEN is logic 0.

Using appropriate programming, all suitable lines of the
odd field (TTXOVS and TTXOVE) plus all suitable lines of
the even field (TTXEVS and TTXEVE) can be used for
teletext insertion.

Fig.23 Teletext timing.

handbook, full pagewidth

ti(TTXW)

tTTX

tPD

tFD

CVBS/Y

TTX

TTXRQ (new)

TTXRQ (old)

text bit #:

10 11

18 19 20

MHB504

2002

Oct

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

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APPLICA

TION INFORMA

TION

book, full pagewidth

MHB583

(1)

VSSA1 to VSSA3

VDDA1 to VDDA3

VDDA4

22, 32, 33

25, 28, 31

UB
0.70 V (p-p)

(2)

DAC6

BLUE

AGND

VSSD1 to VSSD3

5, 18, 38

DGND

0.1

3.3 V analog

0.1

1 nF

10 pF

27.0 MHz

3rd harmonic

XTAL

XTALI

(1)

UG
0.70 V (p-p)

(2)

DAC5

GREEN

AGND

(1)

UR
0.70 V (p-p)

(2)

DAC4

RED

AGND

(1)

UC
0.89 V (p-p)

(2)

DAC3

AGND

(1)

UVBS
1.00 V (p-p)

(2)

DAC2

VBS

AGND

(1)

4.7

UCVBS
1.23 V (p-p)

(2)

DAC1

CVBS

AGND

DGND

use one capacitor
for each VDDA

VDDD1 to VDDD3

6, 17, 39

0.1

3.3 V digital

digital

inputs and

outputs

DGND

use one capacitor
for each VDDD

AGND

SAA7128H
SAA7129H

Fig.24 Application circuit.

(1) Typical value.

(2) For

100

colour bar.

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

9.1

Analog output voltages

The analog output voltages are dependent on the open-loop voltage of the operational amplifiers for full-scale conversion
(typical value 1.35 V), the internal series resistor (typical value 2

), the external series resistor and the external load

impedance.

The digital output signals in front of the DACs under nominal conditions occupy different conversion ranges, as indicated
in Table 76 for a

100

colour bar signal.

Values for the external series resistors result in a 75

load.

Table 76 Digital output signals conversion range

CONVERSION RANGE (peak-to-peak)

CVBS

SYNC-TIP TO PEAK-CARRIER (digits)

Y (VBS)

SYNC-TIP TO WHITE (digits)

RGB (Y)

BLACK TO WHITE AT

GDY = GDC =

6 (digits)

1016

881

712

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

10 PACKAGE OUTLINE

UNIT

(1)

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

EIAJ

0.25
0.05

1.85
1.65

0.25

0.40
0.20

0.25
0.14

10.1

9.9

0.8

1.3

12.9
12.3

1.2
0.8

0.15

0.1

0.15

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.95
0.55

SOT307-2

95-02-04
97-08-01

(1)

10.1

9.9

12.9
12.3

1.2
0.8

Z E

detail X

(A )

pin 1 index

2.5

5 mm

scale

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm

SOT307-2

max.

2.10

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

11 SOLDERING

11.1

Introduction to soldering surface mount
packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"Data Handbook IC26; Integrated Circuit Packages"

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.

11.2

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.

Typical reflow peak temperatures range from
215 to 250

C. The top-surface temperature of the

packages should preferable be kept below 220

C for

thick/large packages, and below 235

C for small/thin

packages.

11.3

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

For packages with leads on two sides and a pitch (e):

larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

For packages with leads on four sides, the footprint must
be placed at a 45

angle to the transport direction of the

printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

11.4

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

11.5

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. For more detailed information on the BGA packages refer to the

"(LF)BGA Application Note" (AN01026); order a copy

from your Philips Semiconductors sales office.

2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

"Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods".

3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder

cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.

4. If wave soldering is considered, then the package must be placed at a 45

angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not

suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

12 REVISION HISTORY

PACKAGE

(1)

SOLDERING METHOD

WAVE

REFLOW

(2)

BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA

not suitable

suitable

HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN,
HVSON, SMS

not suitable

(3)

suitable

PLCC

(4)

, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended

(4)(5)

suitable

SSOP, TSSOP, VSO

not recommended

(6)

suitable

REV

DATE

CPCN

DESCRIPTION

2002

Product specification (9397 750 09727)

Modification:

Chapter 9; value of capacitor in the application circuit
changed to 1 nF

20000308

Product specification (9397 750 06127)

2002 Oct 15

Philips Semiconductors

Product specification

Digital video encoder

SAA7128H; SAA7129H

13 DATA SHEET STATUS

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was

published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

LEVEL

DATA SHEET

STATUS

(1)

PRODUCT

STATUS

(2)(3)

DEFINITION

Objective data

Development

This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.

Preliminary data Qualification

This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.

III

Product data

Production

This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).

14 DEFINITIONS

Short-form specification

The data in a short-form

specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition

Limiting values given are in

accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.

Application information

Applications that are

described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.

15 DISCLAIMERS

Life support applications

These products are not

designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes

Philips Semiconductors

reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status `Production'), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.

SCA74

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Philips Semiconductors a worldwide company

Contact information

For additional information please visit http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.

Printed in The Netherlands

753505/02/pp

Date of release:

2002 Oct 15

Document order number:

9397 750 09727

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SAA7129H/V1

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SAA7129H/V1