April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder
with SCART interface (DMSD2-SCART)

SAA7151B

FEATURES

8-bit performance on chip for luminance and
chrominance signal processing for PAL, NTSC and
SECAM standards

Separate 8-bit luminance and 8-bit chrominance input
signals from Y/C, CVBS, S-Video (S-VHS or Hi8)
sources

SCART signal insertion by means of RGB/YUV
convertion; fast switch handling

Horizontal and vertical sync detection for all standards

Real time control output RTCO

Fast sync recovery of vertical blanking for VCR signals
(bottom flutter compensation)

Controls via the I

C-bus

User programmable aperture correction (horizontal
peaking)

Cross-colour reduction by chrominance comb-filtering
(NTSC) or by special cross-colour cancellation
(SECAM)

8-bit quantization of output signals in 4:1:1 or 4:2:2
formats

720 active samples per line

The YUV bus supports a data rate of 13.5 MHz
(CCIR 601).

(864

) for 50 Hz

(858

) for 60 Hz

Compatible with memory-based features (line-locked
clock)

One 24.576 MHz crystal oscillator for all standards

GENERAL DESCRIPTION

The SAA7151B is a digital multistandard colour-decoder
having two 8-bit input channels, one for CVBS or Y, the
other for chrominance or time-multiplexed
colour-difference signals.

QUICK REFERENCE DATA

ORDERING INFORMATION

Note

1. SOT188-2; 1996 December 16.

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

supply voltage (pins 5, 18, 28, 37 and 52)

4.5

5.5

total supply current (pins 5, 18, 28, 37 and 52)

100

250

input levels

TTL-compatible

output levels

TTL-compatible

amb

operating ambient temperature

EXTENDED TYPE

NUMBER

PACKAGE

PINS

PIN POSITION

MATERIAL

CODE

SAA7151B

mini-pack PLCC

plastic

SOT188

(1)

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

BLOCK DIAGRAM

Fig.1 Block diagram (application circuits see Figs 17, 18 and 19).

ull pagewidth

MEH292

POWER-ON

RESET

COMPONENT PROCESSING;

SCART INTERFACE CONTROL;

FAST SWITCH INSERTION

CHROMINANCE PROCESSOR

SYNCHRONIZATION

LUMINANCE

PROCESSOR

INPUT

INTERFACE

STATUS

C-BUS

CONTROL

OUTPUT

INTERFACE

CLOCK

14 to 17

20 to 23

6 to 13

45 to 50,

53, 54

55 to 62

1, 2

DD1

to V

DD4

5, 18, 28, 52

19, 38, 51, 67

SS1

to V

SS4

GPSW2

SYIS

CPI

test pins

GPSW1

MUXC

FSI

SCART

FSO

RESN

CVBS0 to

CVBS7

CUV0 to

CUV7

SDA

SCL

IICSA

GPSW0

HCL

clock

status

HSY

ODD

CREF

LL27

XTALI

XTAL

FEIN

HREF

UV output

(UV7 to UV0)

output

(Y7 to

Y0)

LFCO

SSA

DDA

5 V

SAA7151A

5 V

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

PINNING

SYMBOL

PIN

DESCRIPTION

connected to ground (shift pin for testing)

connected to ground (action pin for testing)

RESN

reset, active-LOW

CREF

clock reference, sync from external to ensure in-phase signals on the Y-, CUV- and YUV-bus

DD1

5 V supply input 1

CUV0

chrominance input data bits CUV7 to CUV0 (digitized chrominance signals in two's complement
format from a S-Video source (S-VHS, Hi8) or time-multiplexed colour-difference signals from a
YUV(RGB) source or both in combination)

CUV1

CUV2

CUV3

CUV4

CUV5

CUV6

CUV7

CVBS0

CVBS lower input data bits CVBS3 to CVBS0
(CVBS with luminance, chrominance and all sync information in two's complement format)

CVBS1

CVBS2

CVBS3

DD2

5 V supply input 2

SS1

ground 1 (0 V)

CVBS4

CVBS upper input data bits CVBS7 to CVBS4
(CVBS with luminance, chrominance and all sync information in two's complement format)

CVBS5

CVBS6

CVBS7

GPSW1

status bit output FSST0 or port 1 output for general purpose (programmable by subaddress 0C)

GPSW2

status bit output FSST1 or port 2 output for general purpose (programmable by subaddress 0C)

HCL

black level clamp pulse output (begin and stop programmable), e.g. for TDA8708A (ADC)

LL27

line-locked system clock input signal (27 MHz)

DD3

5 V supply input 3

HSY

hor. sync pulse reference output (begin and stop programmable), e.g. for gain adj.TDA8708A
(ADC)

vertical sync output signal (Fig.11)

horizontal sync output signal (Fig.16; start point programmable)

RTCO

real time control output; serial increments of HPLL and FSCPLL and status PAL or SECAM
sequence (Fig.10)

XTAL

24.576 MHz clock output (open-circuit for use with external oscillator)

XTALI

24.576 MHz connection for crystal or external oscillator (TTL compatible squarewave)

SSA

analog ground

LFCO

line frequency control output signal, multiple of horizontal frequency (nominal 6.75 MHz)

DDA

5 V supply input for analog part

SS2

ground 2 (0 V)

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

ODD

odd/even field identification output (odd = HIGH)

SDA

C-bus data line

SCL

C-bus clock line

HREF

horizontal reference for YUV data outputs (for active line 720Y samples long)

IICSA

set module address input of I

C-bus (LOW = 1000 101X; HIGH = 1000 111X)

CPI

clamping pulse input (digital clamping of external UV signals)

Y signal output bits Y7 to Y2 (luminance), part of the digital YUV-bus

SS3

ground 3 (0 V)

DD4

5 V supply input 4

Y signal output bits Y1 to Y0 (luminance), part of the digital YUV-bus

UV7

UV signal output bits UV7 to UV0, part of the digital YUV-bus

UV6

UV5

UV4

UV3

UV2

UV1

UV0

GPSW0

port output for general purpose (programmable by subaddress 0D)

FEIN

fast enable input (active-LOW to control fast switching due to YUV data; HIGH = YUV high-Z

MUXC

multiplexer control output; source select signal for external ADC (UV signal multiplexing)

FSO

fast switch and sync insertion output; gated FS signal from FSI or sync insertion pulse in full screen
RGB mode

SS4

ground 4 (0 V)

FSI

fast switch input signal fed from SCART/peri-TV connector (indicates fast insertion of RGB signals)

SYMBOL

PIN

DESCRIPTION

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

Fig.2 Pin configuration.

handbook, full pagewidth

SAA7151A
SAA7151B

MEH293

CUV4

CUV5

CUV6

CUV7

CVBS0

CVBS1

CVBS2

CVBS3

VDD2

VSS1

CVBS4

CVBS5

CVBS6

CVBS7

GPSW1

GPSW2

HCL

UV2

UV3

UV4

UV5

UV6

UV7

VDD4

VSS3

CPI

LL27

DD3

HSY

SYIS

XTAL

XTALI

SSA

LFCO

DDA

SS2

ODD

SDA

SCL

HREF

IICSA

CUV3

CUV2

CUV1

CUV0

DD1

CREF

RESN

FSI

SS4

FSO

MUXC

FEIN

GPSW0

UV0

UV1

FUNCTIONAL DESCRIPTION

System configuration

The SAA7151B system processes digital TV signals with
line-locked clock in PAL, SECAM and NTSC standards
(CVBS or S-Video) as well as RGB signals coming from a
SCART/peri-TV connector. The different source signals
are switched, if necessary matrixed and converted (Fig.3
and Table 1).
8-bit CVBS data (digitized composite video) and 8-bit UV
data (digitized chrominance and /or time-multiplexed
colour-difference signals) are fed to the SAA7151B. The
data rate is 27 MHz.

Chrominance processing

The 8-bit chrominance input signal (signal "C" out of CVBS
or Y/C in Fig.4) is fed via the input interface to a bandpass
filter for eliminating the DC component, then to the
quadrature demodulator. Subcarrier signals from the local
oscillator (DTO1) with 90 degree phase shift are applied to
its multiplier inputs. The frequency depends on set TV
standard.

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

handbook, full pagewidth

TDA8446

VIDEO

SWITCH AND

MATRIX

SCART

(PERI-TV)

TDA8540

VIDEO

SWITCH

Y/C

CVBS

sync

CVBS/Y/sync

chroma

sync

TDA8709A

8-bit ADC

and multiplexer

(CHROMINANCE)

TDA8708A

8-bit ADC

(LUMINANCE)

CSO

HCL

GPSW1

GPSW2

CPI

SW1

SW2

FSO

FSI

from SCART interface SAA7151B

GA GB

ADI

CPO

to and from SAA7151B

CVBS(7-0)

DO(7-0)

CUV(7-0)

CPI

CLS CLP

MUXC

GPSW1

+5 V

CLK

MEH305-3

I C-bus
(select)

ADI

fast switching of Y signal for insertion

(UV are switched inside SAA7151B)

clamping

sync

CVBS/Y

HCT4053

MULTIPLEXER

U/V

Fig.3 System configuration, RGB fast switch interface included (SCART).

The multipliers operate as a quadrature demodulator for all
PAL and NTSC signals; it operates as a frequency
down-mixer for SECAM signals.
The two multiplier output signals are converted to a serial
UV data stream and applied to two low-pass filter stages,
then to a gain controlled amplifier. A final multiplexed
low-pass filter achieves, together with the preceding
stages, the required bandwidth performance. The from
PAL and NTSC originated signals are applied to a
comb-filter. The signals, originated from SECAM, are fed
through a cloche filter (0 Hz centre frequency), a phase
demodulator and a differentiator to obtain
frequency-demodulated colour-difference signals.

The SECAM signals are fed after de-emphasis to a
cross-over switch, to provide the both serial-transmitted
colour-difference signals. These signals are finally fed via

the fast switch to the output formatter stages and to the
output interface.
Chrominance signals are output in parallel (4:2:2) on the
YUV-bus. The data rate of Y signal (pixel rate) is
13.5 MHz. UV signals have a data rate of 13.5 MHz/2 for
the 4:2.2 format (Table 2) respectively 13.5 MHz/4 for the
4:1.1 format (Table 3).

Component processing and SCART interface control

The 8-bit multiplexed colour-difference input signal (signal
CUV, Fig.1, out of matrixed RGB in Fig.3) is fed via the
input interface to a chrominance stop filter (UV signal only
can pass through; Figures 22 to 24). Here it is clamped
and fed to the offset compensation which can be enabled
or disabled via the I

C-bus.

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

For matrixed RGB signals - the full screen SCART mode
and the fast insertion mode (blanking/switching) are
selectable. The chrominance stop filter is automatically
bypassed in full screen SCART mode.

Full screen RGB mode (SCART):

The CUV digital input signal (7-0) consists of
time-multiplexed samples for U and V. An offset correction
for both signals is applied to correct external clamping

errors. An internal timing correction compensates for slight
differences in timing during sampling. The U and V signals
are delay-compensated and fed to the output formatter.
The format 4:2:2 or 4:1:1 is generated by a switchable
filter.
The control signals for the front end (Figures 3 and 20)
MUXC, status bits FSST1, FSST0 (outputs GPSW2,
GPSW1) and FSO are generated by the SAA7151B.

Table 1

SCART interface control (Fig.3)

MODE

CONNECTION

chroma
output of
TDA8446
to TDA8709A

TDA8709A

luminance
fast switch
TDA8446

input
selector (via
I

C-bus)

TDA8540

FSO GPSW 2

GPSW 1 MUXC

selected
input

CUV
(7-0)

RGB
only

0
0

0
1

high-Z

VIN2

U/V

sync (RGB)

Y/C or
CVBS
only

0
0

1
1

0
1

VIN1

Y (Y/C) or CVBS

Y (Y/C) or
CVBS

Fast
switch

0
0

1
1

0
0

0
1

VIN2

0.5(C

U)/

0.5(C

Y (Y/C) or CVBS

Y (Y/C) or
CVBS

0
0

1
1

0
1

not used

RGB
only

1
1

0
0

0
1

high-Z

VIN2

U/V

Y (RGB)

sync (RGB)

1
1

0
0

1
1

0
1

not used

Fast
switch

1
1

0
0

0
1

VIN2

0.5(C

U)/

0.5(C

Y (RGB)

Y (Y/C) or
CVBS

1
1

0
1

not used

Fast insertion mode:

Fast insertion is applied by FSI pulse to ensure correct
timing. The RGB source signal is matrixed into UV and
inserted into the CVBS or Y/C source signal after two field
periods if FSI pulses are received. The output FSO is set
to HIGH during a determined insertion window (screen
plain minus 6 % of horizontal and vertical deflection).
Switch over depends on the phase of FSI in relation to the
valid pixel sequence depending on the phase-different
weighting factors. They are applied to the original and the

inserted UV data (Figures 6 and 7)
The control signals for the front end (Table 1) MUXC, FSO,
status bits FSST1 and FSST0 (outputs GPSW2 and
GPSW1) are generated by the SAA7151B.

The amplitude of chrominance and colour-difference
signals are scaled down by factor 2 to avoid overloading of
the chrominance analog-to-digital converter. The
amplitudes are reduced in the TDA8446 by signals on lines
GPSW2 and GPSW1.

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

Luminance processing

The luminance input signal, a digital CVBS format or an
8-bit luminance format (S-Video), is fed through a sample
rate converter to reduce the data rate to 13.5 MHz (Fig.5).

Sample rate is converted by means of a switchable
pre-filter. High frequency components are emphasized to
compensate for loss in the following chrominance trap
filter. This chrominance trap filter (f

= 4.43 MHz or

= 3.58 MHz centre frequency selectable) eliminates the

most of the colour carrier signal, therefore, it must be
bypassed for S-Video signals.

The high frequency components of the luminance signal
can be "peaked" in two bandpass filters with selectable
transfer characteristic. A coring circuit (

1 LSB) can

improve the signal, this signal is then added to the original
signal. A switchable amplifier achieves a common DC
amplification, because the DC gains are different in both
chrominance trap modes. Additionally, a cut-off sync pulse
is generated for the original signal in both modes.

Synchronization

The luminance output signal is fed to the synchronization
stage. Its bandwidth is reduced to 1 MHz in a low-pass
filter (sync pre-filter). The sync pulses are sliced and fed to
the phase detectors to be compared with the sub-divided
clock frequency. The resulting output signal is applied to
the loop filter to accumulate all phase deviations. There
are three groups of output timing signals:

a. signals related to data output signals (HREF)
b. signals related to the input signals (HSY, and HCL)
c. signals related to the internal sync phase

All horizontal timings are derived from the main counter,
which represents the internal sync phase. The HREF
signal only with its critical timing is phase-compensated in
relationship to the data output signal. Future circuit
improvements could slightly influence the processing

delays of some internal stages to achieve a changed
timing due to the timing groups b and c.
The HREF signal only controls the data multiplexer phase
and the data output signals.
All timings of the following diagrams are measured with
nominal input signals, for example coming from a pattern
generator. Processing delay times are taken between
input and data output, respectively between internal sync
reference (main counter = 0) and the rising edge of HREF.

Line locked clock frequency

LFCO is required in an external PLL (SAA7157) to
generate the line-locked clock frequency LL27 and CREF.

YUV-bus, digital outputs

The 16-bit YUV-bus transfers digital data from the output
interfaces to a feature box, or to the digital-to-analog
converter (DAC). Outputs are controlled via the I

C-bus in

normal selections, or they are controlled by output enable
chain (FEIN, pin 64). The YUV-bus data rate 13.5 MHz.
Timing is achieved by marking each second positive rising
edge of the clock LL27 synchronized by CREF.

YUV-bus formats

4 : 2 : 2 and 4 : 1 : 1

The output signals Y7 to Y0 are the bits of the digital
luminance signal. The output signals UV7 to UV0 are the
bits of the digital colour-difference signal. The frames in
the Tables 2 and 3 are the time to transfer a full set of
samples. In case of 4 : 2 : 2 format two luminance samples
are transmitted in comparison to one U and one V sample
within one frame. The time frames are controlled by the
HREF signal, which determines the correct UV data
phase. The YUV data outputs can be enabled or set to
3-state position by means of the FEIN signal. FEIN = LOW
enables the output; HIGH on this pin forces the Y and U/V
outputs to a high-impedance state (Fig.6).

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

handbook, full pagewidth

MEH294

INPUT

INTERF

ACE

CHROMINANCE

BANDP

ASS

QUADRA

TURE

DEMODULA

SEQUENCE

PROCESSOR

BURST

ACCUMULA

DIFFERENTIA

DE-EMPHASIS

FSST

OFTS

COLO

OEDY

OEDC

OEHS

CHSB

CCIR

SUVI

COFF

SXCR

FISE

FSAU

FSDL(2-0)

GPSI(2-1)

OFTS

FSIV

ANDARD

DETECTION

PHASE

DEMODULA

AND

AMPLITUDE

DETECT

DISCRETE TIME

OSCILLA

OR (DT

O1)

AND DIVIDER

DELA

COMPENSA

TION

LOOP

FIL

TER

PI1

LOOP

FIL

TER

PI2

LOW

ASS

FIL

TER

CLOCHE

FIL

TER

(SECAM)

LOW

ASS

FIL

TER

OUTPUT

FORMA

TTER

AND OUTPUT

INTERF

ACE

SCAR

INTERF

ACE

CONTROL

GAIN

CONTROLLED

AMPLIFIER

TIME

INTERPOLA

TION

CHROMINANCE

FIL

TER,

OFFSET

COMPENSA

TION

COMB FIL

TER

AND

SECAM

RECOMBINA

TION

AST

SWITCH

AND

WEIGHTING

CSTD(2-0)

ASTD

CDET

to luminance

from luminance

SAA7151B

CHR

OMINANCE

SEQA

PLSE(7-0)

SESE(7-0)

CDVI

CKTS (4-0)

CHCV (7-0)

CKT

O (4-0)

LFIS (2-1)

OSCE

clamping

TCO

CVBS

(7-0)

CUV

(7-0)

BYPS

YDEL0

CDMO

CHRS

UVSS

CDPO

CPI

HUEC(7-0)

(7-0)

HREF

GPSW2

GPSW1

MUXC

FSO

FSI

FEIN

(7-0)

OFTS, IPBP

CGFX, AMPF(3-0)

Fig.4 Detailed block diagram; continued in Fig.5.

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

handbook, full pagewidth

MEH295

SAMPLE RA

CONVER

TER

PRE-FIL

TER

SYNC

VER

TICAL

PROCESSOR

HCLB (7-0)

HCLS (7-0)

HSYB (7-0)

HSYS (7-0)

HPHI (7-0)

IDEL

(7-0)

C-BUS

CONTROL

PHASE DETECT

FINE

PHASE DETECT

COARSE

PROGRAMMABLE

DELA

DISCRETE TIME

OSCILLA

(DT

O2)

DAC

FIDT

VNOI (1-0)

WIND

BOFL

BFON

FSEL

AUFD

COUNTER

SCEN

OEVS

OEHS

VTRC

HLCK

HPLL

HCL

GPSW0

HLCK

HSY

LFCO

LINE-LOCKED

CLOCK

GENERA

LOOP

FIL

TER

SYNC SLICER

OFFSET

COMPENSA

TION

PRE-FIL

TER

PREF

LUMINANCE

SAA7151B

SYNC

from input interface

to output interface

BYPS

BPSS

(1-0)

PREF

BYPS

APER

(1-0)

YDEL

(3-1)

CORI

CORING

TCHING

AMPLIFIER

CHROMINANCE

TRAP

ARIABLE DELA

COMPENSA

TION

ARIABLE

BANDP

ASS

FIL

TER

WEIGHTING

AND

ADDING ST

AGE

SCL

SDA

IICSA

ODD

CREF

LL27

YST

CLOCK

GENERA

ALI

Fig.5 Detailed block diagram; continued from Fig.4.

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

Table 2

for the 4 : 2 : 2 format (720 pixels per line). The quoted frequencies are valid on the YUV-bus. The time
frames are controlled by the HREF signal.

Table 3

for the 4 : 1 : 1 format (720 pixels per line). The quoted frequencies are valid on the YUV-bus. The time
frames are controlled by the HREF signal.

OUTPUT

PIXEL BYTE SEQUENCE

Y0 (LSB)

Y7 (MSB)

UV0 (LSB)

UV1

UV2

UV3

UV4

UV5

UV6

UV7 (MSB)

Y frame

UV frame

OUTPUT

PIXEL BYTE SEQUENCE

Y0 (LSB)

Y7 (MSB)

UV0 (LSB)

UV1

UV2

UV3

UV4

UV5

UV6

UV7 (MSB)

Y frame

UV frame

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

Signal levels (Figures 12, 13 and 14)

The nominal input and output signal levels are defined by a colour bar signal with 75 % colour, 100 % saturation and
100 % luminance amplitude (EBU colour bar).

CUV-bus input format

The CUV-bus transfers the digital chrominance/colour-difference signals from the ADC to the SAA7151B (Fig.6; Table 1):

normal mode for digital chrominance transmission.

UV colour-difference mode for colour-difference signals UV (out of matrixed RGB signals)

FS mode (fast switch mode; UV inserted into chrominance signal C with addition of the two signal spectra).

RTCO output

The RTCO output signal (Fig.10) contains serialized information about actual clock frequency, subcarrier frequency and
PAL/SECAM sequence. This signal may preferably be used with the frequency-locked digital video encoder SAA7199B.

Fig.6 Timing example of fast enable input (FEIN).

handbook, full pagewidth

MEH548

HREF

FEIN

YUV

CREF

tSU

tHD

tOH

tOS

from 3-state

to 3-state

LL27

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

Fig.7

CUV input formats.
(1) each second sample only after a MUXC change is taken for down-sampling to 13.5 MHz to reduce
cross-talk components between U and V signals.

handbook, full pagewidth

MEH332

(1)

(V1

C1)/2

(U3

C3)/2

(V0

C0)/2

(V1

C1)/2

(U2

C2)/2

(U3

C3)/2

(V4

C0)/2

(V5

C5)/2

(V5

C5)/2

LL27 clock

LL13.5 clock

MUXC

chrominance

UV colour-difference mode (UV pixel byte sequence)

colour-
difference

valid colour-
difference

CUV

valid CUV

Fast switch mode (data insertion)

Normal mode (chrominance pixel byte sequence)

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

Fig.8 Addition of weighted components.

handbook, full pagewidth

MEH307

7/8 old

1/8 new

3/4 old

1/4 new

5/8 old

3/8 new

1/2 old

1/2 new

0 old

1 new

new

old

T(n

T(n)

Note: in 4:2:2 format weighting
in 1/4 steps only.

T(n

1/8 old

7/8 new

1/4 old

3/4 new

3/8 old

5/8 new

Fig.9 Weighting factors of fast switching for 4:2:2 and 4:1:1 formats.

handbook, full pagewidth

MEH308

U0, V0

U1, V1

U0, V0

U2, V2

U3, V3

LL6.75

LL27

LL3.375

LL27

3/4 1/2 1/4

fast switch weighting for 4:2:2 format

7/8 3/4 5/8 1/2 3/8 1/4 1/8

fast switch weighting for 4:1:1 format

10 11 12 13 14 15 16

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

Fig.10 Line control by HREF in 4:2:2 format for 50 Hz and 60 Hz systems.

handbook, full pagewidth

MEH297

start of
active line

Byte number for pixels:

Y signal

50/60 Hz

U and V signal

HREF

CREF

LL27

handbook, full pagewidth

MEH298

LL27

CREF

HREF

end of
active line

Byte number for pixels:

Y signal

714

715

716

717

718

719

U714

V714

U716

V716

U718

V718

50/60 Hz

U and V signal

Fig.11 RTCO timing.

handbook, full pagewidth

MEH341

RTCO

(1)

Sequence bit:

SECAM: 0 equals DB-line

1 equals DR-line

PAL:

0 equals (R-Y) line normal
1 equals (R-Y) line inverted

NTSC:

0 (no change)

(2)

Reserve bits: 236 for 50 Hz systems; 233 for 60 Hz systems

128 clocks

HPLL

increment

bits 13 to 0

FSCPLL

increment

bits 21 to 0

H/L transition

(counter start)

valid

sequence bit

(1)

reserved

(2)

1 0

bit

time slot
(LL27/4)

4 bits

reserve

5 bits

reserve

not valid

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

Fig.14 Input and output signal ranges in DTV mode (digital TV).

handbook, full pagewidth

luminance

50 Hz mode

luminance

60 Hz mode

chrominance

50 Hz mode

chrominance

60 Hz mode

132

128

103

127

106

clipped

sync

reserved

blanking level

chrominance

component of

colour-difference

signal

103

128

127

MEH299

105

100

U-component

output signal range

127

100

101

128

127

105

106

128

blue 75%

yellow 75%

(d) U output signal range (B

Y).

V-component

output signal range

red 75%

cyan 75%

(e) V output signal range (R

Y).

luminance signal

output range

128

255

235

white 100%

black

Notes: 1. All levels related to EBU colour bar.

2. Values in decimal at 100% luminance and 75% chrominance amplitude

(b) CUV input signal range

(U and V out of RGB;
in FS mode ranges

0.5).

(a) CVBS input signal range.

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

Fig.15 Input and output signal ranges in CCIR mode.

Notes: 1. All levels are related to EBU colour bar.

2. Values in decimal at 100 % luminance and 75 % chrominance amplitude.

3. For SECAM input signals the CCIR levels will be exceeded.

handbook, full pagewidth

luminance

50 Hz mode

luminance

60 Hz mode

chrominance

50 Hz mode

chrominance

60 Hz mode

132

128

103

127

106

clipped

sync

reserved

blanking level

100% white

chrominance

component of

colour-difference

signal

128

127

MEH300

U-component

output signal range

128

255

212

blue 75%

yellow 75%

(d) U output signal range (B

Y).

V-component

output signal range

128

255

212

red 75%

cyan 75%

(e) V output signal range (R

Y).

luminance signal

output range

128

255

235

white 100%

black

(b) CUV input signal range

(U and V out of RGB;
in FS mode ranges

0.5).

(a) CVBS input signal range.

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

Fig.16 Horizontal sync and clamping timing for 50/60 Hz (signals HSY, HCL, HREF and HS).

handbook, full pagewidth

MEH549

Yout

2/LL27

burst

128

191

127

432

431

235

83.5

2/LL27(1)

2/LL27 (50 HZ)

2/LL27 (60 HZ)

144

2/LL27 (50 HZ)

138

2/LL27 (60 HZ)

HREF length fix

2/LL27 (50 HZ)

2/LL27 (60 HZ)

2/LL27

720

2/LL27

HREF position

0...

...719

CVBS

HSY
step size 2/LL27

HCL

Y-output

HREF

HSY
programming
range
(step size: 2/LLC)

HCL
programming
range
(step size: 2/LL27)

HS
programming range
(step size: 8/LL27)

(1)

the processing delay will be ifluenced in future enhancements

(1) the processing delay will be influenced in future enhancements.

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134); ground pins 19, 35, 38, 51 and 67 as well as
supply pins 5, 18, 28, 37 and 52 connected together.

Note

1. Equivalent to discharging a 100 pF capacitor through a 1.5 k

series resistor; inputs and outputs are protected

against electrostatic discharge in normal handling. Normal precautions appropriate to handle MOS devices is
recommended (

"Handling MOS Devices").

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

supply voltage (pins 5, 18, 28, 37, 52)

0.5

7.0

diff GND

difference voltage V

SS A

SS(1 to 4)

100

voltage on all inputs

0.5

voltage on all outputs (I

O max

= 20 mA)

0.5

tot

total power dissipation

2.5

stg

storage temperature range

150

amb

operating ambient temperature range

ESD

electrostatic handling

(1)

for all pins

2000

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

CHARACTERISTICS

= 4.5 to 5.5 V; T

amb

= 0 to 70

C unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

supply voltage range (pins 5, 18, 28, 37, 52)

4.5

5.5

total supply current (pins 5, 18, 28, 37, 52)

= 5 V; inputs LOW;

outputs not connected

100

250

C-bus, SDA and SCL (pins 40 and 41)

I L

input voltage LOW

0.5

1.5

I H

input voltage HIGH

0.5

40, 41

input current

ACK

output current on pin 40

acknowledge

O L

output voltage at acknowledge

= 3 mA

0.4

Data, clock and control inputs (pins 3, 4, 6 to 17, 20 to 23, 27, 34, 64 and 68); Figures 14 and 15

I L

LL27 input voltage (pin 27)

LOW

0.5

0.6

I H

HIGH

2.4

0.5

I L

other input voltages

LOW

0.5

0.8

I H

HIGH

2.0

0.5

leak

input leakage current

input capacitance

data inputs; note 1

I/O high-impedance

clock inputs

SU.DAT

input data set-up time

Fig.17

HD.DAT

input data hold time

YUV-bus, HREF and VS outputs (pins 30, 42, 45 to 50 and pins 53 to 62), Figures 10, 14 and 15

O L

output voltage LOW

notes 1 and 2

0.6

O H

output voltage HIGH

2.4

load capacitor

LFCO output (pin 36)

output signal (peak-to-peak value)

note 2

1.4

2.6

output voltage range

Control outputs (pins 24 to 26, 29, 31, 32, 33, 39, 63, 65 and 66); Figures 12, 16 and 17

O L

output voltage LOW

notes 1 and 2

0.6

O H

output voltage HIGH

2.4

load capacitor

7.5

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

Notes

1. Data output signals are Y7 to Y0 and UV7 to UV0. All other are control signals.

2. Levels are measured with load circuit. YUV-bus, HREF and VS outputs with 1.2 k

in parallel to 50 pF at 3 V

(TTL load);

LFCO output with 10 k

in parallel to 15 pF and other outputs with 1.2 k

in parallel to 25 pF at 3 V (TTL load).

3. Recommended crystal: Philips 4322 143 05291.

4. t

, t

and t

include t

and t

Timing of YUV-bus and control outputs

Figures 10, 12 and 13

output signal hold time

YUV, HREF, VS
at C

= 15 pF;

controls at C

= 7.5 pF

output set-up time

YUV, HREF, VS
at C

= 50 pF;

controls at C

= 25 pF

data output disable transition time

to 3-state condition

data output enable transition time

from 3-state condition

Chrominance PLL

catching range

400

Crystal oscillator

Figures 19 and 20; note 3

nominal frequency

3rd harmonic

24.576

MHz

f / f

permissible deviation f

temperature deviation from f

crystal specification:

temperature range T

amb

load capacitance C

series resonance resistance R

motional capacitance C

1.5

20%

parallel capacitance C

3.5

20%

Line locked clock input LL27 (pin 27)

Fig.9 and 17

LL27

cycle time

note 4

duty factor

LL27H

LL27

rise time

fall time

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

Fig.19 Application of SAA7151B.

handbook, full pagewidth

MEH328

680

0.1

VDD

680

0.1

2.2

0.1

12
pF

1 nF

digital

SAA7157

MUXC

FSO

GPSW1

digital

analog

FSI

VDDA

VSSA

GPSW2

RESN

LL27A

CREF

LL27B

LL13A

LL13B

RESN

LFCO

UV0

UV7 to UV0

UV1

UV2

UV3

UV4

UV5

UV6

UV7

Y7 to Y0

YUV-bus

RTCO

HSY

HCL

HREF

ODD

GPSW0

SDA

C-bus

SCL

FEIN

BAT45

13 MHz

(from SCART)

IICSA

CUV0

chrominance

CUV7 to CUV0

luminance

CVBS7 to CVBS0

X1 :
Philips 4322 143 05291

CUV1

CUV2

CUV3

CUV4

CUV5

CUV6

CUV7

24.576 MHz

digital

CPI

67 51 38 19

SAA7151B

5 V

VDD analog

VDD digital

5 V

digital

150

VSS

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

Fig.20 Application of input signal selecting (SCART interface).

handbook, full pagewidth

MEH330

4.7 k

0.1

4.7

2.2

0.1

0.15

0.1

1 k

chrominance

bandpass filter

12 V

5 V

sync

from SCAR

connector

1 nF

SCL

SDA

unused signal

outputs

to SAA7151B

C-bus

TDA8446

TDA8540

CVBS

(chrominance)

10 k

1.6 k

330

150

0.1

7808
stabilizer

audio

source
control

220 pF

150

SDA
(to SAA7151B)

SCL

CLO

GPSW1

HCL

C signal

FSO

from / to

TDA8708/09

GPSW2

CVBS/Y

sync

V signal

Y signal

U signal

0.1

8 V

12 V

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

Fig.21 Application circuit analog-to-digital conversions.

handbook, full pagewidth

MEH329

CVBS0

CVBS1

CVBS2

CVBS3

CLK

CVBS4

CVBS3

CVBS2

CVBS7

DDO

DDA

DDD

DDA

1 k

220

2 k

6.8 k

100 k

680

TDA8708A

4.7

0.1

0.22

0.1

to pin 8

U signal

from pin 17

V signal

from pin 15

2 MHz

low-pass

filters

5.6

3 k

3.3 k

1.5 k

1.2 k

1 k

6.2 k

1 k

0.1

0.22

68 pF

analog

2.2 k

120

5.6

0.1

VIN0

from/to TDA8446

1 nF

BC547

(

5 V)

or CVBS

from pin 16

C signal

from pin 1

VIN1

VIN2

1 mH

33 pF

digital

CUV(7-0)

GPSW1

GPSW2

MUXC

analog

HCL

to pin 9

of TDA8446

CLO from pin 4

of TDA8446

LL27A

UV gain level for CCIR

5 V (analog supply)

5 V (digital supply)

5 MHz low-pass

filter

NOR

VIN2

VIN1

VIN0

TDA8709A

HCT4053

6, 8,

CUV0

CUV1

CUV2

CUV3

DDD

DDA

DDO

CLK

CPI

HCL

HSY

CVBS(7-0)

CUV4

CUV5

CUV6

CUV7

from/to SAA7151B

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

C-BUS FORMAT

Note

1. If more than 1 byte DATA are transmitted, then auto-increment of the subaddress is performed.

Remarks: - Prior to reset of the IC all outputs are undefined.

- After power-on reset, the control register 12 (hex) is set to 00 (hex).

SLAVE ADDRESS

SUBADDRESS

DATA0

DATAn

start condition

SLAVE
ADDRESS

1000 101X (IICSA = LOW) or 1000 111X (IICSA = HIGH)

acknowledge, generated by the slave

SUBADDRESS

(1)

subaddress byte (Table 5)

DATA

data byte (Table 5)

stop condition

read/write control bit
X = 0, order to write (the circuit is slave receiver)
X = 1, order to read (the circuit is slave transmitter)

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

Table 5

C-bus; DATA for status byte (X in address byte = 1; slave address 8B (hex) at IICSA = LOW or 8F (hex) at

IICSA = HIGH)

FUNCTION

DATA

status byte

STTC

HLCK

FIDT

FSST1

FSST0 CDET2

CDET1

CDET0

Function of the bits:

STTC

Status time constant (to be used for gogical combfilter SAA7152)

0 = TV mode; 1 = VCR mode

HLCK

Horizontal PLL information:

0 = HPLL locked; 1 = HPLL unlocked

FIDT

Field information

0 = 50 Hz system detected; 1 = 60 Hz system detected

FSST1 to FSST0

Fast switching output mode:

FSST1

FSST0

mode

0
0
1
1

0
1
0
1

RGB; FSI = HIGH (pin 68)
Y/C; FSI = LOW (pin 68)
fast switching (toggle)
not used

CDET2 to CDET0

Identified colour standard

CDET2

CDET2 standard

0
0
0
0

0
0
1
1

0
1
0
1

PAL-B/G, -H, -I; 50 Hz
PAL-N; 50 Hz
SECAM; 50 Hz
PAL-M; 60 Hz

1
1
1
1

0
0
1
1

0
1
0
1

PAL 4.43; 60 Hz
NTSC-M; 60 Hz
NTSC 4.43; 60 Hz
black/white

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

Table 6

C-bus; subaddress and data bytes for writing (X in address byte = 0; slave address 8A (hex) at

IICSA = LOW or 8E at IICSA = HIGH)

function

subaddress byte

data byte

increment delay
H-sync HSY begin
H-sync HSY stop

00
01
02

IDEL7
HSYB7
HSYS7

IDEL6
HSYB6
HSYS6

IDEL5
HSYB5
HSYS5

IDEL4
HSYB4
HSYS4

IDEL3
HSYB3
HSYS3

IDEL2
HSYB2
HSYS2

IDEL1
HSYB1
HSYS1

IDEL0
HSYB0
HSYS0

H-clamp HCL begin
H-clamp HCL stop
H-sync after PHI1

03
04
05

HCLB7
HCLS7
HPHI7

HCLB6
HCLS6
HPHI6

HCLB5
HCLS5
HPHI5

HCLB4
HCLS4
HPHI4

HCLB3
HCLS3
HPHI3

HCLB2
HCLS2
HPHI2

HCLB1
HCLS1
HPHI1

HCLB0
HCLS0
HPHI0

luminance control
hue control
miscellaneous controls #1

06
07
08

BYPS
HUEC7
CSTD2

PREF
HUEC6
CSTD1

BPSS1
HUEC5
CSTD0

BPSS0
HUEC4
CKTQ4

BFBY
HUEC3
CKTQ3

CORI
HUEC2
CKTQ2

APER1
HUEC1
CKTQ1

APER0
HUEC0
CKTQ0

miscellaneous controls #2
PAL switch sensitivity
SECAM switch sensitivity

09
0A
0B

OSCE
PLSE7
SESE7

LFIS1
PLSE6
SESE6

LFIS0
PLSE5
SESE5

CKTS4
PLSE4
SESE4

CKTS3
PLSE3
SESE3

CKTS2
PLSE2
SESE2

CKTS1
PLSE1
SESE1

CKTS0
PLSE0
SESE0

miscellaneous controls #3
miscellaneous controls #4
miscellaneous controls #5

0C
0D
0E

FSAU
COLO
CCIR

GPSI2
CHSB
COFF

GPSI1
GPSW0
OEHS

CGFX
SUVI
OEVS

AMPF3
SXCR
UVSS

AMPF2
FSDL2
CHRS

AMPF1
FSDL1
CDMO

AMPF0
FSDL0
CDPO

miscellaneous controls #6
miscellaneous controls #7

0F
10

AUFD
ASTD

FSEL
OFTS

HPLL
IPBP

SCEN
CDVI

VTRC
YDEL3

MUIV
YDEL2

FSIV
YDEL1

WIND
YDEL0

chroma gain reference
miscellaneous controls #8

11
12

CHCV7
OEDY

CHCV6
OEDC

CHCV5
VNOI1

CHCV4
VNOI0

CHCV3
BFON

CHCV2
BOFL2

CHCV1
BOFL1

CHCV0
BOFL0

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

Function of the bits of Table 6

DEL7 to IDEL0

Increment delay time, step size = 4/LL27 = 148 ns

(1)

"00"

D7 D6 D5 D4

decimal number

note

1 to

110

minimum

148 ns

16.3

s (outside available range)

111 to

214

16.44

31.7

s (maximum value at FSEL = 1)

215

31.85

s (outside central counter range

at FSEL = 1

(2)

)

216

32.0

s (maximum value at FSEL = 0

(2)

)

217 to

256

32.148

s (outside central counter range

at FSEL = 0

(2)

)

37.9

s (outside central counter

(2)

)

HSYB7 to HSYB0

Horizontal sync begin, step size = 2/LL27 = 74 ns

HSYS7 to HSYS0

Horizontal sync stop, step size = 2/LL27 = 74 ns

"01" and "02"

D2 D1

D0 decimal multiplier

note

191 to 1

14.2

s (maximum negative value)

74 ns

0 equals reference value

1 to

74 ns

4.7

HCLB7 to HCLB0

Horizontal clamp begin, step size = 2/LL27 = 74 ns

HCLS7 to HCLS0

Horizontal clamp stop, step size = 2/LL27 = 74 ns

"03" and "04"

D2 D1

D0 decimal multiplier

note

127 to 1

9.4

s (maximum negative value)

74 ns

0 equals reference value

1 to

128

74 ns

9.5

s (maximum positive value)

HPHI7 to HPHI0

Horizontal sync start, step size = 8/LL27 = 296 ns

"05"

D2 D1

D0 decimal multiplier

note

0
0

1
1

1
0

1
1

1
0

1
1

127 to

109

) forbidden (outside available central
)

counter range)

108 to

s (maximum negative value)

0.296 ns

0 equals reference value

1
1

1
0

1
1

1
0

1
1

1
0

1
1

1 to

107

0.296

31.7

s (maximum positive value)

1
1

0
0

1
0

0
0

1
0

0
0

108 to

128

) forbidden (outside available central
)

counter range)

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

BYPS
"06"

Input mode select bit:

0 = CVBS mode (chroma trap active)
1 = S-Video mode (chroma trap by-passed)

PREF

Use of pre-emphasis (to be used if chrominance trap is active):

0 = pre-filter bypassed; 1 = pre-filter on

BPSS1 to BPSS0

Aperture bandpass to select different centre frequencies (Figures 25 to 40):

BPSS1

BPSS0

centre frequency

0
0
1
1

0
1
0
1

4.1 MHz
3.8 MHz
2.6 MHz
2.9 MHz

BFBY

Bandfilter bypass switching:

0 = bandfilter active; 1 = bandfilter bypassed

CORI

Coring function:

0 = coring off; 1 =

1 LSB coring

APER1 to APER0

Aperture factor (Figures 25 to 40):

APER1

APER0

factor

0
0
1
1

0
1
0
1

0
0.25
0.5
1

HUE7 to HUE0
"07"

Hue control from

178.6

180.0

, equals data bytes 7F to 80 (hex); 0

equals 00.

CSTD2 to CSTD0

Forced colour standard of input signal;

"08"

CSTD2

CSTD1

CSTD0

standard

0
0
0
0

0
0
1
1

0
1
0
1

PAL-B/G, -H, -I; 50 Hz
PAL-N; 50 Hz
SECAM; 50 Hz
PAL-M; 60 Hz

1
1
1
1

0
0
1
1

0
1
0
1

PAL 4.43; 60 Hz
NTSC-M; 60 Hz
NTSC 4.43; 60 Hz
black/white

CKTQ4 to CKTQ0

Colour killer threshold QAM (PAL/NTSC):

CKTQ4

CKTQ3

CKTQ2

CKTQ1

CKTQ0

1
1
0

1
0
0

approximately

30 to

24 dB

24 dB to

18 dB

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

OSCE
"09"

External UV offset compensation: 0 = disabled; 1 = enabled

LFIS1 to LFIS0

Chrominance gain control (AGC filter):

LFIS1

LFIS0

control of loop filter time constant

0
0
1
1

0
1
0
1

slow
medium
fast
actual gain, stored (for test purposes only)

CKTS4 to CKTS0

Colour killer threshold SECAM as previously described under CKTQ subaddress "08"

PLSE7 to PLSE0
"0A"

PAL switch sensitivity from LOW to HIGH (HIGH means immediate sequence correction), equals FF to
00 (hex), MEDIUM equals 80.

SESE7 to SESE0
"0B"

SECAM switch sensitivity from LOW to HIGH (HIGH means immediate sequence correction), equals FF
to 00 (hex), MEDIUM equals 80.

FSAU; GPSI2,

Set port outputs (general purpose switching, internal)

and GPSI1

FSAU

GPSI2

GPSI1

output GPSW2 (pin 25)

output GPSW1 (pin 24)

"0C"

0
0
0
0

0
0
1
1

0
1
0
1

LOW
LOW
HIGH
HIGH

LOW
HIGH
LOW
HIGH

status bit FSST1 set

status bit FSST0 set

CGFX

Chrominance gain pre-determination: 0 = gain controlled via loop; 1 = gain set by AMPF-bits

AMPF3 to AMPF0

Chrominance amplification factor

AMPF3

AMPF2

AMPF1

AMPF0

gain

0
0
0

0
1
1

0
0
0

0
0
1

6 dB

0 dB

1.5 dB

3 to

16.5 dB (approximately 1.5 dB steps)

17 dB

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

COLO
"0D"

Colour-on bit:

0 = colour-killer automatically enabled;
1 = forced colour-on.

CHSB

Chrominance (UV) output code:

0 = two's complement; 1 = straightly binary

GPSW0

General purpose port output (pin 63):

0 = LOW; 1 = HIGH

SUVI

SECAM UV output signal polarity:

0 = U and V positive; 1 = U and V negative

SXCR

SECAM cross-colour reduction:

0 = off; 1 = on

FDSL2 to FDSL0

Fast switching delay adjustment in 37 ns steps:

FDSL2

FDSL1

FDSL0

delay

0
0
0
0

0
0
1
1

0
1
0
1

0
37 ns
74 ns
111 ns

1
1
1
1

0
0
1
1

0
1
0
1

148 ns (negative delay)

111 ns

74 ns

37 ns

CCIR
"0E"

Set CCIR mode: 0 = digital TV mode (DTV); 1 = CCIR mode

COFF

Set colour off: 0 = colour on; 1 = colour off

OEHS

Enable horizontal sync outputs HS and HREF:

0 = output high-impedance;
1 = HS and HREF enabled

OEVS

Enable vertical sync output VS:

0 = output high-impedance; 1 = VS enabled

UVSS

Select UV pixel sample:

1 = first pixel after U/V signal has changed;
0 = second pixel (free of crosstalk signals)

CHRS

S-Video input mode:

0 = chrominance signal from CVBS or CUV input

and controlled by BYPS (subaddress 06);

1 = S-Video mode; chrominance signal from CUV input

CDMO, CDPO

Chrominance delay:

CDMO

CDPO

0
1
0

0
X
1

no delay

37 ns (negative delay)

37 ns

AUFD
"0F"

Automatic field detection:

0 = field selection by FSEL-bit;
1 = automatic field detection

FSEL

Field select (AUFD-bit = 0):

0 = 50 Hz (625 lines);
1 = 60 Hz (525 lines)

HPLL

Horizontal PLL:

0 = PLL closed; 1 = PLL open, horizontal frequency fixed

SCEN

Sync and clamping pulse enable:

0 = HCL and HSY outputs HIGH (pins 26 and
29);
1 = HCL and HSY outputs active.

VTRC

VTR/TV mode select:

0 = TV mode (slow time constant);
1 = VTR mode (fast time constant).

MUIV

MUXC signal invertion:

0 = inverted; 1 = not inverted

FSIV

Fast switch input signal inversion:

0 = not inverted; 1 = inverted

WIND

Narrow fast switch window:

0 = off; 1 = on

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

ASTD
"10"

Automatic standard switching:

0 = off; 1 = on

OFTS

Select output format:

0 = 4 : 1 : 1 format; 1 = 4 : 2 : 2 format.

IPBP

External UV signal interpolation filter:

0 = active; 1 = bypassed

CDVI

Chrominance PLL filter selection for:

0 = VTR or TV source; 1 = fast time constant

for FSC-PLL (only for special applications)

YDEL3 to YDEL0

Luminance delay compensation in 37 ns steps:

YDEL3

YDEL2

YDEL1

YDEL0

delay

0
0

0
1

)
)

0 to 259 ns (step 0 to 7)

1
1

0
1

)
)

296 to

37 ns (negative delay;

step -8 to

-1)

CHCV7 to CHCV0 Chroma gain reference value

"11"

D2 D1

gain

1
:
0
:
0
:
0

1
:
0
:
1
:
0

maximum gain

DTV level

CCIR level

minimum gain

)
)
)
)
)

default programmed values
dependent on application

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

Notes

1. an internal sign-bit D8 set to HIGH indicates that all values are always negative

2. H-PLL does not operate in this condition; the system clock frequency is set to a value fixed by the last update and is

within

7.1 % of the nominal frequency.

OEDY
"12"
OEDC

Enable Y signals on YUV-bus:

0 = output high-impedance; 1 = output active

(dependent on FEIN)

Enable UV signals on YUV-bus:

0 = output high-impedance; 1 = output active

(dependent on FEIN)

VNOI1, VNOI0

Vertical noise reduction mode:

VNOI1

VNOI0

mode

0
0
1
1

0
1
0
1

normal
searching
free-running
bypassed

BFON

Bottom flutter compensation switching: 0 = off; 1 = on (controlled by BOFL-bit)

BOFL2 to BOFL0

Bottom flutter compensation

BOFL2

BOFL1

BOFL0

start at line number

0
0

1
1

0
0

1
1

0
1

297 for PAL (247 for NTSC; active to end of field)
298 for PAL (248 for NTSC; active to end of field)
.

303 for PAL (253 for NTSC; active to end of field)
304 for PAL (254 for NTSC; active to end of field)

The bottom flutter circuit is able to compensate for horizontal phase jump of up to

Note: The bottom flutter gate is active at

- HPLL is locked
- HPLL in VTR mode
- the vertical noise limiter (VNL)

is in the VTR mode

- gating is switched by

BFON-bit = 1 (subaddress 12)

Gate 2

Gate 1

HPLL function

0
1
0
1

0
0
1
1

normal
disabled
double speed
unused

vertical

pulse

gate 2

gate 1

programmable by BOFL(2-0)

000

111

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

Fig.22 Frequency response of chroma stop filter in

colour-difference mode for 50 Hz PAL. Filter
is only active in fast switching mode, but
bypassed in RGB mode. The selected filter
is dependent on actual detected colour
standard.

handbook, halfpage

MEH326

fY (MHz)

(dB)

PAL

Fig.23 Frequency response of chroma stop filter in

colour-difference mode for 60 Hz NTSC.
Filter is only active in fast switching mode,
but bypassed in RGB mode. The selected
filter is dependent on actual detected colour
standard.

handbook, halfpage

MEH325

fY (MHz)

(dB)

NTSC

Fig.24 Frequency response of chroma stop filter colour-difference mode for 50 Hz SECAM. Filter is only active

in fast switching mode, but bypassed in RGB mode. The selected filter is dependent on actual detected
colour standard.

handbook, halfpage

MEH327

fY (MHz)

(dB)

SECAM

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

Fig.25 Maximum luminance peaking control as a function of four different aperture centre frequencies

controllable by subaddress byte 06; aperture factor 1; coring off; chroma trap on; pre-filter on; and
bandfilter on.

handbook, full pagewidth

MEH309

fY (MHz)

(dB)

63h

43h

53h

43h

53h

73h

63h

73h

50 Hz PAL/SECAM;

pre-filter on

Fig.26 3.8 MHz luminance peaking control as a function of four different aperture factors controllable by

subaddress byte 06; coring off; chroma trap on; pre-filter on and bandfilter on.

handbook, full pagewidth

MEH310

fY (MHz)

(dB)

40h

41h

42h

43h

40h

41h

42h

43h

50 Hz PAL/SECAM;

pre-filter on

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

Fig.27 Maximum luminance peaking control as a function of four different aperture centre frequencies controllable

by subaddress byte 06; aperture factor 1; coring off; chroma trap on; pre-filter off; and bandfilter on.

handbook, full pagewidth

MEH311

fY (MHz)

(dB)

03h

13h

23h

33h

03h

13h

23h

33h

50 Hz PAL/SECAM;

pre-filter off

Fig.28 4.1 MHz luminance peaking control as a function of four different aperture factors controllable by

subaddress byte 06; coring off; chroma trap on; pre-filter off and bandfilter on.

handbook, full pagewidth

MEH312

fY (MHz)

(dB)

00h

01h

02h

03h

50 Hz PAL/SECAM;

pre-filter off

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

handbook, full pagewidth

MEH313

fY (MHz)

(dB)

63h

73h

53h

43h

63h

53h

73h

60 Hz NTSC;

pre-filter on

Fig.29 Maximum luminance peaking control as a function of four different aperture centre frequencies

controllable by subaddress byte 06; aperture factor 1; coring off; chroma trap on; pre-filter on; and
bandfilter on.

Fig.30 3.8 MHz luminance peaking control as a function of four different aperture factors controllable by

subaddress byte 06; coring off; chroma trap on; pre-filter on and bandfilter on.

handbook, full pagewidth

MEH314

fY (MHz)

(dB)

43h

41h

40h

43h

42h

41h

40h

60 Hz NTSC;

pre-filter on

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

Fig.31 Maximum luminance peaking control as a function of four different aperture centre frequencies

controllable by subaddress byte 06; aperture factor 1; coring off; chroma trap on; pre-filter off; and
bandfilter on.

handbook, full pagewidth

MEH315

fY (MHz)

(dB)

13h

33h

23h

33h

13h

23h

03h

60 Hz NTSC;

pre-filter off

Fig.32 4.1 MHz luminance peaking control as a function of four different aperture factors controllable by

subaddress byte 06; coring off; chroma trap on; pre-filter off and bandfilter on.

handbook, full pagewidth

MEH316

fY (MHz)

(dB)

00h

01h

02h

03h

00h

01h

02h

03h

60 Hz NTSC;

pre-filter off

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

Fig.33 4.1 MHz luminance peaking control as a

function of four different aperture factors
controllable by subaddress byte 06;
pre-filter off; coring off and bandpass
filter on.

handbook, halfpage

MEH317

fY (MHz)

(dB)

82h

80h

81h

83h

50 Hz S-Video;
chroma trap off

Fig.34 2.6 MHz luminance peaking control as a

function of four different aperture factors
controllable by subaddress byte 06;
pre-filter off; coring off and bandpass
filter on.

handbook, halfpage

MEH318

fY (MHz)

(dB)

A2h

A0h

A1h

A3h

50 Hz S-Video;
chroma trap off

Fig.35 4.1 MHz luminance peaking control as a

function of four different aperture factors
controllable by subaddress byte 06;
pre-filter off; coring off and bandpass
filter on.

handbook, halfpage

MEH320

fY (MHz)

(dB)

82h

80h

81h

83h

60 Hz S-Video;
chroma trap off

Fig.36 2.6 MHz luminance peaking control as a

function of four different aperture factors
controllable by subaddress byte 06;
pre-filter off; coring off and bandpass
filter on.

handbook, halfpage

MEH319

fY (MHz)

(dB)

A0h

A3h

A2h

A1h

60 Hz S-Video;
chroma trap off

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

Fig.37 4.1 MHz luminance peaking control in

50 Hz / S-VHS mode as a function of four
different aperture factors controllable by
subaddress byte 06.

handbook, halfpage

MEH321

fY (MHz)

(dB)

82h

80h

81h

83h

50 Hz Y/C;

all filters off

Fig.38 4.1 MHz luminance peaking control in

60 Hz / S-VHS mode as a function of four
different aperture factors controllable by
subaddress byte 06.

handbook, halfpage

MEH322

fY (MHz)

(dB)

8Ah

89h

88h

8Bh

60 Hz Y/C;

all filters off

Fig.39 Maximum luminance peaking control in

50 Hz / S-VHS mode as a function of four
aperture centre frequencies controllable by
subaddress byte 06.

handbook, halfpage

MEH323

fY (MHz)

(dB)

B3h

83h

93h

A3h

50 Hz Y/C;

bandfilter on

Fig.40 Maximum luminance peaking control in

60 Hz / S-VHS mode as a function of four
aperture centre frequencies controllable by
subaddress byte 06.

handbook, halfpage

MEH324

fY (MHz)

(dB)

B3h

83h

93h

A3h

60 Hz Y/C;

bandfilter on

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

PROGRAMMING EXAMPLE

Coefficients to set operation for application circuits Figures 19, 20 and 21. Values recommended for PAL CVBS input
signal and 4:2:2 CCIR output signal (all numbers of the Table 6 are hex values).

Table 7

Recommended default values (note 1)

Notes

1. Slave address is 8A (hex) at IICSA = LOW or 8E (hex) at IICSA = HIGH.

2. Dependent on applications (Figures 25 to 40).

SUBADDRESS

BIT NAME

FUNCTION

VALUE (HEX)

00
01
02

IDEL(7-0)
HSYB(7-0)
HSYS(7-0)

increment delay
horizontal sync HSY begin
horizontal sync HSY stop

4D
3D
0D

03
04
05

HCLB(7-0)
HCLS(7-0)
HPHI(7-0)

horizontal clamping HCL begin
horizontal clamping HCL stop
horizontal sync after PHI1

F3
C6
FB

BYPS, PREF, BPSS(1-0)
BFBY, CORI, APER(1-0)

luminance bandwidth control:

02 (note 2)

HUEC(7-0)

hue control (0 degree)

CSTD(2-0), CKTQ(4-0)

miscellaneous controls #1

OSCE, LFIS(1-0), CKTS(4-0)

miscellaneous controls #2

PLSE(7-0)

PAL switch sensitivity

SESE(7-0)

SECAM switch sensitivity

FSAU, GPSI(2-1), CGFX,
AMPF(3-0)

miscellaneous controls #3

COLO, CHSB, GPSW0,
SUVI, SXCR, FSDL(2-0)

miscellaneous controls #4

CCIR, COEF, OEHS, OEVS
UVSS, CHRS, CDMO, CDPO

miscellaneous controls #5

AUFD, FSEL, HPLL, SCEN,
VTRC, MUIV, FSIV, WIND

miscellaneous controls #6

ASTD, OFTS, IPBP, CDVI,
YDEL(3-0)

miscellaneous controls #7

CHCV(7-0)

nominal chrominance gain

OEDY, OEDC, VNOI(1-0),
BFON, BOFL(2-0)

miscellaneous controls #8

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

PACKAGE OUTLINE

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

EIAJ

Note

1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.

SOT188-2

detail X

(A )

Z D

Z E

pin 1 index

112E10

MO-047AC

10 mm

scale

92-11-17
95-03-11

PLCC68: plastic leaded chip carrier; 68 leads

SOT188-2

UNIT

min.

max.

max. max.

(1)

4.57
4.19

0.51

3.30

0.53
0.33

0.021
0.013

1.27

0.51

2.16

0.18

0.10

0.18

DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)

(1)

24.33
24.13

25.27
25.02

2.16

0.81
0.66

1.22
1.07

0.180
0.165

0.020

0.13

0.25

0.01

0.05

0.020

0.085

0.007 0.004

0.007

1.44
1.02

0.057
0.040

0.958
0.950

24.33
24.13

0.958
0.950

0.995
0.985

25.27
25.02

0.995
0.985

23.62
22.61

0.930
0.890

23.62
22.61

0.930
0.890

0.085

0.032
0.026

0.048
0.042

inches

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

SOLDERING

Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"IC Package Databook" (order code 9398 652 90011).

Reflow soldering

Reflow soldering techniques are suitable for all PLCC
packages.

The choice of heating method may be influenced by larger
PLCC packages (44 leads, or more). If infrared or vapour
phase heating is used and the large packages are not
absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

"Quality

Reference Handbook" (order code 9397 750 00192).

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45

Wave soldering

Wave soldering techniques can be used for all PLCC
packages if the following conditions are observed:

A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

The longitudinal axis of the package footprint must be
parallel to the solder flow.

The package footprint must incorporate solder thieves at
the downstream corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260

C, and

maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150

C within

6 seconds. Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300

C. When

using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320

April 1993

Philips Semiconductors

Product specification

Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)

SAA7151B

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PURCHASE OF PHILIPS I

C COMPONENTS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I

C components conveys a license under the Philips' I

C patent to use the

components in the I

C system provided the system conforms to the I

C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

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