1996 Oct 02
2
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
FEATURES
Monolithic CMOS 3.3 V device with 5 V input stages
Digital PAL/NTSC/SECAM encoder
System pixel frequency 13.5 MHz
Accepts MPEG decoded data on 8-bit wide input port.
Input data format Cb, Y, Cr etc. "
(CCIR 656)" or
Y and Cb, Cr on 16 lines
Three DACs for CVBS, Y and C operating at 27 MHz
with 10 bit resolution
Three DACs for RGB operating at 27 MHz with 9 bit
resolution, RGB sync on CVBS and Y
Analog multiplexing between internal RGB and external
RGB on-chip
CVBS, Y, C and RGB output simultaneously
Closed captioning and teletext encoding including
sequencer and filter
Line 23 wide screen signalling encoding
On-chip Cr, Y, Cb to RGB dematrix, including gain
adjustment for Y and Cr, Cb, optionally to be by-passed
for Cr, Y, Cb output on RGB DACs
Fast I
2
C-bus control port (400 kHz)
Encoder can be master or slave
Programmable horizontal and vertical input
synchronization phase
Programmable horizontal sync output phase
Internal Colour Bar Generator (CBG)
Overlay with Look-Up Tables (LUTs) 8
3 bytes
Macrovision Pay-per-View copy protection system as
option, also used for RGB output.
This applies to SAA7183A only. The device is protected
by USA patent numbers 4631603, 4577216 and
4819098 and other intellectual property rights. Use of
the Macrovision anti-copy process in the device is
licensed for non-commercial home use only.
Reverse engineering or disassembly is prohibited.
Please contact your nearest Philips Semiconductor
sales office for more information
Controlled rise/fall times of output syncs and blanking
Down-mode of DACs
PQFP80 or PLCC84 package.
GENERAL DESCRIPTION
The SAA7182A; SAA7183A encodes digital YUV video
data to an NTSC, PAL, SECAM CVBS or S-Video signal
and also RGB.
Optionally, the YUV to RGB dematrix can be by-passed
providing the digital-to-analog converted Cb, Y, Cr signals
instead of RGB.
The circuit accepts CCIR compatible YUV data with
720 active pixels per line in 4 : 2 : 2 multiplexed formats,
for example MPEG decoded data. It includes a sync/clock
generator and on-chip Digital-to-Analog Converters
(DACs).
The circuit is compatible to the DIG-TV2 chip family.
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
SAA7182AWP;
SAA7183AWP
PLCC84
plastic leaded chip carrier; 84 leads
SOT189-2
QFP80
plastic quad flat package; 80 leads (lead length 1.95 mm);
body 14
20
2.8 mm
SOT318-2
1996 Oct 02
3
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
V
DDA3
3.3 V analog supply voltage
3.1
3.3
3.5
V
V
DDD3
3.3 V digital supply voltage
3.0
3.3
3.6
V
V
DDD5
5 V digital supply voltage
4.75
5.0
5.25
V
I
DDA
analog supply current
-
-
110
mA
I
DDD3
3.3 V digital supply current
-
-
80
mA
I
DDD5
5 V digital supply current
-
-
10
mA
V
i
input signal voltage levels
TTL compatible
V
o(p-p)
analog output signal voltages Y, C, CVBS and RGB without load
(peak-to-peak value)
-
1.4
-
V
R
L
load resistance
75
-
300
ILE
LF integral linearity error
-
-
2
LSB
DLE
LF differential linearity error
-
-
1
LSB
T
amb
operating ambient temperature
0
-
+70
C
1996 Oct 02
4
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
BLOCK DIAGRAM
Fig.1 Block diagram; PLCC84.
handbook, full pagewidth
I
2
C-BUS
INTERFACE
DATA
MANAGER
SECAM
PROCESSOR
ENCODER
SYNC
CLOCK
OUTPUT
INTERFACE
D
A
RGB
PROCESSOR
D
A
1
84
83
4
50 35
36 20 47
45 44
48
75
63, 64,
68, 70,
72, 74
37
DP0
to
DP7
MP7
to
MP0
KEY
TTX
OVL2
to
OVL0
3, 15, 24,
30, 39, 42,
51, 79, 81
5, 14, 22,
29, 38, 46,
49, 80, 82
2, 23, 40, 41,
43, 66
78
77
59
56
54,
57, 60
73
71
69
52, 67, 76
65
53
62
61
58
55
RESET SDA SCL
RTCI
CDIR
RCV1
RCV2
TTXRQ
CREF
XTALO
XTALI
LLC
TESTB
VDDA4 to VDDA9
SA
CVBS
Y
CHROMA
VSSA1
to
VSSA3
TESTC
SELI
RI
RED
GREEN
BLUE
I
2
C-bus
control
I
2
C-bus
control
I
2
C-bus
control
I
2
C-bus
control
I
2
C-bus
control
I
2
C-bus
control
I
2
C-bus
control
DbDr
8
VSSD1
to
VSSD9
VDDD1
to
VDDD9
VDDA1
to
VDDA3
n.c.
SP
AP
GI
BI
internal
control bus
clock
and timing
8
8
8
8
3
8
8
8
Y
Y
C
CbCr
Y
CbCr
3
21
9
10 to 13
16 to 19
25 to 28
31 to 34
6 to 8
SAA7182A
SAA7183A
MGD668
1996 Oct 02
5
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
Fig.2 Block diagram; QFP80.
handbook, full pagewidth
I
2
C-BUS
INTERFACE
DATA
MANAGER
SECAM
PROCESSOR
ENCODER
SYNC
CLOCK
OUTPUT
INTERFACE
D
A
RGB
PROCESSOR
D
A
73
72
71
75
38 25
26 11 35
33 32
36
63
52, 53,
56, 58,
60, 62
27
KEY
TTX
6, 14, 20,
29, 31, 39,
67, 69, 74
5, 13, 19,
28, 34, 37,
68, 70, 76
30, 40
66
65
48
45
43,
46, 49
61
59
57
41, 55, 64
54
42
51
50
47
44
RESET SDA SCL
RTCI
CDIR
RCV1
RCV2
TTXRQ
CREF
XTALO
XTALI
LLC
TESTB
VDDA4 to VDDA9
SA
CVBS
Y
CHROMA
TESTC
SELI
RI
RED
GREEN
BLUE
I
2
C-bus
control
I
2
C-bus
control
I
2
C-bus
control
I
2
C-bus
control
I
2
C-bus
control
I
2
C-bus
control
I
2
C-bus
control
DbDr
8
VSSD1
to
VSSD9
VDDD1
to
VDDD9
VDDA1
to
VDDA3
n.c.
SP
AP
GI
BI
internal
control bus
clock
and timing
8
8
8
8
3
8
8
8
Y
Y
C
CbCr
Y
CbCr
3
12
80
1 to 4
7 to 10
15 to 18
21 to 24
77 to 79
SAA7182A
SAA7183A
MGD670
DP0
to
DP7
MP7
to
MP0
OVL2
to
OVL0
VSSA1
to
VSSA3
PDF 
ZIP