2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

CONTENTS

FEATURES

GENERAL DESCRIPTION

ORDERING INFORMATION

QUICK REFERENCE DATA

BLOCK DIAGRAM

PINNING

FUNCTIONAL DESCRIPTION

7.1

Decoder part

7.1.1

Principal operational modes of the decoder

7.1.2

Decoding speed and crystal frequency

7.1.3

Lock-to-disc mode

7.1.4

Standby modes

7.2

Crystal oscillator

7.3

Data slicer and clock regenerator

7.4

Demodulator

7.4.1

Frame sync protection

7.4.2

EFM demodulation

7.5

Subcode data processing

7.5.1

Q-channel processing

7.5.2

EIAJ 3 and 4-wire subcode (CD graphics)
interfaces

7.5.3

V4 subcode interface

7.6

FIFO and error corrector

7.6.1

Flags output (CFLG)

7.7

Audio functions

7.7.1

De-emphasis and phase linearity

7.7.2

Digital oversampling filter

7.7.3

Concealment

7.7.4

Mute, full-scale, attenuation and fade

7.7.5

Peak detector

7.8

DAC interface

7.8.1

Internal bitstream Digital-to-Analog
Converter (DAC)

7.8.2

External DAC interface

7.9

EBU interface

7.9.1

Format

7.10

KILL circuit

7.11

Audio features off

7.12

The VIA interface

7.13

Spindle motor control

7.13.1

Motor output modes

7.13.2

Spindle motor operating modes

7.13.3

Loop characteristics

7.13.4

FIFO overflow

7.14

Servo part

7.14.1

Diode signal processing

7.14.2

Signal conditioning

7.14.3

Focus servo system

7.14.4

Radial servo system

7.14.5

Off-track counting

7.14.6

Defect detection

7.14.7

Off-track detection

7.14.8

High-level features

7.14.9

Driver interface

7.14.10

Laser interface

7.14.11

Radial shock detector

7.15

Microcontroller interface

7.15.1

Microcontroller interface (4-wire bus mode)

7.15.2

Microcontroller interface (I

C-bus mode)

7.15.3

Decoder registers and shadow registers

7.15.4

Summary of functions controlled by decoder
registers 0 to F

7.15.5

Summary of functions controlled by shadow
registers

7.15.6

Summary of servo commands

7.15.7

Summary of servo command parameters

LIMITING VALUES

CHARACTERISTICS

OPERATING CHARACTERISTICS
(SUBCODE INTERFACE TIMING)

OPERATING CHARACTERISTICS (I

S-BUS

TIMING)

OPERATING CHARACTERISTICS
(MICROCONTROLLER INTERFACE TIMING)

APPLICATION INFORMATION

PACKAGE OUTLINE

SOLDERING

15.1

Introduction to soldering surface mount
packages

15.2

Reflow soldering

15.3

Wave soldering

15.4

Manual soldering

15.5

Suitability of surface mount IC packages for
wave and reflow soldering methods

DATA SHEET STATUS

DEFINITIONS

DISCLAIMERS

PURCHASE OF PHILIPS I

C COMPONENTS

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

FEATURES

�

Extended operating ambient temperature range of

40 to +85

�

Integrated bitstream DAC with differential outputs,
operating at 96f

with 3rd-order noise shaper; typical

performance of

90 dB signal-to-noise ratio

�

Separate serial input and output interfaces allow data
`loopback' mode for use of onboard DAC with external
Electronic Shock Absorption (ESA) systems

�

Up to 2 times speed mode

�

Lock-to-disc mode

�

Full error correction strategy, t = 2 and e = 4

�

Full CD graphics interface

�

All standard decoder functions implemented digitally on
chip

�

FIFO overflow concealment for rotational shock
resistance

�

Digital audio interface (EBU), audio and data

�

2 and 4 times oversampling integrated digital filter,
including f

mode

�

Audio data peak level detection

�

Kill interface for external DAC deactivation during digital
silence

�

All SAA737x (CD7) digital servo and high-level functions

�

Low focus noise

�

Same playability performance as SAA737x (CD7)

�

Automatic closed-loop gain control available for focus
and radial loops

�

Pulsed sledge support

�

Electronic damping of fast radial actuator during long
jump

�

Microcontroller loading LOW

�

High-level servo control option

�

High-level mechanism monitor

�

Communication may be via TDA1301/SAA7345
compatible bus or I

C-bus

�

On-chip clock multiplier allows the use of 8.4672,
16.9344 or 33.8688 MHz crystals or ceramic
resonators.

GENERAL DESCRIPTION

The SAA7326 (CD10 II) is a single chip combining the
functions of a CD decoder, digital servo and bitstream
DAC. It has an extended operating ambient temperature
range when compared with other CD10 II variants.
The decoder/servo part is based on the SAA737x (CD7)
and is software compatible with this design. Extra
functions are controlled by use of `shadow' registers
(see Section 7.15.3).

Supply of this Compact Disc IC does not convey an
implied license under any patent right to use this IC in any
Compact Disc application.

ORDERING INFORMATION

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

SAA7326H

QFP64

plastic quad flat package; 64 leads (lead length 1.6 mm);
body 14

�

2.7 mm

SOT393-1

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

BLOCK DIAGRAM

handbook, full pagewidth

DECODER

MICRO-

CONTROLLER

INTERFACE

VERSATILE PINS

INTERFACE

SUBCODE

PROCESSOR

KILL

PEAK

DETECT

SERIAL DATA

INTERFACE

TIMING

TEST

ADC

Vref

GENERATOR

FRONT-END

DIGITAL

PLL

MOTOR

CONTROL

AUDIO

PROCESSOR

EBU

INTERFACE

ERROR

CORRECTOR

MICROCONTROLLER

INTERFACE

PRE-

PROCESSING

CONTROL

FUNCTION

CONTROL

PART

EFM

DEMODULATOR

SRAM

RAM

ADDRESSER

OUTPUT
STAGES

FLAGS

VRIN

Iref

SCL

SDA

RAB

SILD

HFIN

HFREF

ISLICE

TEST1

TEST2

TEST3

SELPLL

CRIN

CROUT

CL16

CL11/4

SBSY

SFSY

SUB

RCK

STATUS

VSSA1

VDDA2

VSSD2

VDDD2(C)

VSSA2

VDDA1

VSSD1

VSSD3

VDDD1(P)

V2/V3

KILL

DATA

WCLK

SCLK

SERIAL DATA

(LOOPBACK)

INTERFACE

SDI

WCLI

SCLI

BITSTREAM

DAC

Vpos

Vneg

DOBM

MOTO2

MOTO1

LDON

CFLG

RESET

SAA7326

MGL697

Fig.1 Block diagram.

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

PINNING

SYMBOL

PIN

DESCRIPTION

HFREF

comparator common mode input

HFIN

comparator signal input

ISLICE

current feedback output from data slicer

SSA1

(1)

analog ground 1

DDA1

(1)

analog supply voltage 1

ref

reference current output

RIN

reference voltage for servo ADCs

unipolar current input 1 (central diode signal input)

unipolar current input 2 (central diode signal input)

unipolar current input 3 (central diode signal input)

unipolar current input 4 (central diode signal input)

unipolar current input 1 (satellite diode signal input)

unipolar current input 2 (satellite diode signal input)

SSA2

(1)

analog ground 2

CROUT

crystal/resonator output

CRIN

crystal/resonator input

DDA2

(1)

analog supply voltage 2

DAC left channel differential negative output

DAC left channel differential positive output

neg

DAC negative reference input

pos

DAC positive reference input

DAC right channel differential negative output

DAC right channel differential positive output

SELPLL

selects whether internal clock multiplier PLL is used

TEST1

test control input 1 (this pin should be tied LOW)

CL16

16.9344 MHz system clock output

DATA

serial d4(1) data output (3-state)

WCLK

word clock output (3-state)

SCLK

serial bit clock output (3-state)

C2 error flag output (3-state)

TEST2

test control input 2 (this pin should be tied LOW)

KILL

kill output (programmable; open-drain)

SSD1

(1)

digital ground 1

V2/V3

versatile I/O: versatile input 2 or versatile output 3 (open-drain)

WCLI

word clock input (for data loopback to DAC)

SDI

serial data input (for data loopback to DAC)

SCLI

serial bit clock input (for data loopback to DAC)

RESET

power-on reset input (active LOW)

SDA

microcontroller interface data I/O line (I

C-bus; open-drain output)

SCL

microcontroller interface clock line input (I

C-bus)

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

Note

1. All supply pins must be connected to the same external power supply voltage.

RAB

microcontroller interface R/W and load control line input (4-wire bus mode)

SILD

microcontroller interface R/W and load control line input (4-wire bus mode)

STATUS

servo interrupt request line/decoder status register output (open-drain)

TEST3

test control input 3 (this pin should be tied LOW)

RCK

subcode clock input

SUB

P-to-W subcode bits output (3-state)

SFSY

subcode frame sync output (3-state)

SBSY

subcode block sync output (3-state)

CL11/4

11.2896 or 4.2336 MHz (for microcontroller) clock output

SSD2

(1)

digital ground 2

DOBM

bi-phase mark output (externally buffered; 3-state)

DDD1(P)

(1)

digital supply voltage 1 for periphery

CFLG

correction flag output (open-drain)

radial actuator output

focus actuator output

sledge control output

DDD2(C)

(1)

digital supply voltage 2 for core

SSD3

(1)

digital ground 3

MOTO1

motor output 1; versatile (3-state)

MOTO2

motor output 2; versatile (3-state)

versatile output 4

versatile output 5

versatile input 1

LDON

laser drive on output (open-drain)

SYMBOL

PIN

DESCRIPTION

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

handbook, full pagewidth

SAA7326H

MGL712

SBSY

SFSY

SUB

RCK

TEST3

STATUS

SILD

RAB

SCL

SDA

SCLI

SDI

WCLI

V2/V3

VSSD1

HFREF

HFIN

ISLICE

VSSA1

VDDA1

Iref

VRIN

VSSA2

CROUT

CRIN

LDON

MOTO2

MOTO1

SSD3

DDD2(C)

CFLG

DDD1(P)

DOBM

SSD2

CL11/4

DDA2

neg

pos

SELPLL

TEST1

CL16

DATA

WCLK

SCLK

TEST2

KILL

RESET

Fig.2 Pin configuration.

FUNCTIONAL DESCRIPTION

7.1

Decoder part

7.1.1

RINCIPAL OPERATIONAL MODES OF THE DECODER

The decoding part supports a full audio specification and
can operate at two different disc speeds, from
single-speed (n = 1) to 2 times speed (n = 2).
The factor `n' is called the overspeed factor. A simplified
data flow through the decoder part is illustrated in Fig.7.

7.1.2

ECODING SPEED AND CRYSTAL FREQUENCY

The SAA7326 is a two speed decoding device, with an
internal Phase-Locked Loop (PLL) clock multiplier.
Depending on the crystal frequency used and the internal
clock settings (selectable via decoder register B), the
playback speeds shown in Table 1 are possible, where `n'
is the overspeed factor (1 or 2).

An internal clock multiplier is present, controlled by
SELPLL, and should only be used if a 8.4672 or
16.9344 MHz crystal, ceramic resonator or external clock
is present.

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

7.1.3

OCK

DISC MODE

For electronic shock absorption applications, the SAA7326
can be put into lock-to-disc mode. This allows Constant
Angular Velocity (CAV) disc playback with varying input
data rates from the inside-to-outside of the disc.

In the lock-to-disc mode, the FIFO is blocked and the
decoder will adjust its output data rate to the disc speed.
Hence, the frequency of the I

S-bus (WCLK and SCLK)

clocks are dependent on the disc speed. In the lock-to-disc
mode there is a limit on the maximum variation in disc
speed that the SAA7326 will follow. Disc speeds must
always be within 25% to 100% range of their nominal
value. The lock-to-disc mode is enabled/disabled by
decoder register E.

7.1.4

TANDBY MODES

The SAA7326 may be placed in two standby modes
selected by decoder register B (it should be noted that the
device core is still active):

�

Standby 1: CD-STOP mode; most I/O functions are
switched off

�

Standby 2: CD-PAUSE mode; audio output features are
switched off, but the motor loop, the motor output and
the subcode interfaces remain active; this is also called
a `Hot Pause'.

In the standby modes the various pins will have the
following values:

�

MOTO1 and MOTO2: put in high-impedance, PWM
mode (standby 1 and reset: operating in standby 2); put
in high-impedance, PDM mode (standby 1 and reset:
operating in standby 2)

�

SCL and SDA: no interaction; normal operation
continues

�

SCLK, WCLK, DATA, EF and DOBM: 3-state in both
standby modes; normal operation continues after reset

�

CRIN, CROUT, CL16 and CL11/4: no interaction;
normal operation continues

�

V1, V2/V3, V4, V5 and CFLG: no interaction; normal
operation continues.

Table 1

Playback speeds

Notes

1. The CL11 output is always a 5.6448 MHz clock if a 16.9344 MHz external clock is used and SELPLL = 0. CL11 is

available on the CL11/4 output, enabled by programming shadow register 3 (see Section 7.15.3).

2. Data capture performance is not optimized for this option.

REGISTER B

SELPLL

CRYSTAL FREQUENCY (MHz)

CL11 FREQUENCY (MHz)

(1)

33.8688

16.9344

8.4672

00XX

n = 1

11.2896

00XX

n = 1

11.2896

01XX

n = 1

5.6448

01XX

n = 1

11.2896

10XX

n = 2

11.2896

10XX

n = 2

11.2896

11XX

n = 2

(2)

5.6448

11XX

n = 2

11.2896

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

7.2

Crystal oscillator

The crystal oscillator is a conventional 2-pin design
operating between 8 and 35 MHz. This oscillator is
capable of operating with ceramic resonators and with
both fundamental and third overtone crystals. External
components should be used to suppress the fundamental
output of the third overtone crystals as shown in
Figs 3 and 4. Typical oscillation frequencies required are
8.4672, 16.9344 or 33.8688 MHz depending on the
internal clock settings used and whether or not the clock
multiplier is enabled.

7.3

Data slicer and clock regenerator

The SAA7326 has an integrated slice level comparator
which can be clocked by the crystal frequency clock, or
4 times the crystal frequency clock (if SELPLL is set HIGH
while using a 16.9344 MHz crystal and register 4 is set to
0XXX), or 8 times the crystal frequency clock (if SELPLL is
set HIGH while using an 8.4672 MHz crystal, and
register 4 is set to 0XXX). The slice level is controlled by
an internal current source applied to an external capacitor
under the control of the Digital Phase-Locked
Loop (DPLL).

Regeneration of the bit clock is achieved with an internal
fully digital PLL. No external components are required and
the bit clock is not output. The PLL has two registers
(8 and 9) for selecting bandwidth and equalization. The
PLL response is shown in Fig.5.

For certain applications an off-track input is necessary.
This is internally connected from the servo part (its polarity
can be changed by the foc_parm1 parameter), but may be
input via the V1 pin if selected by register C. If this flag is
HIGH, the SAA7326 will assume that its servo part is
following on the wrong track, and will flag all incoming
HF data as incorrect.

handbook, halfpage

OSCILLATOR

8.4672 MHz

CRIN

CROUT

SAA7326

33 pF

MGL709

Fig.3 8.4672 MHz fundamental configuration.

handbook, halfpage

OSCILLATOR

33.8688 MHz

CRIN

CROUT

SAA7326

3.3

�

1 nF

10 pF

MGL710

Fig.4 33.8688 MHz overtone configuration.

MGS178

handbook, halfpage

3. PLL, LPF

2. PLL bandwidth

1. PLL integrator

PLL

loop

response

Fig.5 Digital PLL loop response.

1, 2 and 3 are programmable via decoder register 8.

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

47 pF

HFREF

HFIN

ISLICE

22 k

2.2 k

100 nF

1 nF

HF input

crystal

clock

DPLL

VSSA

VSS

MGS179

VDD

100

�

100

�

Fig.6 Data slicer showing typical application components (for n = 1).

7.4

Demodulator

7.4.1

RAME SYNC PROTECTION

A double timing system is used to protect the demodulator
from erroneous sync patterns in the serial data.
The master counter is only reset if:

�

A sync coincidence is detected; sync pattern occurs
588

�

1 EFM clocks after the previous sync pattern

�

A new sync pattern is detected within

�

6 EFM clocks of

its expected position.

The sync coincidence signal is also used to generate the
PLL lock signal, which is active HIGH after 1 sync
coincidence found, and reset LOW if during 61
consecutive frames no sync coincidence is found.

The PLL lock signal can be accessed via the SDA or
STATUS pins selected by decoder registers 2 and 7.

Also incorporated in the demodulator is a Run
Length 2 (RL2) correction circuit. Every symbol detected
as RL2 will be pushed back to RL3. To do this, the phase
error of both edges of the RL2 symbol are compared and
the correction is executed at the side with the highest error
probability.

7.4.2

EFM

DEMODULATION

The 14-bit EFM data and subcode words are decoded into
8-bit symbols.

2000

Jun

Philips Semiconductors

Product specification

Digital ser

processor and Compact Disc

decoder with integ

r
ated D

C (CD10 II)

SAA7326

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SUBCODE

PROCESSOR

DIGITAL PLL

AND

DEMODULATOR

FIFO

ERROR

CORRECTOR

FADE/MUTE/

INTERPOLATE

DIGITAL

FILTER

PHASE

COMPENSATION

DE-EMPHASIS

FILTER

KILL

S/EIAJ BUS

INTERFACE

S/EIAJ

LOOPBACK

INTERFACE

WCLI
SCLI
SDI

LN
LP
RN
RP

SCLK
WCLK
DATA
EF

decoder

reg 3

Vneg

decoder reg C

decoder reg 3

reg F

decoder reg A

1: decoder reg 3

101X

0: decoder reg 3

101X

(CD-ROM modes)

1: shadow reg 7

XX1X

0: shadow reg 7

XX0X

1: shadow reg 7

XX1X

0: shadow reg 7

XX0X

0: reg D

XX01

1: decoder reg A

XX0X

0: decoder reg A

XX1X

V4 SUBCODE

INTERFACE

MICROCONTROLLER

INTERFACE

CD GRAPHICS

INTERFACE

EBU

INTERFACE

SBSY
SFSY
SUB

RCK

DOBM

SDA

output from

data slicer

1: decoder reg 3 = XX10
(1fs mode)

0: decoder reg 3

XX10

1: no pre-emphasis detected
OR reg D

01XX

(de-emphasis signal at V5)
0: pre-emphasis detected
AND reg D

01XX

KILL
V3

MGS180

ONBOARD

DAC

1: shadow reg 7

XXX1

0: shadow reg 7

XXX0

Fig.7 Simplified data flow of decoder functions.

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

7.5

Subcode data processing

7.5.1

Q-

CHANNEL PROCESSING

The 96-bit Q-channel word is accumulated in an internal
buffer. The last 16 bits are used internally to perform a
Cyclic Redundancy Check (CRC). If the data is good, the
SUBQREADY-I signal will go LOW. SUBQREADY-I can
be read via the SDA or STATUS pins, selected via decoder
register 2. Good Q-channel data may be read from SDA.

7.5.2

EIAJ 3

AND

WIRE SUBCODE

(CD

GRAPHICS

)

INTERFACES

Data from all the subcode channels (P-to-W) may be read
via the subcode interface, which conforms to EIAJ
CP-2401. The interface is enabled and configured as
either a 3-wire or 4-wire interface via decoder register F.

The subcode interface output formats are illustrated in
Fig.8, where the RCK signal is supplied by another device
such as a CD graphics decoder.

7.5.3

SUBCODE INTERFACE

Data of subcode channels, Q-to-W, may be read via pin V4
if selected via decoder register D. The format is similar to
RS232 and is illustrated in Fig.9. The subcode sync word
is formed by a pause of (200/n)

�

s minimum. Each

subcode byte starts with a logic 1 followed by 7 bits
(Q-to-W). The gap between bytes is variable between
(11.3/n)

�

s and (90/n)

�

The subcode data is also available in the EBU output
(DOBM) in a similar format.

handbook, full pagewidth

SBSY

SFSY

RCK

SUB

SFSY

RCK

SUB

SFSY

RCK

SUB

EIAJ 4-wire subcode interface

EIAJ 3-wire subcode interface

SF0

SF1

SF2

SF3

SF97

SF0

SF1

P-W

MBG410

SF0

SF1

SF2

SF3

SF97

SF0

SF1

Fig.8 EIAJ subcode (CD graphics) interface format.

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

W96

200/n

�

min

11.3/n

�

11.3/n

�

s min

90/n

�

s max

MBG401

Fig.9 Subcode format and timing on pin V4.

n = disc speed.

7.6

FIFO and error corrector

The SAA7326 has a

�

8 frame FIFO. The error corrector is

a t = 2, e = 4 type, with error corrections on both
C1 (32 symbol) and C2 (28 symbol) frames. Four symbols
are used from each frame as parity symbols. This error
corrector can correct up to two errors on the C1 level and
up to four errors on the C2 level.

The error corrector also contains a flag processor. Flags
are assigned to symbols when the error corrector cannot
ascertain if the symbols are definitely good. C1 generates
output flags which are read after (de-interleaving) by C2,
to help in the generation of C2 output flags.

The C2 output flags are used by the interpolator for
concealment of uncorrectable errors. They are also output
via the EBU signal (DOBM). The EF output will flag bytes
in error in both audio and CD-ROM modes.

7.6.1

LAGS OUTPUT

(CFLG)

The flags output pin CFLG shows the status of the error
corrector and interpolator and is updated every frame
(7.35

�

n kHz). In the SAA7326 chip a 1-bit flag is present

on the CFLG pin as illustrated in Fig.10. This signal shows
the status of the error corrector and interpolator.

The first flag bit, F1, is the absolute time sync signal, the
FIFO-passed subcode sync and relates the position of the
subcode sync to the audio data (DAC output). This flag
may also be used in a super FIFO or in the synchronization
of different players. The output flags can be made
available at bit 4 of the EBU data format (LSB of the 24-bit
data word), if selected by decoder register A.

handbook, full pagewidth

11.3/n

�

33.9/n

�

33.9/n

�

MBG425

Fig.10 Flag output timing diagram.

n = disc speed.

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

Table 2

Output flags

DESCRIPTION

no absolute time sync

absolute time sync

C1 frame contained no errors

C1 frame contained 1 error

C1 frame contained 2 errors

C1 frame uncorrectable

C2 frame contained no errors

C2 frame contained 1 error

C2 frame contained 2 errors

C2 frame contained 3 errors

C2 frame contained 4 errors

C2 frame uncorrectable

no interpolations

at least one 1-sample interpolation

at least one hold and no interpolations

at least one hold and one 1-sample interpolation

7.7

Audio functions

7.7.1

EMPHASIS AND PHASE LINEARITY

When pre-emphasis is detected in the Q-channel
subcode, the digital filter automatically includes a
de-emphasis filter section. When de-emphasis is not
required, a phase compensation filter section controls the
phase of the digital oversampling filter to

�

within the

band 0 to 16 kHz. With de-emphasis the filter is not phase
linear.

If the de-emphasis signal is set to be available at V5,
selected via decoder register D, then the de-emphasis
filter is bypassed.

7.7.2

IGITAL OVERSAMPLING FILTER

For optimizing performance with an external DAC, the
SAA7326 contains a 2 to 4 times oversampling IIR filter.
The filter specification of the 4 times oversampling filter is
given in Table 3.

These attenuations do not include the sample-and-hold at
the external DAC output or the DAC post filter. When using
the oversampling filter, the output level is scaled

0.5 dB

down to avoid overflow on full-scale sine wave inputs
(0 to 20 kHz).

Table 3

Filter specification

7.7.3

ONCEALMENT

A 1-sample linear interpolator becomes active if a single
sample is flagged as erroneous but cannot be corrected.
The erroneous sample is replaced by a level midway
between the preceding and following samples. Left and
right channels have independent interpolators. If more
than one consecutive non-correctable sample is found, the
last good sample is held. A 1-sample linear interpolation is
then performed before the next good sample (see Fig.11).

In CD-ROM modes (i.e. the external DAC interface is
selected to be in a CD-ROM format) concealment is not
executed.

PASS BAND

STOP BAND

ATTENUATION

0 to 9 kHz

0.001 dB

19 to 20 kHz

0.03 dB

24 kHz

25 dB

24 to 27 kHz

38 dB

27 to 35 kHz

40 dB

35 to 64 kHz

50 dB

64 to 68 kHz

31 dB

68 kHz

35 dB

69 to 88 kHz

40 dB

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

7.7.4

UTE

FULL

SCALE

ATTENUATION AND FADE

A digital level controller is present on the SAA7326 which
performs the functions of soft mute, full-scale, attenuation
and fade; these are selected via decoder register 0:

�

Mute: signal reduced to 0 in a maximum of 128 steps;
(3/n) ms

�

Attenuate: signal scaled by

12 dB

�

Full-scale: ramp signal back to 0 dB level. From mute
takes (3/n) ms

�

Fade: activates a 128 stage counter which allows the
signal to be scaled up/down by 0.07 dB steps

� 128 = full-scale

� 120 =

0.5 dB (i.e. full-scale if oversampling filter

used)

� 32 =

12 dB

� 0 = mute.

7.7.5

EAK DETECTOR

The peak detector measures the highest audio level
(absolute value) on positive peaks for left and right
channels. The 8 most significant bits are output in the
Q-channel data in place of the CRC bits. Bits 81 to 88
contain the left peak value (bit 88 = MSB) and
bits 89 to 96 contain the right peak value (bit 96 = MSB).
The values are reset after reading Q-channel data via
SDA.

Interpolation

Hold

Interpolation

MGA372

Error

Fig.11 Concealment mechanism.

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

7.8

DAC interface

7.8.1

NTERNAL BITSTREAM

IGITAL

-A

NALOG

ONVERTER

(DAC)

The onboard bitstream DAC operates at a clock frequency
of 96f

and is designed for operation with an audio input at

. Optimum performance is dependent on the application

circuit used and careful consideration should be given to
the recommended application circuits shown in
Figs 38 and 39. The onboard DAC is controlled from
shadow register 7 (see Section 7.15.3 for definition of
shadow registers). This shadow register controls routing of
data into the onboard DAC and also controls the DAC
output pins, which can be held at zero when the onboard
DAC is not required; see Table 4.

Audio data from the decoder part of the SAA7326 can be
routed as described in Sections 7.8.1.1 and 7.8.1.2.

7.8.1.1

Use onboard DAC

Setting shadow register 7 to XX11 will route audio data
from the CD10 decoder into the internal DAC, and enables
the DAC output pins (LN, LP, RN and RP). To enable the
on-board DAC, the DAC interface format (set by register 3)
must be set to 16-bit 1fs mode, either I

S or EIAJ format.

CD-ROM mode can also be used if interpolation is not
required. The serial data output pins for interfacing with an
external DAC (SCLK, WCLK, DATA and EF) are set to
high-impedance.

7.8.1.2

Loopback external data into onboard DAC

The onboard DAC can also be set to accept serial data
inputs from an external source, e.g. an Electronic Shock
Absorption (ESA) IC. This is known as loopback mode and
is enabled by setting shadow register 7 to XX01. This
enables the serial data output pins SCLK, WCLK, DATA
and EF so that data can be routed from the SAA7326 to an
external ESA system (or external DAC).

The serial data from an external ESA IC can then also be
input to the onboard DAC on the SAA7326 by utilising the
serial data input interface (SCLI, SDI and WCLI).

In this mode, a wide range of data formats to the external
ESA IC can be programmed as shown in Table 5.
However, the serial input on the SAA7326 will always
expect the input data from the ESA IC to be 16-bit 1f

and

the same data format, either I

S-bus or EIAJ, as the serial

output format (set by decoder register 3).

Table 4

Shadow register

SHADEN

SHADOW

ADDRESS

REGISTER

DATA

FUNCTION

RESET

0111 (7H)

control of

onboard DAC

XXX0

hold onboard DAC outputs at zero

reset

XXX1

enable onboard DAC outputs

XX0X

use external DAC or route audio data into
onboard DAC (loopback mode)

reset

XX1X

route audio data into onboard DAC
(non-loopback mode)

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

7.8.2

XTERNAL

DAC

INTERFACE

Audio data from the SAA7326 can be sent to an external
DAC, identical to the SAA737x series. This is similar to the
`loopback' mode, but in this case the internal DAC outputs
can be held at zero i.e. shadow register 7 is set to XX00.
The SAA7326 is compatible with a wide range of external
DACs. Eleven formats are supported and are given in
Table 5. Figures 12 and 13 show the Philips I

S-bus and

the EIAJ data formats respectively. When the decoder is
operated in lock-to-disc mode, the SCLK frequency is
dependent on the disc speed factor `d'.

All formats are MSB first and f

is (44.1

�

n) kHz.

The polarity of the WCLK and the data can be inverted;
selectable by decoder register 7. It should be noted
that EF is only a defined output in CD-ROM and
1f

modes.

When using an external DAC (or when using the onboard
DAC in non-loopback mode), the serial data inputs to the
onboard DAC (SCLI, SDI and WCLI) should be left
unconnected.

Table 5

DAC interface formats

Note

1. In this mode the first 16 bits contain data, but if any of the fade, attenuate or de-emphasis filter functions are activated

then the first 18 bits contain data.

REGISTER 3

SAMPLE

FREQUENCY

NUMBER OF

BITS

SCLK (MHz)

FORMAT

INTERPOLATION

1010

2.1168

�

CD-ROM (I

S-bus)

1011

2.1168

�

CD-ROM (EIAJ)

1110

16/18

(1)

2.1168

�

Philips I

S-bus 16/18 bits

(1)

yes

0010

2.1168

�

EIAJ 16 bits

yes

0110

2.1168

�

EIAJ 18 bits

yes

0000

8.4672

�

EIAJ 16 bits

yes

0100

8.4672

�

EIAJ 18 bits

yes

1100

8.4672

�

Philips I

S-bus 18 bits

yes

0011

4.2336

�

EIAJ 16 bits

yes

0111

4.2336

�

EIAJ 18 bits

yes

1111

4.2336

�

Philips I

S-bus 18 bits

yes

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

7.9

EBU interface

The bi-phase mark digital output signal at pin DOBM is in
accordance with the format defined by the IEC958
specification. Three different modes can be selected via
decoder register A:

�

DOBM pin held LOW

�

Data taken before concealment, mute and fade (must
always be used for CD-ROM modes)

�

Data taken after concealment, mute and fade.

7.9.1

ORMAT

The digital audio output consists of 32-bit words
(subframes) transmitted in bi-phase mark code (two
transitions for a logic 1 and one transition for a logic 0).
Words are transmitted in blocks of 384. The formats are
given in Table 6.

Table 6

Format

Table 7

Description of Table 6

Table 8

Bit assignment

FUNCTION

BITS

DESCRIPTION

Sync

0 to 3

Auxiliary

4 to 7

not used; normally zero

Error flags

CFLG error and interpolation flags when selected by register A

Audio sample

8 to 27

first 4 bits not used (always zero); twos complement; LSB = bit 12, MSB = bit 27

Validity flag

valid = logic 0

User data

used for subcode data (Q-to-W)

Channel status

control bits and category code

Parity bit

even parity for bits 4 to 30

FUNCTION

DESCRIPTION

Sync

The sync word is formed by violation of the bi-phase rule and therefore does not contain any data.
Its length is equivalent to 4 data bits. The 3 different sync patterns indicate the following situations:
sync B: start of a block (384 words), word contains left sample; sync M: word contains left sample
(no block start) and sync W: word contains right sample.

Audio sample

Left and right samples are transmitted alternately.

Validity flag

Audio samples are flagged (bit 28 = 1) if an error has been detected but was uncorrectable. This
flag remains the same even if data is taken after concealment.

User data

Subcode bits Q-to-W from the subcode section are transmitted via the user data bit. This data is
asynchronous with the block rate.

Channel status

The channel status bit is the same for left and right words. Therefore a block of 384 words contains
192 channel status bits. The category code is always CD. The bit assignment is given in Table 8.

FUNCTION

BITS

DESCRIPTION

Control

0 to 3

copy of CRC checked Q-channel control bits 0 to 3; bit 2 is logic 1 when
copy permitted; bit 3 is logic 1 when recording has pre-emphasis

Reserved mode

4 to 7

always zero

Category code

8 to 15

CD; bit 8 = logic 1; all other bits = logic 0

Clock accuracy

28 to 29

set by register A; 10 = level I; 00 = level II; 01 = level III

Remaining

6 to 27 and 30 to 191 always zero

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

7.10

KILL circuit

The KILL circuit detects digital silence by testing for an
all-zero or all-ones data word in the left or right channel
prior to the digital filter. The output is switched to active
LOW when silence has been detected for at least 270 ms,
or if mute is active, or in CD-ROM modes. Two modes are
available which can be selected by decoder register C:

�

Pin KILL: KILL active LOW indicates silence detected on
both left and right channels

�

Pin KILL: KILL active LOW indicates silence detected on
left channel. V3 active LOW indicates silence detected
on right channel.

It should be noted that when mute is active or in CD-ROM
modes the output(s) are switched LOW.

7.11

Audio features off

The audio features can be turned off (selected by decoder
register E) which affects the following functions;

�

Digital filter, fade, peak detector and KILL circuit (but
outputs KILL and V3 still active) are disabled

�

V5 (if selected to be the de-emphasis flag output) and
the EBU outputs become undefined.

It should be noted that the EBU output should be set LOW
prior to switching the audio features off and after switching
audio features back on a full-scale command should be
given.

7.12

The VIA interface

The SAA7326 has four pins that can be reconfigured for
different applications. One of these pins, V2/V3, can be
programmed as an input (V2) or as an output (V3). Control
of the V2/V3 pin is via shadow register 3; see Table 9.

Selection of the V2/V3 pin does not affect the function
programmed by decoder register C i.e. the V2/V3 pin can
be changed from V2 to V3 function either before or after
setting the desired function via decoder register 1100.
Selection of, for instance, a V3 function while the V2/V3
pin is set to V2 will not affect the V2 functionality.

The functions of these versatile pins is identical to the
SAA737x series. The functions of these versatile pins is
programmed by decoder registers C and D, as shown in
Table 10.

Table 9

V2/V3 configuration

Table 10 Pin applications

SHADEN

ADDRESS

REGISTER

DATA

FUNCTION

RESET

0011 (3H)

control of V2/V3 pin

0XXX

V2/V3 pin configured as V2 input

reset

1XXX

V2/V3 pin configured as V3 output (open-drain)

PIN NAME

PIN

NUMBER

TYPE

REGISTER

ADDRESS

REGISTER

DATA

FUNCTION

input

1100

XXX1

external off-track signal input

XXX0

internal off-track signal used input may be read via
decoder status bit; selected via register 2

input

input may be read via decoder status bit; selected
via register 2

output

1100

XX0X

KILL output for right channel

X01X

output = 0

X11X

output = 1

output

1101

0000

4-line motor drive (using V4 and V5)

XX01

Q-to-W subcode output

XX10

output = 0

XX11

output = 1

output

1101

01XX

de-emphasis output (active HIGH)

10XX

output = 0

11XX

output = 1

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

7.13

Spindle motor control

7.13.1

OTOR OUTPUT MODES

The spindle motor speed is controlled by a fully integrated
digital servo. Address information from the internal

�

frame FIFO and disc speed information are used to
calculate the motor control output signals. Several output
modes, selected by decoder register 6, are supported:

�

Pulse density, 2-line (true complement output),
(1

�

n) MHz sample frequency

�

PWM output, 2-line, (22.05

�

n) kHz modulation

frequency

�

PWM output, 4-line, (22.05

�

n) kHz modulation

frequency

�

CDV motor mode.

7.13.1.1

Pulse density output mode

In the pulse density mode the motor output pin (MOTO1)
is the pulse density modulated motor output signal. A 50%
duty factor corresponds with the motor not actuated,
higher duty factors mean acceleration, lower mean
braking. In this mode, the MOTO2 signal is the inverse of
the MOTO1 signal. Both signals change state only on the
edges of a (1

�

n) MHz internal clock signal. Possible

application diagrams are illustrated in Fig.14.

7.13.1.2

PWM output mode (2-line)

In the PWM mode the motor acceleration signal is put in
pulse-width modulation form on the MOTO1 output.
The motor braking signal is pulse-width modulated on the
MOTO2 output. The timing is illustrated in Fig.15. A typical
application diagram is illustrated in Fig.16.

MGA363 - 1

MOTO2

VSS

MOTO1

22 k

10 nF

+
�

22 k

10 nF

+
�

VSS

MOTO1

22 k

10 nF

+
�

22 k

VSS

VDD

VSS

22 k

Fig.14 Motor pulse density application diagrams.

rep

t = 45

�

t 240 ns

dead

Accelerate

Brake

MOTO1

MOTO2

MGA366

Fig.15 2-line PWM mode timing.

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

MGA364 - 2

VSS

MOTO1

MOTO2

100 nF

Fig.18 Motor 4-line PWM mode application diagram.

7.13.1.4

CDV/CAV output mode

In the CDV motor mode, the FIFO position will be put in
pulse-width modulated form on the MOTO1 pin [carrier
frequency (300

�

d) Hz], where `d' is the disc speed factor.

The PLL frequency signal will be put in pulse-density
modulated form (carrier frequency 4.23

�

n MHz) on the

MOTO2 pin. The integrated motor servo is disabled in this
mode.

The PWM signal on MOTO1 corresponds to a total
memory space of 20 frames, therefore the nominal FIFO
position (half full) will result in a PWM output of 60%.

In the lock to-disc (CAV) mode the CDV motor mode is the
only mode that can be used to control the motor.

7.13.2

PINDLE MOTOR OPERATING MODES

The operating modes of the motor servo is controlled by
decoder register 1 (see Table 11).

In the SAA7326 decoder there is an anti-windup mode for
the motor servo, selected via decoder register 1. When the
anti-windup mode is activated the motor servo integrator
will hold if the motor output saturates.

7.13.2.1

Power limit

In start mode 1, start mode 2, stop mode 1 and stop
mode 2, a fixed positive or negative voltage is applied to
the motor. This voltage can be programmed as a
percentage of the maximum possible voltage, via
register 6, to limit current drain during start and stop.

The following power limits are possible; 100% (no power
limit), 75%, 50% or 37% of maximum.

7.13.3

OOP CHARACTERISTICS

The gain and crossover frequencies of the motor control
loop can be programmed via decoder registers 4 and 5.
The following parameter values are possible:

�

Gains: 3.2, 4.0, 6.4, 8.0, 12.8, 16, 25.6 and 32

�

Crossover frequency f

: 0.5

�

n Hz, 0.7

�

n Hz,

1.4

�

n Hz and 2.8

�

n Hz

�

Crossover frequency f

: 0.85

�

n Hz, 1.71

�

n Hz and

3.42

�

n Hz.

It should be noted that the crossover frequencies f

and f

are scaled with the overspeed factor `n' whereas the gains
are not.

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

7.13.4

FIFO

OVERFLOW

If FIFO overflow occurs during Play mode (e.g.: as a result of motor rotational shock), the FIFO will be automatically reset
to 50% and the audio interpolator tries to conceal as much as possible to minimize the effect of data loss.

Table 11 Operating modes

MODE

DESCRIPTION

Start mode 1

The disc is accelerated by applying a positive voltage to the spindle motor. No decisions are
involved and the PLL is reset. No disc speed information is available for the microcontroller.

Start mode 2

The disc is accelerated as in start mode 1, however the PLL will monitor the disc speed. When the
disc reaches 75% of its nominal speed, the controller will switch to jump mode. The motor status
signals selectable via register 2 are valid.

Jump mode

Motor servo enabled but FIFO kept reset at 50%, integrator is held. The audio is muted but it is
possible to read the subcode. It should be noted that in the CD-ROM modes the data, on EBU and
the I

S-bus is not muted.

Jump mode 1

Similar to jump mode but motor integrator is kept at zero. Used for long jumps where there is a large
change in disc speed.

Play mode

FIFO released after resetting to 50%. Audio mute released.

Stop mode 1

Disc is braked by applying a negative voltage to the motor. No decisions are involved.

Stop mode 2

The disc is braked as in stop mode 1 but the PLL will monitor the disc speed. As soon as the disc
reaches 12% (or 6%, depending on the programmed brake percentage, via register E) of its
nominal speed, the MOTSTOP status signal will go HIGH and switch the motor servo to Off mode.

Off mode

Motor not steered.

MGA362 - 2

Fig.19 Motor servo mode diagram.

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

7.14

Servo part

7.14.1

IODE SIGNAL PROCESSING

The photo detector in conventional two-stage three-beam
Compact Disc systems normally contains six discrete
diodes. Four of these diodes (three for single Foucault
systems) carry the Central Aperture signal (CA) while the
other two diodes (satellite diodes) carry the radial tracking
information. The CA signal is processed into an HF signal
(for the decoder function) and LF signal (information for
the focus servo loop) before it is supplied to the SAA7326.

The analog signals from the central and satellite diodes
are converted into a digital representation using
Analog-to-Digital Converters (ADCs).

The ADCs are designed to convert unipolar currents into a
digital code. The dynamic range of the input currents is
adjustable within a given range, which is dependent on the
value of the external reference current (I

ref

) resistor and

the values programmed in shadow registers A and C.
The magnitude of the signal currents for the central
aperture diodes D1 to D4 and the radial diodes R1 and R2
are programmed separately to sixteen separate current
ranges.

The maximum input currents with an external 30 k

reference current resistor are given in Table 12.

Table 12 Shadow register settings to control diode input current ranges

SHADEN

BIT

SHADOW

REGISTER

ADDRESS

DATA

FUNCTION

INITIAL

A
signal
magnitude
control for
diodes D1 to D4

1010

0000

(0.042).I

ref

= 1.006

�

A (nominal)

0001

(0.083).I

ref

= 2.013

�

A (nominal)

0010

(0.125).I

ref

= 3.019

�

A (nominal)

0011

(0.167).I

ref

= 4.025

�

A (nominal)

0100

(0.208).I

ref

= 5.031

�

A (nominal)

0101

(0.25).I

ref

= 6.034

�

A (nominal)

0110

(0.292).I

ref

= 7.044

�

A (nominal)

0111

(0.333).I

ref

= 8.05

�

A (nominal

1000

(0.375).I

ref

= 9.056

�

A (nominal)

1001

(0.417).I

ref

= 10.063

�

A (nominal)

1010

(0.458).I

ref

= 11.069

�

A (nominal)

1011

(0.5).I

ref

= 12.075

�

A (nominal)

1100

(0.542).I

ref

= 13.081

�

A (nominal)

1101

(0.583).I

ref

= 14.088

�

A (nominal)

1110

(0.625).I

ref

= 15.094

�

A (nominal)

1111

(0.667).I

ref

= 16.1

�

A (nominal)

reset

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

C
signal
magnitude
control for
diodes
R1 and R2

1100

0000

(0.042).I

ref

= 1.006

�

A (nominal)

0001

(0.083).I

ref

= 2.013

�

A (nominal)

0010

(0.125).I

ref

= 3.019

�

A (nominal)

0011

(0.167).I

ref

= 4.025

�

A (nominal)

0100

(0.208).I

ref

= 5.031

�

A (nominal)

0101

(0.25).I

ref

= 6.034

�

A (nominal)

0110

(0.292).I

ref

= 7.044

�

A (nominal)

0111

(0.333).I

ref

= 8.05

�

A (nominal)

1000

(0.375).I

ref

= 9.056

�

A (nominal)

1001

(0.417).I

ref

= 10.063

�

A (nominal)

1010

(0.458).I

ref

= 11.069

�

A (nominal)

1011

(0.5).I

ref

= 12.075

�

A (nominal)

1100

(0.542).I

ref

= 13.081

�

A (nominal)

1101

(0.583).I

ref

= 14.088

�

A (nominal)

1110

(0.625).I

ref

= 15.094

�

A (nominal)

1111

(0.667).I

ref

= 16.1

�

A (nominal)

reset

SHADEN

BIT

SHADOW

REGISTER

ADDRESS

DATA

FUNCTION

INITIAL

7.14.2

IGNAL CONDITIONING

The digital codes retrieved from the ADCs are applied to
logic circuitry to obtain the various control signals.
The signals from the central aperture diodes are
processed to obtain a normalised focus error signal.

where the detector set-up is assumed as shown in Fig.20.

In the event of single Foucault focusing method, the signal
conditioning can be switched under software control such
that the signal processing is as follows:

The error signal, FE

, is further processed by a

Proportional Integral and Differential (PID) filter section.

A Focus OK (FOK) flag is generated by means of the
central aperture signal and an adjustable reference level.
This signal is used to provide extra protection for the
Track-Loss (TL) generation, the focus start-up procedure
and the dropout detection.

The radial or tracking error signal is generated by the
satellite detector signals R1 and R2. The radial error
signal can be formulated as follows:

= (R1

R2)

�

re_gain + (R1 + R2)

�

re_offset

Where the index `s' indicates the automatic scaling
operation which is performed on the radial error signal.
This scaling is necessary to avoid non-optimum dynamic
range usage in the digital representation and reduces the
radial bandwidth spread. Furthermore, the radial error
signal will be made free from offset during start-up of the
disc.

The four signals from the central aperture detectors,
together with the satellite detector signals generate a
Track Position signal (TPI) which can be formulated as
follows:

TPI = sign [(D1 + D2 + D3 + D4)

(R1 + R2)

�

sum_gain]

Where the weighting factor sum_gain is generated
internally by the SAA7326 during initialization.

�

----------------------

�

----------------------

�

----------------------

�

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

handbook, full pagewidth

SATELLITE

DIODE R1

SATELLITE

DIODE R2

SATELLITE

DIODE R1

SATELLITE

DIODE R2

SATELLITE

DIODE R1

SATELLITE

DIODE R2

single Foucault

astigmatic focus

double Foucault

MBG422

Fig.20 Detector arrangement.

7.14.3

OCUS SERVO SYSTEM

7.14.3.1

Focus start-up

Five initially loaded coefficients influence the start-up
behaviour of the focus controller. The automatically
generated triangular voltage can be influenced by
3 parameters; for height (ramp_height) and DC offset
(ramp_offset) of the triangle and its steepness
(ramp_incr).

For protection against false focus point detections two
parameters are available which are an absolute level on
the CA signal (CA_start) and a level on the FE

signal

(FE_start). When this CA level is reached the FOK signal
becomes true.

If the FOK signal is true and the level on the FE

signal is

reached, the focus PID is enabled to switch-on when the
next zero crossing is detected in the FE

signal.

7.14.3.2

Focus position control loop

The focus control loop contains a digital PID controller
which has 5 parameters that are available to the user.
These coefficients influence the integrating (foc_int),
proportional (foc_lead_length, part of foc_parm3) and
differentiating (foc_pole_lead, part of foc_parm1) action of
the PID and a digital low-pass filter (foc_pole_noise, part
of foc_parm2) following the PID. The fifth coefficient
foc_gain influences the loop gain.

7.14.3.3

Dropout detection

This detector can be influenced by one parameter
(CA_drop). The FOK signal will become false and the
integrator of the PID will hold if the CA signal drops below
this programmable absolute CA level. When the FOK
signal becomes false it is assumed, initially, to be caused
by a black dot.

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

7.14.3.4

Focus loss detection and fast restart

Whenever FOK is false for longer than approximately
3 ms, it is assumed that the focus point is lost. A fast
restart procedure is initiated which is capable of restarting
the focus loop within 200 to 300 ms depending on the
programmed coefficients of the microcontroller.

7.14.3.5

Focus loop gain switching

The gain of the focus control loop (foc_gain) can be
multiplied by a factor of 2 or divided by a factor of 2 during
normal operation. The integrator value of the PID is
corrected accordingly. The differentiating (foc_pole_lead)
action of the PID can be switched at the same time as the
gain switching is performed.

7.14.3.6

Focus automatic gain control loop

The loop gain of the focus control loop can be corrected
automatically to eliminate tolerances in the focus loop.
This gain control injects a signal into the loop which is used
to correct the loop gain. Since this decreases the optimum
performance, the gain control should only be activated for
a short time (for example, when starting a new disc).

7.14.4

ADIAL SERVO SYSTEM

7.14.4.1

Level initialization

During start-up an automatic adjustment procedure is
activated to set the values of the radial error gain (re_gain),
offset (re_offset) and satellite sum gain (sum_gain) for TPI
level generation. The initialization procedure runs in a
radial open loop situation and is

300 ms. This start-up

time period may coincide with the last part of the motor
start-up time period:

�

Automatic gain adjustment: as a result of this
initialization the amplitude of the RE signal is adjusted to
within

�

10% around the nominal RE amplitude

�

Offset adjustment: the additional offset in RE due to the
limited accuracy of the start-up procedure is less than

�

50 nm

�

TPI level generation: the accuracy of the initialization
procedure is such that the duty factor range of TPI
becomes 0.4 < duty factor < 0.6 (default duty
factor = TPI HIGH/TPI period).

7.14.4.2

Sledge control

The microcontroller can move the sledge in both directions
via the steer sledge command.

7.14.4.3

Tracking control

The actuator is controlled using a PID loop filter with user
defined coefficients and gain. For stable operation
between the tracks, the S-curve is extended over 0.75 of
the track. On request from the microcontroller, S-curve
extension over 2.25 tracks is used, automatically changing
to access control when exceeding those 2.25 tracks.

Both modes of S-curve extension make use of a
track-count mechanism. In this mode, track counting
results in an `automatic return-to-zero track', to avoid
major music rhythm disturbances in the audio output for
improved shock resistance. The sledge is continuously
controlled, or provided with step pulses to reduce power
consumption using the filtered value of the radial PID
output. Alternatively, the microcontroller can read the
average voltage on the radial actuator and provide the
sledge with step pulses to reduce power consumption.
Filter coefficients of the continuous sledge control can be
preset by the user.

7.14.4.4

Access

The access procedure is divided into two different modes
(see Table 13), depending on the requested jump size.

Table 13 Access modes

Note

1. Microcontroller presettable.

The access procedure makes use of a track counting
mechanism, a velocity signal based on a fixed number of
tracks passed within a fixed time interval, a velocity set
point calculated from the number of tracks to go and a user
programmable parameter indicating the maximum sledge
performance.

If the number of tracks remaining is greater than the
brake_distance then the sledge jump mode should be
activated or, the actuator jump should be performed.
The requested jump size together with the required sledge
breaking distance at maximum access speed defines the
brake_distance value.

ACCESS

TYPE

JUMP SIZE

(1)

ACCESS

SPEED

Actuator
jump

1 - brake_distance

decreasing
velocity

Sledge
jump

brake_distance - 32768 maximum power

to sledge

(1)

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

During the actuator jump mode, velocity control with a
PI controller is used for the actuator. The sledge is then
continuously controlled using the filtered value of the radial
PID output. All filter parameters (for actuator and sledge)
are user programmable.

In the sledge jump mode maximum power (user
programmable) is applied to the sledge in the correct
direction while the actuator becomes idle (the contents of
the actuator integrator leaks to zero just after the sledge
jump mode is initiated). The actuator can be electronically
damped during sledge jump. The gain of the damping loop
is controlled via the hold_mult parameter.

Fast track jumping circuitry can be enabled/disabled via
the xtra_preset parameter.

7.14.4.5

Radial automatic gain control loop

The loop gain of the radial control loop can be corrected
automatically to eliminate tolerances in the radial loop.
This gain control injects a signal into the loop which is used
to correct the loop gain. Since this decreases the optimum
performance, the gain control should only be activated for
a short time (for example, when starting a new disc).

This gain control differs from the level initialization. The
level initialization should be performed first.
The disadvantage of using the level initialization without
the gain control is that only tolerances from the front-end
are reduced.

7.14.5

TRACK COUNTING

The Track Position signal (TPI) is a flag which is used to
indicate whether the radial spot is positioned on the track,
with a margin of

�

of the track-pitch. In combination with

the Radial Polarity flag (RP) the relative spot position over
the tracks can be determined.

These signals are, however, afflicted with some
uncertainties caused by:

�

Disc defects such as scratches and fingerprints

�

The HF information on the disc, which is considered as
noise by the detector signals.

In order to determine the spot position with sufficient
accuracy, extra conditions are necessary to generate a
Track Loss signal (TL) and an off-track counter value.
These extra conditions influence the maximum speed and
this implies that, internally, one of the following three
counting states is selected:

1. Protected state: used in normal play situations. A good

protection against false detection caused by disc
defects is important in this state.

2. Slow counting state: used in low velocity track jump

situations. In this state a fast response is important
rather than the protection against disc defects (if the
phase relationship between TL and RP of

radians

is affected too much, the direction cannot then be
determined accurately).

3. Fast counting state: used in high velocity track jump

situations. Highest obtainable velocity is the most
important feature in this state.

7.14.6

EFECT DETECTION

A defect detection circuit is incorporated into the
SAA7326. If a defect is detected, the radial and focus error
signals may be zeroed, resulting in better playability.
The defect detector can be switched off, applied only to
focus control or applied to both focus and radial controls
under software control (part of foc_parm1).

The defect detector (see Fig.21) has programmable set
points selectable by the parameter defect_parm.

handbook, full pagewidth

DECIMATION

FILTER

FAST

FILTER

DEFECT

GENERATION

PROGRAMMABLE

HOLD-OFF

SLOW

FILTER

defect
output

sat1

sat2

MBG421

Fig.21 Block diagram of defect detector.

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

7.14.7

TRACK DETECTION

During active radial tracking, off-track detection has been
realised by continuously monitoring the off-track counter
value. The off-track flag becomes valid whenever the
off-track counter value is not equal to zero. Depending on
the type of extended S-curve, the off-track counter is reset
after 0.75 extend or at the original track in the 2.25 track
extend mode.

7.14.8

IGH

LEVEL FEATURES

7.14.8.1

Interrupt mechanism and STATUS pin

The STATUS pin is an output which is active LOW, its
output is selected by decoder register 7 to be either the
decoder status bit (active LOW) selected by decoder
register 2 (only available in 4-wire bus mode) or the
interrupt signal generated by the servo part.

Eight signals from the interrupt status register are
selectable from the servo part via the interrupt_mask
parameter. The interrupt is reset by sending the read
high-level status command. The 8 signals are as follows:

�

Focus lost: dropout of longer than 3 ms

�

Subcode ready

�

Subcode absolute seconds changed

�

Subcode discontinuity detected: new subcode time
before previous subcode time, or more than 10 frames
later than previous subcode time

�

Radial error: during radial on-track, no new subcode
frame occurs within time defined by the playwatchtime
parameter; during radial jump, less than 4 tracks have
been crossed during time defined by the jumpwatchtime
parameter

�

Autosequencer state change

�

Autosequencer error

�

Subcode interface blocked: the internal decoder
interface is being used.

It should be noted that if the STATUS pin output is selected
via decoder register 2 and either the microcontroller writes
a different value to decoder register 2 or the decoder
interface is enabled then the STATUS output will change.

7.14.8.2

Decoder interface

The decoder interface allows decoder registers 0 to F to
be programmed and subcode Q-channel data to be read
via servo commands. The interface is enabled/disabled by
the preset latch command (and the xtra_preset
parameter).

7.14.8.3

Automatic error handling

Three Watchdogs are present:

�

Focus: detects focus dropout of longer than 3 ms, sets
focus lost interrupt, switches off radial and sledge
servos, disables drive to disc motor

�

Radial play: started when radial servo is in on-track
mode and a first subcode frame is found; detects when
maximum time between two subcode frames exceeds
time set by playwatchtime parameter; then sets radial
error interrupt, switches radial and sledge servos off,
puts disc motor in jump mode

�

Radial jump: active when radial servo is in long jump or
short jump modes; detects when the off-track counter
value decreases by less than 4 tracks between two
readings (time interval set by jumpwatchtime
parameter); then sets radial jump error, switches radial
and sledge servos off to cancel jump.

The focus Watchdog is always active, the radial
Watchdogs are selectable via the radcontrol parameter.

7.14.8.4

Automatic sequencers and timer interrupts

Two automatic sequencers are implemented (and must be
initialized after power-on):

�

Autostart sequencer: controls the start-up of focus,
radial and motor

�

Autostop sequencer: brakes the disc and shuts down
servos.

When the automatic sequencers are not used it is possible
to generate timer interrupts, defined by the
time_parameter coefficient.

7.14.8.5

High-level status

The read high-level status command can be used to obtain
the interrupt, decoder, autosequencer status registers and
the motor start time. Use of the read high-level status
command clears the interrupt status register, and
re-enables the subcode read via a servo command.

7.14.9

RIVER INTERFACE

The control signals (pins RA, FO and SL) for the
mechanism actuators are pulse density modulated.
The modulating frequency can be set to either 1.0584
(DSD mode) or 2.1168 MHz; controlled via the xtra_preset
parameter. An analog representation of the output signals
can be achieved by connecting a 1st-order low-pass filter
to the outputs.

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

During reset (i.e. RESET pin is held LOW) the RA, FO
and SL pins are high-impedance.

7.14.10 L

ASER INTERFACE

The LDON pin (open-drain output) is used to switch the
laser off and on. When the laser is on, the output is
high-impedance. The action of the LDON pin is controlled
by the xtra_preset parameter; the pin is automatically
driven if the focus control loop is active.

7.14.11 R

ADIAL SHOCK DETECTOR

The shock detector (see Fig.22) can be switched on during
normal track following, and detects within an adjustable
frequency whether disturbances in the radial spot position
relative to the track exceed an adjustable level (controlled
by shock_level).

Every time the radial tracking error exceeds this level the
radial control bandwidth is switched to twice its original
bandwidth and the loop gain is increased by a factor of 4.

The shock detection level is adjustable in 16 steps from
0% to 100% of the traverse radial amplitude which is sent
to an amplitude detection unit via an adjustable band-pass
filter (controlled by sledge_parm1); lower corner frequency
can be set at either 0 or 20 Hz, and upper corner
frequency at 750 or 1850 Hz. The shock detector is
switched off automatically during jump mode.

7.15

Microcontroller interface

Communication on the microcontroller interface can be
set-up in two different modes:

�

4-wire bus mode: protocol compatible with SAA7345
(CD6) and TDA1301 (DSIC2) where:

� SCL = serial clock

� SDA = serial data

� RAB = R/W control and data strobe (active HIGH) for

writing to decoder registers 0 to F, reading status bit
selected via decoder register 2 and reading
Q-channel subcode

� SILD = R/W control and data strobe (active LOW) for

servo commands.

�

C-bus mode: I

C-bus protocol where SAA7326

behaves as slave device, activated by setting
RAB = HIGH and SILD = LOW where;

� I

C-bus slave address (write mode) = 30H

� I

C-bus slave address (read mode) = 31H

� Maximum data transfer rate = 400 kbits/s.

It should be noted that only servo commands can be used
therefore, writing to decoder registers 0 to F, reading
decoder status and reading Q-channel subcode data must
be performed by servo commands.

handbook, full pagewidth

MGC914

SHOCK

OUTPUT

HIGH-PASS FILTER

(0 or 20 Hz)

LOW-PASS FILTER

(750 or 1850 Hz)

AMPLITUDE
DETECTION

Fig.22 Block diagram of radial shock detector.

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

7.15.1

ICROCONTROLLER INTERFACE

(4-

WIRE BUS MODE

)

7.15.1.1

Writing data to registers 0 to F

The sixteen 4-bit programmable configuration registers,
0 to F (see Table 14), can be written to via the
microcontroller interface using the protocol shown in
Fig.23.

It should be noted that SILD must be held HIGH; A3 to A0
identifies the register number and D3 to D0 is the data.
The data is latched into the register on the LOW-to-HIGH
transition of RAB.

7.15.1.2

Writing repeated data to registers 0 to F

The same data can be repeated several times (e.g. for a
fade function) by applying extra RAB pulses as shown in
Fig.24. It should be noted that SCL must stay HIGH
between RAB pulses.

7.15.1.3

Reading decoder status information on SDA

There are several internal status signals, selected via
register 2, which can be made available on the SDA line:

SUBQREADY-I: LOW if new subcode word is ready in
Q-channel register

MOTSTART1: HIGH if motor is turning at 75% or more
of nominal speed

MOTSTART2: HIGH if motor is turning at 50% or more
of nominal speed

MOTSTOP: HIGH if motor is turning at 12% or less of
nominal speed; can be set to indicate 6% or less
(instead of 12% or less) via register E

PLL lock: HIGH if sync coincidence signals are found

V1: follows input on pin V1

V2: follows input on pin V2

MOTOR-OV: HIGH if the motor servo output stage
saturates

FIFO-OV: HIGH if FIFO overflows

SHOCK: MOTSTART2 + PLL
Lock + MOTOR-OV + FIFO-OV + servo interrupt
signal + OTD (HIGH if shock detected)

LA-SHOCK: latched SHOCK signal.

The status read protocol is shown in Fig.25. It should be
noted that SILD must be held HIGH.

7.15.1.4

Reading Q-channel subcode

To read the Q-channel subcode direct in the 4-wire bus
mode, the SUBQREADY-I signal should be selected as
status signal. The subcode read protocol is illustrated in
Fig.26.

It should be noted that SILD must be held HIGH; after
subcode read starts, the microcontroller may take as long
as it wants to terminate the read operation; when enough
subcode has been read (1 to 96 bits), terminate reading by
pulling RAB LOW.

Alternatively, the Q-channel subcode can be read using a
servo command as follows:

�

Use the read high-level status command to monitor the
subcode ready signal

�

Send the read subcode command and read the required
number of bytes (up to 12)

�

Send the read high-level status command; to re-enable
the decoder interface.

7.15.1.5

Behaviour of the SUBQREADY-I signal

When the CRC of the Q-channel word is good, and no
subcode is being read, the SUBQREADY-I status signal
will react as shown in Fig.27. When the CRC is good and
the subcode is being read, the timing in Fig.28 applies.

If t

(SUBQREADY-I status LOW to end of subcode read)

is below 2.6/n ms, then t

= 13.1/n ms (i.e. the

microcontroller can read all subcode frames if it completes
the read operation within 2.6/n ms after the subcode is
ready). If these criteria are not met, it is only possible to
guarantee that t

will be below 26.2/n ms (approximately).

If subcode frames with failed CRCs are present, the
t

and t

times will be increased by 13.1/n ms for each

defective subcode frame.

It should be noted that in the lock-to-disc mode `n' is
replaced by `d', which is the disc speed factor.

7.15.1.6

Write servo commands

A write data command is used to transfer data (a number
of bytes) from the microcontroller, using the protocol
shown in Fig.29. The first of these bytes is the command
byte and the following are data bytes; the number
(between 1 and 7) depends on the command byte.

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

It should be noted that RAB must be held LOW; the
command or data is interpreted by the SAA7326 after the
HIGH-to-LOW transition of SILD; there must be a
minimum time of 70

�

s between SILD pulses.

7.15.1.7

Writing repeated data in servo commands

The same data byte can be repeated by applying extra
SILD pulses as illustrated in Fig.30. SCL must be HIGH
between the SILD pulses.

7.15.1.8

Read servo commands

A read data command is used to transfer data (status
information) to the microcontroller, using the protocol
shown in Fig.31. The first byte written determines the type
of command. After this byte a variable number of bytes can
be read. It should be noted that RAB must be held LOW;
after the end of the command byte (LOW-to-HIGH
transition on SILD) there must be a delay of 70

�

s before

reading data is started (i.e. the next HIGH-to-LOW
transition on SILD); there must be a minimum time of 70

�

between SILD pulses.

7.15.2

ICROCONTROLLER INTERFACE

C-

BUS MODE

)

Bytes are transferred over the interface in groups
(i.e. servo commands) of which there are two types: write
data commands and read data commands.

The sequence for a write data command (that requires
3 data bytes) is as follows:

�

Send START condition

�

Send address 30H (write)

�

Write command byte

�

Write data byte 1

�

Write data byte 2

�

Write data byte 3

�

Send STOP condition.

It should be noted that more than one command can be
sent in one write sequence.

The sequence for a read data command (that reads 2 data
bytes) is as follows:

�

Send START condition

�

Send address 30H (write)

�

Write command byte

�

Send STOP condition

�

Send START condition

�

Send address 31H (read)

�

Read data byte 1

�

Read data byte 2

�

Send STOP condition.

It should be noted that the timing constraints specified for
the read and write servo commands must still be adhered
to.

SDA

(SAA7326)

SCL

(microcontroller)

RAB

(microcontroller)

SDA

(microcontroller)

MGL699

high-impedance

Fig.23 Microcontroller write protocol for registers 0 to F.

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

7.15.3

ECODER REGISTERS AND SHADOW REGISTERS

To maintain compatibility with the SAA737x series,
decoder registers 0 to F are identical to the SAA7370.
However, to control the extra functionality of SAA7326, a
new set of registers called shadow registers have been
implemented.

These are accessed by using the LSB of decoder
register F. This bit is called SHADEN (shadow registers
enable) on SAA7326. When this bit is set to logic 1 (i.e.
decoder register F set to XXX1), any subsequent
addresses will be decoded by the shadow registers.
In fact, only four addresses are implemented as shadow
registers; 3, 7, A and C. Any other addresses sent while
SHADEN = 1 are invalid and have no effect.

When SHADEN is set to logic 0 (decoder register F set to
XXX0) all subsequent addresses are decoded by the main
decoder registers again.

Access to decoder register F is always enabled so that
SHADEN can be set or reset as required.

The SHADEN bit and subsequent shadow registers are
programmed identically to the main decoder registers, i.e.
they can be directly programmed when using the
SAA7326 in 4-wire mode or programmed via the servo
interface when using 3-wire or I

C-bus modes.

The main decoder registers are shown in Table 14.
The functions implemented using shadow registers are
shown in Table 16.

7.15.4

UMMARY OF FUNCTIONS CONTROLLED BY DECODER REGISTERS

Table 14 Registers 0 to F

REGISTER

ADDRESS

DATA

FUNCTION

INITIAL

(1)

0
(fade and
attenuation)

0000

mute

reset

0010

attenuate

0001

full-scale

0100

step down

0101

step up

1
(motor mode)

0001

X000

motor off mode

reset

X001

motor stop mode 1

X010

motor stop mode 2

X011

motor start mode 1

X100

motor start mode 2

X101

motor jump mode

X111

motor play mode

X110

motor jump mode 1

1XXX

anti-windup active

0XXX

anti-windup off

reset

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

2
(status control
to servo part -
not the STATUS
pin)

0010

0000

status = SUBQREADY-I

reset

0001

status = MOTSTART1

0010

status = MOTSTART2

0011

status = MOTSTOP

0100

status = PLL lock

0101

status = V1

0110

status = V2

0111

status = MOTOR-OV

1000

status = FIFO overflow

1001

status = shock detect

1010

status = latched shock detect

1011

status = latched shock detect reset

3
(DAC output)

0011

1010

S-bus; CD-ROM mode

1011

EIAJ; CD-ROM mode

1100

S-bus; 18-bit; 4f

mode

reset

1111

S-bus; 18-bit; 2f

mode

1110

S-bus; 16-bit; f

mode

0000

EIAJ; 16-bit; 4f

0011

EIAJ; 16-bit; 2f

0010

EIAJ; 16-bit; f

0100

EIAJ; 18-bit; 4f

0111

EIAJ; 18-bit; 2f

0110

EIAJ; 18-bit; f

4
(motor gain)

0100

X000

motor gain G = 3.2

reset

X001

motor gain G = 4.0

X010

motor gain G = 6.4

X011

motor gain G = 8.0

X100

motor gain G = 12.8

X101

motor gain G = 16.0

X110

motor gain G = 25.6

X111

motor gain G = 32.0

0XXX

disable comparator clock divider

reset

1XXX

enable comparator clock divider; only if SELLPLL
set HIGH

5
(motor
bandwidth)

0101

XX00

motor f

= 0.5

�

n Hz

reset

XX01

motor f

= 0.7

�

n Hz

XX10

motor f

= 1.4

�

n Hz

XX11

motor f

= 2.8

�

n Hz

00XX

motor f

= 0.85

�

n Hz

reset

01XX

motor f

= 1.71

�

n Hz

10XX

motor f

= 3.42

�

n Hz

REGISTER

ADDRESS

DATA

FUNCTION

INITIAL

(1)

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

6
(motor output
configuration)

0110

XX00

motor power maximum 37%

reset

XX01

motor power maximum 50%

XX10

motor power maximum 75%

XX11

motor power maximum 100%

00XX

MOTO1 and MOTO2 pins 3-state

reset

01XX

motor PWM mode

10XX

motor PDM mode

11XX

motor CDV mode

7
(DAC output
and status
control)

0111

XX00

interrupt signal from servo at STATUS pin

reset

XX10

status bit from decoder status register at STATUS
pin

X0XX

DAC data normal value

reset

X1XX

DAC data inverted value

0XXX

left channel first at DAC (WCLK normal)

reset

1XXX

right channel first at DAC (WCLK inverted)

8
(PLL loop filter
bandwidth)

see Table 15

9
(PLL
equalization)

1001

0011

PLL loop filter equalization

reset

0001

PLL 30 ns over-equalization

0010

PLL 15 ns over-equalization

0100

PLL 15 ns under-equalization

0101

PLL 30 ns under-equalization

A
(EBU output)

1010

XX0X

EBU data before concealment

XX1X

EBU data after concealment and fade

reset

X0X0

level II clock accuracy (<1000 ppm)

reset

X0X1

level I clock accuracy (<50 ppm)

X1X0

level III clock accuracy (>1000 ppm)

X1X1

EBU off - output low

0XXX

flags in EBU off

reset

1XXX

flags in EBU on

B
(speed control)

1011

X0XX

33.8688 MHz crystal present, or 8.4672 MHz (or
16.9344 MHz) crystal with SELPLL set HIGH

reset

X1XX

16.9344 MHz crystal present

0XXX

single-speed mode

reset

1XXX

double-speed mode

XX00

standby 1: `CD-STOP' mode

reset

XX10

standby 2: `CD-PAUSE' mode

XX11

operating mode

REGISTER

ADDRESS

DATA

FUNCTION

INITIAL

(1)

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

Note

1. The initial column shows the power-on reset state.

C
(versatile pins
interface)

1100

XXX1

external off-track signal input at V1

XXX0

internal off-track signal used (V1 may be read via
status)

reset

XX0X

kill-L at KILL output, kill-R at V3 output

001X

V3 = 0; single KILL output

reset

011X

V3 = 1; single KILL output

D
(versatile pins
interface)

1101

0000

4-line motor (using V4 and V5)

XX01

Q-to-W subcode at V4

XX10

V4 = 0

XX11

V4 = 1

reset

01XX

de-emphasis signal at V5, no internal
de-emphasis filter

10XX

V5 = 0

11XX

V5 = 1

reset

1110

00XX

audio features disabled

01XX

audio features enabled

reset

XX0X

lock-to-disc mode disabled

reset

XX1X

lock-to-disc mode enabled

XXX0

motor brakes to 12%

reset

XXX1

motor brakes to 6%

F
(subcode
interface and
shadow register
enable)

1111

X0XX

subcode interface off

reset

X1XX

subcode interface on

0XXX

4-wire subcode

reset

1XXX

3-wire subcode

XXX0

SHADEN = 0; shadow registers not enabled;
addresses will be decoded by main decoder
registers

reset

XXX1

SHADEN = 1; shadow registers enabled; all
subsequent addresses will be decoded by
shadow registers, not decoder registers

REGISTER

ADDRESS

DATA

FUNCTION

INITIAL

(1)

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

Table 15 Loop filter bandwidth

Note

1. The initial column shows the power-on reset state.

7.15.5

UMMARY OF FUNCTIONS CONTROLLED BY SHADOW REGISTERS

Table 16 Shadow register settings

REGISTER

ADDRESS

DATA

FUNCTION

INITIAL

(1)

LOOP

BANDWIDTH

(Hz)

INTERNAL

BANDWIDTH

(Hz)

LOW-PASS

BANDWIDTH

(Hz)

8
(PLL loop filter
bandwidth)

1000

0000

1640

�

525

�

8400

�

0001

3279

�

263

�

16800

�

0010

6560

�

131

�

33600

�

0100

1640

�

1050

�

8400

�

0101

3279

�

525

�

16800

�

0110

6560

�

263

�

33600

�

1000

1640

�

2101

�

8400

�

1001

3279

�

1050

�

16800

�

reset

1010

6560

�

525

�

33600

�

1100

1640

�

4200

�

8400

�

1101

3279

�

2101

�

16800

�

1110

6560

�

1050

�

33600

�

SHADEN BIT

SHADOW

REGISTER

ADDRESS

DATA

FUNCTION

INITIAL

3
control of
versatile and
clock pins

0011

XXX0

select CL4 on CL11/4 output

reset

XXX1

select CL11 on CL11/4 output

XX0X

enable CL11/4 output pin

reset

XX1X

set CL11/4 output pin to
high-impedance

X0XX

enable CL16 output pin

reset

X1XX

set CL16 output pin to
high-impedance

0XXX

V2/V3 pin configured as V2 input

reset

1XXX

V2/V3 pin configured as V3 output
(open-drain)

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

7
control of
onboard DAC

0111

XXX0

hold onboard DAC outputs at zero

reset

XXX1

enable onboard DAC outputs

XX0X

use external DAC or route audio
data into onboard DAC (loopback
mode)

reset

XX1X

route audio data into onboard DAC
(non-loopback mode)

7
servo
reference
pin 7, V

RIN

X1XX

use internal reference for servo
reference voltage

reset

X0XX

use external reference for servo
reference voltage

A
signal
magnitude
control for
diodes
D1 to D4

1010

0000

(0.042).I

ref

= 1.006

�

A (nominal)

0001

(0.083).I

ref

= 2.013

�

A (nominal)

0010

(0.125).I

ref

= 3.019

�

A (nominal)

0011

(0.167).I

ref

= 4.025

�

A (nominal)

0100

(0.208).I

ref

= 5.031

�

A (nominal)

0101

(0.25).I

ref

= 6.034

�

A (nominal)

0110

(0.292).I

ref

= 7.044

�

A (nominal)

0111

(0.333).I

ref

= 8.05

�

A (nominal)

1000

(0.375).I

ref

= 9.056

�

A (nominal)

1001

(0.417).I

ref

= 10.063

�

A (nominal)

1010

(0.458).I

ref

= 11.069

�

A (nominal)

1011

(0.5).I

ref

= 12.075

�

A (nominal)

1100

(0.542).I

ref

= 13.081

�

A (nominal)

1101

(0.583).I

ref

= 14.088

�

A (nominal)

1110

(0.625).I

ref

= 15.094

�

A (nominal)

1111

(0.667).I

ref

= 16.1

�

A (nominal)

reset

SHADEN BIT

SHADOW

REGISTER

ADDRESS

DATA

FUNCTION

INITIAL

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

7.15.6

UMMARY OF SERVO COMMANDS

A list of the servo commands is given in Table 17. These are fully compatible with SAA7370.

Table 17 SAA7326 servo commands

Notes

1. These commands only available when internal decoder interface is enabled.

2. <peak_l> and <peak_r> bytes are clocked out LSB first.

3. Decoder status flag information in <dec_stat> is only valid when the internal decoder interface is enabled.

COMMANDS

CODE

BYTES

PARAMETERS

Write commands

Write_focus_coefs1

17H

<foc_parm3> <foc_int> <ramp_incr> <ramp_height> <ramp_offset>
<FE_start> <foc_gain>

Write_focus_coefs2

27H

<defect_parm> <rad_parm_jump> <vel_parm2> <vel_parm1>
<foc_parm1> <foc_parm2> <CA_drop>

Write_focus_command

33H

<foc_mask> <foc_stat> <shock_level>

Focus_gain_up

42H

<foc_gain> <foc_parm1>

Focus_gain_down

62H

<foc_gain> <foc_parm1>

Write_radial coefs

57H

<rad_length_lead> <rad_int> <rad_parm_play> <rad_pole_noise>
<rad_gain> <sledge_parm2> <sledge_parm_1>

Preset_Latch

81H

<chip_init>

Radial_off

C1H

1CH

Radial_init

C1H

3CH

Short_jump

C3H

<tracks_hi> <tracks_lo> <rad_stat>

Long_jump

C5H

<brake_dist> <sledge_U_max> <tracks_hi> <tracks_lo> <rad_stat>

Steer_sledge

B1H

<sledge_level>

Preset_init

93H

<re_offset> <re_gain> <sum_gain>

Write_decoder_reg

(1)

D1H

<decoder_reg_data>

Write_parameter

A2H

<param_ram_addr> <param_data>

Read commands

Read_Q_subcode

(1)(2)

up to 12 <Q_sub1 to 10> <peak_l> <peak_r>

Read_status

70H

up to 5

<foc_stat> <rad_stat> <rad_int_lpf> <tracks_hi> <tracks_lo>

Read_hilevel_status

(3)

E0H

up to 4

Read_aux_status

F0H

up to 3

<re_offset> <re_gain> <sum_gain>

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

7.15.7

UMMARY OF SERVO COMMAND PARAMETERS

Table 18 Servo command parameters

PARAMETER

RAM

ADDRESS

AFFECTS

POR

VALUE

DETERMINES

foc_parm_1

focus PID

end of focus lead

defect detector enabling

foc_parm_2

focus PID

focus low-pass

focus error normalising

foc_parm_3

focus PID

focus lead length

minimum light level

foc_int

14H

focus PID

focus integrator crossover frequency

foc_gain

15H

focus PID

70H

focus PID loop gain

CA_drop

12H

focus PID

sensitivity of drop-out detector

ramp_offset

16H

focus ramp

asymmetry of focus ramp

ramp_height

18H

focus ramp

peak-to-peak value of ramp voltage

ramp_incr

focus ramp

slope of ramp voltage

FE_start

19H

focus ramp

minimum value of focus error

rad_parm_play

28H

radial PID

end of radial lead

rad_pole_noise

29H

radial PID

radial low-pass

rad_length_lead

1CH

radial PID

length of radial lead

rad_int

1EH

radial PID

radial integrator crossover frequency

rad_gain

2AH

radial PID

70H

radial loop gain

rad_parm_jump

27H

radial jump

filter during jump

vel_parm1

1FH

radial jump

PI controller crossover frequencies

vel_parm2

32H

radial jump

jump pre-defined profile

speed_threshold

48H

radial jump

maximum speed in fastrad mode

hold_mult

49H

radial jump

00H

electronic damping

sledge bandwidth during jump

brake_dist_max

21H

radial jump

maximum sledge distance allowed in fast
actuator steered mode

sledge_long_brake

58H

radial jump

FFH

brake distance of sledge

sledge_Umax

sledge

voltage on sledge during long jump

sledge_level

sledge

voltage on sledge when steered

sledge_parm_1

36H

sledge

sledge integrator crossover frequency

sledge_parm_2

17H

sledge

sledge low-pass frequencies

sledge gain

sledge operation mode

sledge_pulse1

46H

pulsed sledge

pulse width

sledge_pulse2

64H

pulsed sledge

pulse height

defect_parm

defect detector

defect detector setting

shock_level

shock detector

shock detector operation

playwatchtime

54H

Watchdog

radial on-track Watchdog time

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

jumpwatchtime

57H

Watchdog

radial jump Watchdog time-out

radcontrol

59H

Watchdog

enable/disable automatic radial off feature

chip_init

set-up

enable/disable decoder interface

xtra_preset

4AH

set-up

38H

laser on/off

RA, FO and SL PDM modulating frequency

fast jumping circuit on/off

cd6cmd

4DH

decoder interface

decoder part commands

interrupt_mask

53H

STATUS pin

enabled interrupts

seq_control

42H

autosequencer

autosequencer control

focus_start_time

5EH

autosequencer

focus start time

motor_start_time1

5FH

autosequencer

motor start 1 time

motor_start_time2

60H

autosequencer

motor start 2 time

radial_init_time

61H

autosequencer

radial initialization time

brake_time

62H

autosequencer

brake time

RadCmdByte

63H

autosequencer

radial command byte

osc_inc

68H

focus/radial AGC

AGC control

frequency of injected signal

phase_shift

67H

focus/radial AGC

phase shift of injected signal

level1

69H

focus/radial AGC

amplitude of signal injected

level2

6AH

focus/radial AGC

amplitude of signal injected

agc_gain

6CH

focus/radial AGC

focus/radial gain

PARAMETER

RAM

ADDRESS

AFFECTS

POR

VALUE

DETERMINES

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

Notes

1. All V

(and V

pos

) connections and V

(and V

neg

) connections must be made externally to the same power supply.

2. Equivalent to discharging a 100 pF capacitor via a 1.5 k

series resistor with a rise time of 15 ns.

3. Equivalent to discharging a 200 pF capacitor via a 2.5

�

H series inductor.

CHARACTERISTICS

= 3.0 to 3.6 V; V

= 0 V; T

amb

40 to +85

�

C; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

supply voltage

note 1

0.5

+3.6

I(max)

maximum input voltage

any input

0.5

+ 0.5

pins SDA, SCL, RAB and SILD

0.5

+5.5

output voltage (any output)

0.5

+3.6

DD(diff)

difference between V

DDA

, V

DDD

and V

pos

�

0.25

output current (continuous)

�

I(d)

DC input diode current (continuous)

�

electrostatic handling

note 2

2000

+2000

note 3

200

+200

amb

ambient temperature

+85

�

stg

storage temperature

+125

�

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply

supply voltage

3.0

3.3

3.6

supply current

= 3.3 V; n = 1

mode

= 3.3 V; n = 2

mode

Bitstream DAC output (V

DDD

= 3.3 V; V

pos

= 3.3 V; V

= 0 V; V

neg

= 0 V; T

amb

= 25

�

IFFERENTIAL OUTPUTS

: LN, LP, RN

AND

S/N

signal-to-noise ratio

note 1

(THD + N)/S total harmonic distortion

plus noise-to-signal ratio

at 0 dB; note 1

Servo and decoder analog functions (V

DDA

= 3.3 V; V

SSA

= 0 V; T

amb

= 25

�

EFERENCE GENERATOR

REF

Iref

reference voltage level

1.14

1.2

1.26

ref

input reference current

�

Iref

external resistor

�

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

Decoder analog front-end (V

DDA

= 3.3 V; V

SSA

= 0 V; T

amb

= 25

�

OMPARATOR INPUTS

: HFIN

AND

HFREF

clk

clock frequency

note 2

MHz

th(sw)

switching voltage threshold

0.5V

i(HFIN)

input voltage level (HFIN)

1.0

Servo analog part (V

DDA

= 3.3 V; V

SSA

= 0 V; T

amb

= 25

�

C; R

Iref

= 30 k

)

INS

D4; R1

AND

D(max)

maximum input current for
central diode input signal

note 3

1.006

16.1

�

R(max)

maximum input current for
satellite diode input signal

note 3

1.006

16.1

�

RIN

internally generated
reference voltage

note 4

0.64

0.9

externally generated
reference voltage applied
to V

RIN

(pin 7)

note 4

0.5

0.5V

+ 0.1 V

(THD + N)/S total harmonic distortion

plus noise-to-signal ratio

at 0 dB; note 5

S/N

signal-to-noise ratio

PSRR

power supply ripple
rejection at V

DDA2

note 6

tol

gain tolerance

note 7

+20

variation of gain between
channels

channel separation

Digital inputs

INS

RESET

AND

V1 (CMOS

INPUT WITH PULL

UP RESISTOR AND HYSTERESIS

)

thr(sw)

switching voltage threshold
rising

0.8V

DDD

thf(sw)

switching voltage threshold
falling

0.2V

DDD

hys

hysteresis voltage

0.4

i(pu)

input pull-up resistance

= 0 V

160

input capacitance

resL

reset pulse width
(active LOW)

RESET only

�

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

SELPLL (CMOS

INPUT WITH PULL

UP RESISTOR

)

LOW-level input voltage

0.3

0.3V

DDD

HIGH-level input voltage

0.7V

DDD

+ 0.3

i(pu)

input pull-up resistance

= 0 V

160

input capacitance

INS

TEST1, TEST2

AND

TEST3 (CMOS

INPUTS WITH PULL

DOWN RESISTORS

)

LOW-level input voltage

0.3

+0.3V

DDD

HIGH-level input voltage

0.7V

DDD

+ 0.3

i(pu)

input pull-down resistance

= V

DDD

160

input capacitance

INS

RCK, WCLI, SDI

AND

SCLI (CMOS

INPUTS

)

LOW-level input voltage

0.3

+0.3V

DDD

HIGH-level input voltage

0.7V

DDD

+ 0.3

input leakage current

= 0 to V

DDD

+10

�

input capacitance

INS

SCL, SILD

AND

RAB (5 V

TOLERANT

CMOS

INPUTS

)

LOW-level input voltage

0.3

+0.2V

DDD

HIGH-level input voltage

0.8V

DDD

5.5

input leakage current

= 0 to V

DDD

+10

�

input capacitance

Digital outputs

INS

AND

LOW-level output voltage

= 4 mA

0.4

HIGH-level output voltage

4 mA

DDD

0.4

DDD

load capacitance

100

o(r)

output rise time

= 20 pF;

0.4 V to (V

DDD

0.4)

o(f)

output fall time

= 20 pF;

DDD

0.4) to 0.4 V

Open-drain outputs

INS

CFLG, STATUS, KILL

AND

LDON (

OPEN

DRAIN OUTPUT

)

LOW-level output voltage

= 1 mA

0.4

LOW-level output current

load capacitance

o(f)

output fall time

= 50 pF;

DDD

0.4) to 0.4 V

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

3-state outputs

INS

EF, SCLK, WCLK, DATA, CL16, RA, FO, SL, SBSY, SFSY, SUB

AND

CL11/4

LOW-level output voltage

= 1 mA

0.4

HIGH-level output voltage

1 mA

DDD

0.4

DDD

load capacitance

o(r)

output rise time

= 20 pF;

0.4 to (V

DDD

0.4) V

o(f)

output fall time

= 20 pF;

DDD

0.4) to 0.4 V

output 3-state leakage
current

= 0 to V

+10

�

HEN

CL11/4

IS CONFIGURED AS

CL11 O

UTPUT

)

output HIGH time (relative
to clock period)

= 1.5 V

INS

MOTO1, MOTO2

AND

DOBM

LOW-level output voltage

= 4 mA

0.4

HIGH-level output voltage

4 mA

DDD

0.4

load capacitance

100

o(r)

output rise time

= 20 pF;

0.4 to (V

DDD

0.4) V

o(f)

output fall time

= 20 pF;

DDD

0.4) to 0.4 V

output 3-state leakage
current

= 0 to V

+10

�

Digital input/output

SDA (5 V

TOLERANT

CMOS

INPUT

OPEN

DRAIN

C-

BUS OUTPUT

)

LOW-level input voltage

0.3

+0.2V

DDD

HIGH-level input voltage

0.8V

DDD

5.5

3-state leakage current

= 0 to V

DDD

+10

�

input capacitance

LOW-level output voltage

= 2 mA

0.4

LOW-level output current

load capacitance

o(f)

output fall time

= 20 pF;

0.85V

DDD

to 0.4

V2/V3 (CMOS

INPUT WITH PULL

UP RESISTOR AND HYSTERESIS

OPEN

DRAIN OUTPUT

)

thr(sw)

switching voltage threshold
rising

0.8V

DDD

thf(sw)

switching voltage threshold
falling

0.2V

DDD

hys

hysteresis voltage

1.35

1.65

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

Notes

1. Assumes use of external components as shown in the application diagram (Figs 38 or 39).

2. Highest clock frequency at which data slicer produces 1010 output in analog self-test mode.

3. The maximum input current depends on the value of the external resistor connected to I

ref

and the settings of shadow

registers A and C:

a) With R

Iref

= 30 k

, minimum I

max

= (0.025). I

ref

(0.025)

�

(40

�

A) = 1

�

b) With R

Iref

= 30 k

, maximum I

max

= (0.4). I

ref

(0.4)

�

(40

�

A) = 16

�

4. V

RIN

can be set to an internal source or an externally applied reference voltage using shadow register 7.

5. Measuring bandwidth: 200 Hz to 20 kHz, f

i(ADC)

= 1 kHz.

6. f

ripple

= 1 kHz, V

ripple

= 0.5 V (p-p).

7. Gain of the ADC is defined as G

ADC

= f

sys

max

(counts/

�

A); thus digital output = I

�

ADC

where:

a) Digital output = the number of pulses at the digital output in counts/s and I

= the DC input current in

�

b) The maximum input current depends on R

Iref

and on shadow registers A and C.

c) The gain tolerance is the deviation from the calculated gain.

i(pu)

input pull-up resistance

= 0 V

120

input capacitance

LOW-level output voltage

= 1 mA

0.4

LOW-level output current

load capacitance

o(f)

output fall time

= 20 pF;

DDD

0.4) to 0.4 V

Crystal oscillator

NPUT

CRIN (

EXTERNAL CLOCK

)

LOW-level input voltage

0.3

+0.2V

HIGH-level input voltage

0.8V

+ 0.3

input leakage current

+10

�

input capacitance

UTPUT

CROUT;

SEE

IGS

AND

xtal

crystal frequency

�

100 ppm

8.4672

MHz

mutual conductance at
start-up

mA/V

feedback capacitance

output capacitance

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

10 OPERATING CHARACTERISTICS (SUBCODE INTERFACE TIMING)
V

= 3.0 to 3.6 V; V

= 0 V; T

amb

40 to +85

�

C; unless otherwise specified.

Note

1. The subcode timing is directly related to the overspeed factor `n' in normal operating mode. `n' is replaced by the disc

speed factor `d', in lock-to-disc mode.

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

Subcode interface timing (single-speed

�

n); see Fig.32; note 1

NPUT

RCK

CLKH

input clock HIGH time

2/n

4/n

6/n

�

CLKL

input clock LOW time

2/n

4/n

6/n

�

input clock rise time

80/n

input clock fall time

80/n

d(SFSY-RCK)

delay time SFSY to RCK

10/n

20/n

�

UTPUTS

PINS

SBSY, SFSY

AND

SUB (C

= 20 pF)

cy(block)

block cycle time

12.0/n

13.3/n

14.7/n

W(SBSY)

SBSY pulse width

300/n

�

cy(frame)

frame cycle time

122/n

136/n

150/n

�

W(SFSY)

SFSY pulse width (3-wire mode only)

366/n

�

SFSYH

SFSY HIGH time

66/n

�

SFSYL

SFSY LOW time

84/n

�

d(SFSY-SUB)

delay time SFSY to SUB (P data) valid

1/n

�

d(RCK-SUB)

delay time RCK falling to SUB

�

h(RCK-SUB)

hold time RCK to SUB

0.7/n

�

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

11 OPERATING CHARACTERISTICS (I

S-BUS TIMING)

= 3.0 to 3.6 V; V

= 0 V; T

amb

40 to +85

�

C; unless otherwise specified.

Note

1. The I

S-bus timing is directly related to the overspeed factor `n' in the normal operating mode. In the lock-to-disc

mode `n' is replaced by the disc speed factor `d'.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

UNIT

S-bus timing (single speed

�

n); see Fig.33; note 1

LOCK OUTPUT

: SCLK (C

= 20 pF)

output clock period

sample rate = f

472.4/n

sample rate = 2f

236.2/n

sample rate = 4f

118.1/n

clock HIGH time

sample rate = f

166/n

sample rate = 2f

83/n

sample rate = 4f

42/n

clock LOW time

sample rate = f

166/n

sample rate = 2f

83/n

sample rate = 4f

42/n

UTPUTS

: WCLK, DATA

AND

EF (C

= 20 pF)

set-up time

sample rate = f

95/n

sample rate = 2f

48/n

sample rate = 4f

24/n

hold time

sample rate = f

95/n

sample rate = 2f

48/n

sample rate = 4f

24/n

V � 0.8 V

0.8 V

V � 0.8 V

0.8 V

t CH

MBG407

t CL

clock period Tcy

SCLK

WCLK

DATA

t h

t su

Fig.33 I

S-bus timing diagram.

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

12 OPERATING CHARACTERISTICS (MICROCONTROLLER INTERFACE TIMING)
V

= 3.0 to 3.6 V; V

= 0 V; T

amb

40 to +85

�

C; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

NORMAL MODE

LOCK-TO-DISC MODE

UNIT

MIN.

MAX.

MIN.

MAX.

Microcontroller interface timing (4-wire bus mode; writing to decoder registers 0 to F; reading Q-channel
subcode and decoder status); see Figs 34 and 35; note 1

NPUTS

SCL

AND

RAB

input LOW time

480/n + 20

2400/n + 20

input HIGH time

480/n + 20

2400/n + 20

rise time

480/n

fall time

480/n

EAD MODE

= 20 pF)

dRD

delay time RAB to SDA
valid

propagation delay SCL
to SDA

720/n

960/n + 20

720/n + 20

4800/n + 20 ns

dRZ

delay time RAB to SDA
high-impedance

RITE MODE

= 20 pF)

suD

set-up time SDA to SCL

note 2

720/n

hold time SCL to SDA

960/n + 20

4800/n + 20 ns

suCR

set-up time SCL to RAB

240/n + 20

1200/n + 20

dWZ

delay time SDA
high-impedance to RAB

Microcontroller interface timing (4-wire bus mode; servo commands); see Figs 35 and 36

NPUTS

SCL

AND

SILD

input LOW time

710

input HIGH time

710

rise time

240

fall time

240

EAD MODE

= 20 pF)

dLD

delay time SILD to SDA
valid

propagation delay SCL
to SDA

950

dLZ

delay time SILD to SDA
high-impedance

sCLR

set-up time SCL to SILD

480

hCLR

hold time SILD to SCL

830

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

Notes

1. The 4-wire bus mode microcontroller interface timing for writing to decoder registers 0 to F, and reading Q-channel

subcode and decoder status, is a function of the overspeed factor `n'. In the lock-to-disc mode the maximum data
rate is lower.

2. Negative set-up time means that the data may change after clock transition.

3. If a 16.9344 MHz crystal is used and SELPLL = 0 then the timings are divided-by-2 until the microcontroller has

written X1XX to register B.

RITE MODE

= 20 pF)

set-up time SDA to SCL

hold time SCL to SDA

950

sCL

set-up time SCL to SILD

480

hCL

hold time SILD to SCL

120

dPLP

delay between two SILD
pulses

�

dWZ

delay time SDA
high-impedance to SILD

SYMBOL

PARAMETER

CONDITIONS

NORMAL MODE

LOCK-TO-DISC MODE

UNIT

MIN.

MAX.

MIN.

MAX.

Fig.34 4-wire bus microcontroller timing; read mode (Q-channel subcode and decoder status information).

SDA (SAA7326)

SCL

RAB

0.8 V

VDD

0.8 V

VDD

0.8 V

VDD

0.8 V

tPD

tCL

tCH

tdRD

tdRZ

high-impedance

MGL707

2000

Jun

Philips Semiconductors

Product specification

Digital ser

processor and Compact Disc

decoder with integ

r
ated D

C (CD10 II)

SAA7326

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APPLICA

TION INFORMA

TION

k, full pagewidth

MGL711

22 k

1 k

10 k

30 k

2.2

SAA7326

MECHANISM

AND

AMPLIFIER

(TDA1300)

(4)

SBSY

SFSY

SUB

RCK

TEST3

STATUS

SILD

RAB

SCL

SDA

SCLI

SDI

WCLI

V2/V3

VSSD1

HFREF

HFIN

ISLICE

VSSA1

VDDA1

VDDA

Iref

VRIN

VSSA2

CROUT

CRIN

left output

to external

DAC or ESA

to power

amplifiers

to DOBM

transformer

to CD graphics

LDON

MOTO2

MOTO1

SSD3

DDD2(C)

CFLG

DDD1(P)

DOBM

SSD2

CL11/4

DDA2

neg

pos

SELPLL

TEST1

CL16

DATA

WCLK

SCLK

TEST2

KILL

RESET

�

33 pF

100 nF

220 pF

RFE

LDON

47 pF

( 3 )

(1)

100 nF

1.5

220

1.5

(2)

100 nF

1 nF

22 nF

100 nF

VDDA

VDDD

1/2 VDDD

(2)

1/2 VDDD

(2)

MOTOR

INTERFACE

to micro-

controller

interface

to ESA

serial data

loopback

VDDD

2.2

VDDD

2.2

4.7
k

VDDD

4.7
k

100

100 nF

�

2.2

220

10 k

right output

11 k

220

10 k

Fig.38 Typical application diagram for current mechanisms.

(1) For crystal oscillator see Figs 3 and 4.

(2) 1.5 nF capacitors connected between

pins LN and LP, RN and RP must be
placed as near to the pins as possible.
This also applies to the 220 nF and 47

�

capacitors connected between pins V

neg

and V

pos

. Power supplies and V

DDD

reference inputs (

DDD

) for DAC

operational amplifiers must be low noise.

(3) For single speed applications, use 47 pF,

capacitors, for double speed use 22 pF
capacitors.

(4) The connections to TDA1300 are shown

for single Foucault mechanisms.

2000

Jun

Philips Semiconductors

Product specification

Digital ser

processor and Compact Disc

decoder with integ

r
ated D

C (CD10 II)

SAA7326

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,

f
u

l
l

p

i
d

t
h

MGL698

22 k

10 k

1 k

30 k

2.2

SAA7326

LP FILTER

(5)

V I

(5)

OEIC

(4)

TZA1024

(4)

RFEQO

SBSY

SFSY

SUB

RCK

TEST3

STATUS

SILD

RAB

SCL

SDA

SCLI

SDI

WCLI

V2/V3

VSSD1

HFREF

HFIN

ISLICE

VSSA1

VDDA1

VDDA

Iref

VRIN

VSSA2

CROUT

CRIN

left output

to external

DAC or ESA

to power

amplifiers

to DOBM

transformer

to CD graphics

(
C

)

(
P

)

/
4

I
L

RESET

�

33 pF

100 nF

220 pF

VCOM

CMFB

DIN

D1-D4

(4)

RFFB

PWRON

47 pF

( 3 )

(1)

100 nF

1.5

220

1.5

(2)

100 nF

3 nF

100 nF

VDDA

VDDD

1/2 VDDD

(2)

1/2 VDDD

(2)

MOTOR

INTERFACE

to micro-

controller

interface

to ESA

serial data

loopback

VCC

VDDD

2.2

VDDD

2.2

4.7
k

VDDD

4.7
k

100

100 nF

�

2.2

220

10 k

right output

11 k

220

10 k

Fig.39 Typical application diagram for voltage mechanisms.

(1) For crystal oscillator see Figs 3 and 4.

(2) 1.5 nF capacitors connected between pins

LN and LP, RN and RP must be placed as near to
the pins as possible. This also applies to the
220 nF and 47

�

F capacitors connected between

pins V

neg

and V

pos

. Power supplies and V

DDD

reference inputs (

DDD

) for DAC operational

amplifiers must be low noise.

(3) For single speed applications, use 47 pF

capacitors, for double speed use 22 pF capacitors.

(4) For connections between OEIC and TZA1024,

refer to TZA1024 device specification.

(5) Components for LP filter and V to I conversion

depend on OEIC and current range set on
SAA7326.

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

15 SOLDERING

15.1

Introduction to soldering surface mount
packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"Data Handbook IC26; Integrated Circuit Packages"

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

15.2

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250

�

C. The top-surface temperature of the

packages should preferable be kept below 230

�

15.3

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

�

Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

�

For packages with leads on two sides and a pitch (e):

� larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

� smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

�

For packages with leads on four sides, the footprint must
be placed at a 45

�

angle to the transport direction of the

printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250

�

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

15.4

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300

�

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320

�

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

15.5

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

"Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods".

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45

�

angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

PACKAGE

SOLDERING METHOD

WAVE

REFLOW

(1)

BGA, LFBGA, SQFP, TFBGA

not suitable

suitable

HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS

not suitable

(2)

suitable

PLCC

(3)

, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended

(3)(4)

suitable

SSOP, TSSOP, VSO

not recommended

(5)

suitable

2000 Jun 26

Philips Semiconductors

Product specification

Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)

SAA7326

16 DATA SHEET STATUS

Note

1. Please consult the most recently issued data sheet before initiating or completing a design.

DATA SHEET STATUS

PRODUCT

STATUS

DEFINITIONS

(1)

Objective specification

Development

This data sheet contains the design target or goal specifications for
product development. Specification may change in any manner without
notice.

Preliminary specification

Qualification

This data sheet contains preliminary data, and supplementary data will be
published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.

Product specification

Production

This data sheet contains final specifications. Philips Semiconductors
reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.

17 DEFINITIONS

Short-form specification

The data in a short-form

specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition

Limiting values given are in

accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.

Application information

Applications that are

described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.

18 DISCLAIMERS

Life support applications

These products are not

designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes

Philips Semiconductors

reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.

19 PURCHASE OF PHILIPS I

C COMPONENTS

Purchase of Philips I

C components conveys a license under the Philips' I

C patent to use the

components in the I

C system provided the system conforms to the I

C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

� Philips Electronics N.V.

SCA

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

2000

Philips Semiconductors � a worldwide company

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Printed in The Netherlands

753503/02/pp

Date of release:

2000 Jun 26

Document order number:

9397 750 06993

Электронный компонент: SAA7326H/E

Document Outline