2001 apr 05

Philips Semiconductors

Preliminary specification

DSP for CD and DVD-ROM systems

SAA7335

FEATURES

Compatibility with CD-I, CD-ROM, MPEG-video
DVD-ROM and DVD-video applications

Designed for very high playback speeds

Typical CD-ROM operation up to n = 12, DVD-ROM to
n = 1.9, maximum rates (tbf)

Matched filtering, quad-pass error correction
(C1-C2-C1-C2), overspeed audio playback function
included (up to 3 kbytes buffer)

Lock-to-disc playback, Constant Angular Velocity
(CAV), pseudo-Constant Linear Velocity (CLV) and CLV
motor control loops

Interface to 32 kbytes SRAM for DVD error correction
and de-interleave

Sub-code/ header processing for DVD and CD formats

Programmable HF equalizer

In DVD mode it is still compatible with Philips block
decoders

Sub-CPU interface can be parallel or fast I

C-bus

On-chip clock multiplier.

GENERAL DESCRIPTION

This device is a high-end combined Compact Disc (CD)
and Digital Versatile Disc (DVD) compatible decoding
device. The device operates with an external 32 kbytes
S-RAM memory for de-interleaving operations. The device
provides quad-pass error correction for CD-ROM
applications (C1-C2-C1-C2) and operates in lock-to-disk,
CAV, pseudo CLV and CLV modes.

In DVD modes double-pass C1-C2 error correction is used
which is capable of correcting up to 5 C1 frame errors and
16 C2 frame errors.

The SAA7335 contains all the functions required to
decode an EFM or EFM+ HF signal directly from the laser
pre-amplifier, including analog front-end, PLL data
recovery, demodulation and error correction. The spindle
motor interface provides both motor control signals from
the demodulator and, in addition, contains a tachometer
loop that accepts tachometer pulses from the motor unit.

The SAA7335 has two independent microcontroller
interfaces. The first is a serial I

C-bus and the second is a

standard 8-bit multiplexed parallel interface. Both of these
interfaces provide access to a total of 32

8-bit registers

for control and status.

This data sheet contains an descriptive overview of the
device together with electrical and timing characteristics.
For a detailed description of the device refer to the user
guide

"SAU/UM96018".

Supply of this CD/DVD IC does not convey an implied
license under any patent right to use this IC in any CD or
DVD application.

QUICK REFERENCE DATA

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

DDD

digital supply voltage

4.5

5.0

5.5

DDD

digital supply current

300

DDA

analog supply voltage

4.5

5.0

5.5

DDA

analog supply current

300

xtal

crystal input frequency

tbf

MHz

amb

operating ambient temperature

+70

stg

storage temperature

+125

2001 apr 05

Philips Semiconductors

Preliminary specification

DSP for CD and DVD-ROM systems

SAA7335

PINNING

SYMBOL

PIN

TYPE

DESCRIPTION

SSA1

supply

analog ground 1

ref

analog current reference input for ADC

REFLo

analog low reference input for ADC

REFHi

analog high reference input for ADC

VREF

analog negative input

HFIN

analog positive input

SSA2

supply

analog ground 2

AGCOUT

analog test pin output

DDA2

supply

analog supply voltage 2

DDD1

supply

digital supply voltage 1

SSD1

supply

digital ground 1

OTD

off track detect input

MOTO1

3-state motor control output

n.c.

not connected, reserved

MOTO2/T3

I/O

motor control output/tachometer 3 input

n.c.

not connected, reserved

tachometer 1 input

tachometer 2 input

DDD2

supply

digital supply voltage 2

SSD2

supply

digital ground 2

TEST1

test input 1

TEST2

test input 2

POR

power-on reset input

MUXSWICH

use clock multiplier input

n.c.

not connected, reserved

CL1

divided clock output

BCAIN

BCA input

SDA

I/O

sub-CPU I

C-bus serial data input/output

SCL

sub-CPU I

C-bus serial clock input

INT

sub-CPU interrupt output (open-drain)

DDD3

supply

digital supply voltage 3

SSD3

supply

digital ground 3

da7

I/O

sub-CPU data bus bit 7 input/output (parallel)

da6

I/O

sub-CPU data bus bit 6 input/output (parallel)

da5

I/O

sub-CPU data bus bit 5 input/output (parallel)

n.c.

not connected, reserved

da4

I/O

sub-CPU data bus bit 4 input/output (parallel)

n.c.

not connected, reserved

da3

I/O

sub-CPU data bus bit 3 input/output (parallel)

da2

I/O

sub-CPU data bus bit 2 input/output (parallel)

2001 apr 05

Philips Semiconductors

Preliminary specification

DSP for CD and DVD-ROM systems

SAA7335

da1

I/O

sub-CPU data bus bit 1 input/output (parallel)

n.c.

not connected, reserved

da0

I/O

sub-CPU data bus bit 0 input/output (parallel)

DDD4

supply

digital supply voltage 4

SSD4

supply

digital ground 4

WRi

sub-CPU write enable input (active LOW)

RDi

sub-CPU read enable input (active LOW)

ALE

sub-CPU address latch enable input

CSi

sub-CPU chip select input (active HIGH)

STOPCLOCK

stop clock output

n.c.

not connected, reserved

serial subcode output (for CD)

EBUOUT

digital audio output

SYNC

S-bus sector sync output

FLAG

S-bus correction flag output

DATA

S-bus serial data output

BCLK

I/O

S-bus bit serial clock input/output

WCLK

I/O

S-bus word clock input/output

DDD5

supply

digital supply voltage 5

SSD5

supply

digital ground 5

RAMRW

RAM read/write control output

n.c.

not connected, reserved

RAMDA7

I/O

RAM data bus bit 7 input/output

RAMDA6

I/O

RAM data bus bit 6 input/output

RAMDA5

I/O

RAM data bus bit 5 input/output

RAMDA4

I/O

RAM data bus bit 4 input/output

RAMDA3

I/O

RAM data bus bit 3 input/output

RAMDA2

I/O

RAM data bus bit 2 input/output

n.c.

not connected, reserved

RAMDA1

I/O

RAM data bus bit 1 input/output

RAMDA0

I/O

RAM data bus bit 0 input/output

DDD6

supply

digital supply voltage 6

SSD6

supply

digital ground 6

RAMAD0

RAM address bit 0 output

RAMAD1

RAM address bit 1 output

RAMAD2

RAM address bit 2 output

RAMAD3

RAM address bit 3 output

RAMAD4

RAM address bit 4 output

RAMAD5

RAM address bit 5 output

RAMAD6

RAM address bit 6 output

DDD7

supply

digital supply voltage 7

SYMBOL

PIN

TYPE

DESCRIPTION

2001 apr 05

Philips Semiconductors

Preliminary specification

DSP for CD and DVD-ROM systems

SAA7335

Fig.2 Pin configuration.

handbook, full pagewidth

RAMAD1

RAMAD0

VSSD6
VDDD6

RAMDA0

RAMDA1

n.c.

RAMDA2

RAMDA3

RAMDA4

RAMDA5

RAMDA6

RAMDA7

n.c.

RAMRW

VSSD5
VDDD5

WCLK

BCLK

DATA

FLAG

SYNC

EBUOUT

n.c.

MGK241

VSSA1

Iref

REFLo

REFHi

VREF

HFIN

VSSA2

AGCOUT

VDDA2

VDDD1

VSSD1

OTD

MOTO1

n.c.

MOTO2/T3

n.c.

VDDD2

VSSD2

TEST1

TEST2

POR

MUXSWICH

n.c.

RAMAD6

RAMAD5

RAMAD4

RAMAD3

RAMAD2

DDA1

SSD9

DDD9

MEAS1

CFLG

CROUT

CRIN

SSD8

DDD8

RAMAD14

RAMAD13

RAMAD12

RAMAD11

RAMAD10

n.c.

RAMAD9

RAMAD8

RAMAD7

SSD7

DDD7

DDD3

SSD3

da7

da6

da5

n.c.

da4

n.c.

da3

da2

da1

n.c.

da0

DDD4

SSD4

WRi

RDi

ALE

CSi

STOPCLOCK

CL1

BCAIN

SDA

SCL

INT

100

SAA7335

2001 apr 05

Philips Semiconductors

Preliminary specification

DSP for CD and DVD-ROM systems

SAA7335

FUNCTIONAL DESCRIPTION

Analog front-end

This block converts the HF input to the digital domain using
an 8-bit ADC proceeded by an AGC circuit to obtain the
optimum performance from the convertor. This block is
clocked by ADCCLK which is set by the external crystal
frequency plus a flexible clock multiplier and divider block.

PLL and bit detector

This subsystem recovers the data from the channel
stream. The block corrects asymmetry, performs noise
filtering and equalisation and finally recovers the bit clock
and data from the channel using a digital PLL.

The equalizer and the data slicer are programmable.

Digital logic

All the digital system logic is clocked from the master ADC
clock (ADCCLK) described above.

Advanced bit detector

The advanced bit detector offers improved data recovery
for multi-layer discs and contains two extra detection
circuits to increase the margins in the bit recovery block:

1. Adaptive slicer: adds a second stage slicer with higher

bandwidth

2. Run length 2 push-back: all T2 run lengths are pushed

back to T3, thereby automatically determining the
erroneous edge and shifting the transitions on that
edge.

Demodulator

RAME SYNC PROTECTION

MODE

This circuit detects the frame synchronization signals.
Two synchronization counters are used in the SAA7335:

1. The coincidence counter: this is used to detect the

coincidence of successive syncs. It generates a sync
coincidence signal if 2 syncs are 588

1 EFM clocks

apart.

2. The main counter: this is used to partition the EFM

signal into 17-bit words. This counter is reset when:

a) A sync coincidence is generated

b) A sync is found within

6 EFM clocks of its

expected position.

The sync coincidence signal is also used to generate the
lock signal which will go active HIGH when 1 sync
coincidence is found. It will reset to LOW when, during
61 consecutive frames, no sync coincidence is found.

RAME SYNC PROTECTION

DVD

MODE

This circuit detects the frame synchronization signals.
Two synchronization counters are used in the SAA7335:

1. The coincidence counter: this is used to detect the

coincidence of successive syncs. It generates a sync
coincidence signal if 2 syncs are 1488

3 EFM+

clocks apart.

2. The main counter: this is used to partition the EFM+

signal into 16-bit words. This counter is reset when:

a) A sync coincidence is generated

b) A sync is found within

10 EFM+ clocks of its

expected position.

EFM/EFM+ demodulation

The 14-bit EFM (16-bit EFM+) data and subcode words
are decoded into 8-bit symbols.

2001 apr 05

Philips Semiconductors

Preliminary specification

DSP for CD and DVD-ROM systems

SAA7335

Microcontroller interface

The SAA7335 has two microcontroller interfaces, one
serial I

C-bus and one parallel (8051 microcontroller

compatible).

The two communication modes may be operated at the
same time, the modes are described below:

1. Parallel mode: protocol compatible with 8052

multiplexed bus:

a) da0 to da7 = address/data bus

b) ALE = Address Latch Enable, latches the address

information on the bus

c) WRi = active LOW write signal for write to

SAA7335

d) RDi = active LOW read signal for read from

SAA7335

e) CSi = active HIGH Chip Select signal (this signal

gates the RDi and WRi signals).

2. I

C-bus mode: I

C-bus protocol where SAA7335

behaves as slave device where:

a) SDA = I

C-bus data

b) SCL = I

C-bus clock

c) I

C-bus slave address (write mode) = 3EH

d) I

C-bus slave address (read mode) = 3FH

e) Maximum data transfer rate = 400 kbits/s.

ICROCONTROLLER INTERFACE

C-

BUS MODE

)

Bytes are transferred over the interface in single bytes of
which there are two types; write data commands and read
data commands.

The sequence for a write data command (1 data byte) is as
follows:

Send START condition

Send address 3EH (write)

Write command address byte

Write data byte

Send STOP condition.

The sequence for a read data command (that reads 1 data
byte) is as follows:

Send START condition

Send address 3EH (write)

Write status address byte

Send STOP condition

Send START condition

Send address 3FH (read)

Read data byte

Send STOP condition.

EADING AND WRITING DATA TO THE

SAA7335

The SAA7335 has 32

8-bit configuration and status

registers as shown in Table 1. Not all locations are
currently defined and some remain reserved for future
upgrades. These can be written to or read from via the
microcontroller interface using either the serial or parallel
control bus.

2001

apr

Philips Semiconductors

Preliminar

y specification

DSP f

or CD and D

VD-R

OM systems

SAA7335

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EGISTER

Table 1

SAA7335 microcontroller register map

ADDRESS

NAME

R/W

BIT

DEC

HEX

PLL_LOCK

Lock Oride

Pha_Oset

PLL_Force_L

PLL_Freq_R

PLL measured frequency (bits 9 to 2)

PLL_SET

SliceBW

Integ_F0

PLLBW_F1

LP_BW_F3

PLL_ASSYM

PLL asymmetry value (8 bits)

PLL_FREQ

PLL frequency (8 MSBs)

PLL_Jit

jitter value (bits 9 to 2)

PLL_EQU

PLL frequency (2 LSBs)

equalizer tap

equaliser tap

PLL_Lock_In

reserved

Long_Symb F_Lock

In_Lock

PLL_F_MEAS

RL3_EN

reserved

EFM nominal setting (101110)

reserved

OUTPUT1

Fmat(3 to 1)

WCLK_Op

BCLK_Op

Fmat (0)

SyncSwap (1 and 0)

reserved

OUTPUT2

EBU_Valid

EBU_On

EBU control bits 28, 29

EBU control bits (1 to 4)

reserved

OUTPUT3

WCLK_H_
Left

Descr_On

Interp_On

CD_ROM_
Header_On

Flag_Pin

Kill Data On Kill EBU_On

CD_ROM_
Scrb_On

reserved

SEMA1

general purpose semaphore register

SEMA2

general purpose semaphore register

SEMA3

general purpose semaphore register

INTEN

hardware pin interrupt enable bits (map to status bits)

Status

Fl_S1

Fl_S2

Fl_S3

PLL lock

DVD rdy

Mot Ov

Tacho

reserved

MOTOR1

frequency set point

SLICE1

slice compensation value

MOTOR2

G(2 to 0)

EYE_Open

eye opening value

2001

apr

Philips Semiconductors

Preliminar

y specification

DSP f

or CD and D

VD-R

OM systems

SAA7335

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MOTOR3

FIFO set point

MTR_F

MOTO4

PWM_PDM OVF_SW

SW2

SW1

motor servo control (3 to 0)

reserved

MTR_INTG_L

motor integrator value (7 to 0)

MTR_INTG_H

motor integrator value (15 to 8)

CLOCKPRE

CL1Div

BCLKG_En Div1 (2 to 0)

Mux 2

Div2 (2 to 0)

SUB_C_STAT

ready

busy

CRC_OK

err (2 to 0)

cor fail

reserved

DECMODE

mode

reserved

read TOC

reserved

SUB_C_DATA

subcode data (7 to 0)

reserved

SUB_C_End

no meaning (register read used as a signal)

ANASET

AGC_En

gain set

gain up

gain down

AGC_On

reserved

FIFOFILL_L

number of C1 frames in FIFO

VITSET

slice ON

AdDet ON

FEndAutoS
ON

BCA_STAT

Buff_
Loaded

sync

Buff_ORun

TACHO1

tachometer multiplier frequency KTacho (7 to 0)

BCA_DATA

BCA data (7 to 0)

TACHO2

tachometer interrupt trip frequency tachometer trip (7 to 0)

reserved

TACHO3

servo control source

Tacho
FRes

Moto2_T3

Fsam

TachoInt_LF

reserved

BCASET

BCA_Freq (7 to 0)

reserved

27 to

1B to

reserved

ADDRESS

NAME

R/W

BIT

DEC

HEX

2001 apr 05

Philips Semiconductors

Preliminary specification

DSP for CD and DVD-ROM systems

SAA7335

EADING STATUS INFORMATION FROM THE

SAA7335

There are several internal status signals which can be made available on the INT line (see Table 2).

Table 2

Internal status signals; note 1

Note

1. The status signal to be output is selected by interrupt control register.

SIGNAL

DESCRIPTION

Fl_S1

change in semaphore register 1 detected

Fl_S2

change in semaphore register 2 detected

Fl_S3

change in semaphore register 3 detected

PLLlock

channel data PLL lock (not latched) indicates in-lock condition

DVDrdy

DVD header or subcode block is available, reset when SUBREADEND register is read

MotOv

motor overflow, (not latched) indicates when a motor overflow is occurring

Tacho

motor speed is higher (or lower depending on TACHO3 bit 2) than motor set point (defined in
TACHO2) this signal is not latched

Subcode data/DVD header processing

Q-

CHANNEL PROCESSING

The 96-bit Q-channel word is accumulated in an internal
buffer. Sixteen bits are used to perform a Cyclic
Redundancy Check (CRC). Subcode is available via the
V4 output and, in addition, the Q channel code can also be
read via the SUBREADDATA register.

DVD

HEADER

The DVD header processor accumulates a selection of
bytes from the beginning of the DVD sector. Two header
modes are defined, one for reading the normal sector
headers and one for filtering the disk physical format
information (from the control data block in the lead-in area)
This is controlled by the READ_TOC bit in the DECMODE
register.

THER SUBCODE CHANNELS

Data of the other subcode channels (Q-to-W) may be read
via the V4 pin, this is only valid in CD modes.

The data on the V4 pin is clocked on the WCLK edges with
a fixed delay and so may be clocked by external circuitry
running off the WCLK edges, i.e. at twice the WCLK
frequency.The subcode data is also available in the EBU
output (DOBM) in a similar format.

Crystal oscillator

The crystal oscillator is a conventional 2 pin design. This
oscillator is capable of operating with ceramic resonators

and with both fundamental and third overtone crystals.
External components should be used to suppress the
fundamental output of the third overtone crystals as shown
in Figs 3 and 4. Typical oscillation frequencies required
are 8.462, 16.9344 or 22.57 MHz depending on the
internal clock settings used and whether or not the clock
multiplier is enabled.

Error corrector

The error corrector can operate in a number of modes; CD
single-pass, CD dual-pass and DVD mode. In the CD
single-pass mode the error corrector performs 2 error
corrections per frame (C1 and C2). In the CD dual-pass
mode up to 4 symbol corrections per frame are possible
(C1-C2 then C1-C2 again). For the DVD mode full depth
PI and PO error correction is performed allowing
5 corrections per PI row and full depth (2t + e)

16 correction to be performed per PO column. The error

corrector also contains a flag controller. Flags are
assigned to symbols when the error corrector cannot
ascertain if the symbols are definitely good. C1 generates
output flags which are read (after de-interleaving) by C2,
to help in the generation of C2 output flags. The C2 output
flags are used by the interpolator for concealment of
non-correctable errors. They are also output via the EBU
signal (DOBM) and the MISC output via the I

S-bus for

CD-ROM applications.

The flags output pin CFLG provides information on the
state of all error correction and concealment flags.

2001 apr 05

Philips Semiconductors

Preliminary specification

DSP for CD and DVD-ROM systems

SAA7335

Audio functions

ONCEALMENT

A 1-sample linear interpolator becomes active if a single
sample is flagged as erroneous but cannot be corrected.
The erroneous sample is replaced by a level midway
between the preceding and following samples. Left and
right channels have independent interpolators.

If more than one consecutive non-correctable sample is
found the last good sample is held. A 1-sample linear
interpolation is then performed before the next good
sample (see Fig.5).

DAC Interface

The SAA7335 is compatible with a wide range of ROM
block decoders and Digital-to-Analog Converters DACs.
The seven main formats that are supported are given in
Table 3.

Table 3 DAC interface formats (notes 1, 2 and 3)

Notes

1. EIAJ is the abbreviation for Electronic Industries

Associated of Japan.

2. Number of BCLK periods per half WCLK period

(i.e. bits per sample).

3. Clock gating must be DISABLED for format mode 7.

MODE

BITS/WORD

FORMAT

Philips I

S-bus

EIAJ

Philips I

S-bus

EIAJ

Philips I

S-bus

EIAJ

variable

Philips I

S-bus

Fig.6 Philips I

S-bus data format 1 (16-bit word length).

handbook, full pagewidth

MGK245

D15

D14

D13

D12

D11

D10

D15

D14

BCLK

DATA

MISC

WCLK

SYNC

flag-MSB (1 is unreliable)

flag-LSB

flag-MSB

right

left

2001 apr 05

Philips Semiconductors

Preliminary specification

DSP for CD and DVD-ROM systems

SAA7335

Fig.12 Philips I

S-bus data format (variable word length).

handbook, full pagewidth

D15 D14 D13 D12 D11 D10 D9

D15 D14

BCLK

DATA

FLAG

WCLK

SYNC

flag-MSB (1 is unreliable)

flag-LSB

variable number of clocks

flag-MSB

right

MGK251

left

EBU interface

The biphase-mark digital output signal at pin DOBM is in
accordance with the format defined by the

"IEC 958"

specification.

Three different modes can be selected via the EBU output
control register (address 1010).

ORMAT

The digital audio output consists of 32-bit words
(subframes) transmitted in biphase-mark code
(2 transitions for a logic 1 and one transition for a logic 0).
Words are transmitted in blocks of 384 (see Table 4).

YNC

The sync word is formed by violation of the biphase rule
and therefore does not contain any data. Its length is
equivalent to 4 data bits. The three different sync patterns
indicate the following situations:

Sync B: start of a block (384 words), word contains left
sample

Sync M: word contains left sample (no block start)

Sync W: word contains right sample.

UDIO SAMPLE

Left and right samples are transmitted alternately.

ALIDITY FLAG

Audio samples are flagged (bit 28 = logic 1) if an error has
been detected but was non-correctable. This flag remains
the same even if data is taken after concealment.

SER DATA

Subcode bits Q-to-W from the subcode section are
transmitted via the user data bit. This data is asynchronous
with the block rate.

HANNEL STATUS

The channel status bit is the same for left and right words.
Therefore a block of 384 words contains 192 channel
status bits. The category code is always CD. The bit
assignment is given in Table 5.

2001 apr 05

Philips Semiconductors

Preliminary specification

DSP for CD and DVD-ROM systems

SAA7335

Table 4 EBU word format

Table 5 EBU channel status

WORD

BITS

FUNCTION

Sync

0 to 3

Auxiliary

4 to 7

not used; normally zero

Error flags

CFLG error and interpolation flags when bit 3 of EBU control register is set
to logic 1

Audio sample

8 to 27

first 4 bits not used (always zero)

Validity flag

valid = logic 0

User data

used for subcode data (Q-to-W)

Channel status

control bits and category code

Parity bit

even parity for bits 4 to 30

WORD

BITS

FUNCTION

Consumer/professional

always zero

Control

1 to 4

copied from bits 3 to 0 of register OUTPUT2, normally should be set to a
copy of CRC checked Q-channel control bits 0 to 3; bit 2 is logic 1 when
copy permitted; bit 3 is logic 1 when recording has pre-emphasis

Reserved

5 to 7

always zero

Category code

8 to 15

CD; bit 8 = logic 1, all other bits = logic 0

Reserved

16 to 27

always zero

Clock accuracy

28 to 29

set by OUTPUT2 control register bits 5 and 4; 00 = level II, 01 = level III

Remaining

30 to 191

always zero

Spindle motor control

The spindle motor speed is controlled by a fully integrated
digital servo. Address information from the internal

8 frame FIFO and disc speed information are used to

calculate the motor control output signals.

Several output modes are supported:

1. Pulse density, 1-line,

2. Pulse density, 2-line (true complement output) (cannot

be used with tachometer control)

3. PWM output, 2-line.

The modes are selected via the motor output configuration
register.

ULSE DENSITY MODE

In the pulse density mode the motor output (pin MOTO1)
is the pulse density modulated motor output signal. A 50%

duty cycle corresponds with the motor not actuated, higher
duty cycles mean acceleration, lower mean braking.

In this mode, the MOTO2 signal is the inverse of the
MOTO1 signal. Both signals change state only on the
edges of a internal clock signal.

Possible application diagrams are shown in Fig.13.

PWM

MODE

, 2-

LINE

In the PWM mode the motor acceleration signal is put in
pulse-width modulation form on the MOTO1 output and
the motor braking signal is pulse-width modulated on the
MOTO2 output.

Figure 14 illustrates the PWM mode timing and Fig.15
illustrates a typical PWM mode application diagram.

2001 apr 05

Philips Semiconductors

Preliminary specification

DSP for CD and DVD-ROM systems

SAA7335

Flags output (CFLG) (open-drain output)

A 1-bit flag signal is available at the CFLG pin, this contains 11 bits running off the ADCCLK, each bit period is 7 ADCCLK
periods. This signal shows the status of the error corrector and interpolator and is updated every frame.

Table 6 Definition of flag bits

Notes

1. For DVD mode read PI for C1 and PO for C2.

2. This flag refers to the previous correction frame.

3. This flag refers to the previous correction frame (is not valid i.e. always logic 0 in DVD mode).

4. Bit order of root count is 9, then 6 to 8 for root count (3 to 0).

BSOLUTE TIME SYNC

The sync signal is the absolute time sync signal. In the CD mode it is the FIFO-passed subcode sync and relates the
position of the subcode sync to the audio data (DAC output). In the DVD mode it indicates the start of a new sector
header.

The flag may be used for special purposes such as synchronization of different players.

BIT

NUMBER

VALUE

DESCRIPTION

START bit

1 to 3

000

C1 first or C1 last; note 1

001

C2 first, CD mode reserved, DVD mode; note 1

010

reserved; note 1

011

C2 last; note 1

100

corrector not active; note 1

all others reserved

core fail

failure flag set because correction impossible; note 2

flag fail; note 3

9, 6 to 8

root count (3 to 0)

this indicates the number of errors corrected; note 4

STOP bit

Fig.16 Flags output format.

handbook, halfpage

START

bit

data bits

pause

MGK252

2001 apr 05

Philips Semiconductors

Preliminary specification

DSP for CD and DVD-ROM systems

SAA7335

LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).

Notes

1. This maximum value has an absolute maximum of 6.5 V independent of the supply voltage.

2. The human body model ESD simulation is equivalent to discharging a 100 pF capacitor via a 1.5 k

resistor, which

produces a single discharge transient. Reference

"Philips Semiconductors Test Method UZW-BO/FQ-A302 (similar

to MIL-STD 883C method 3015.7)".

3. The machine model ESD simulation is equivalent to discharging a 200 pF capacitor via a resistor and series inductor

with effective dynamic values of 25

and 2.5

H, which produces a damped oscillating discharge. Reference

"Philips Semiconductors Test Method UZW-BO/FQ-B302 (similar to EIAJ IC-121 Test Method 20 condition C)".

QUALITY

This device will meet the requirements of the

"Philips Semiconductors General Quality Specification UZW-BO/FQ-0601"

in accordance with

"Quality Reference Handbook (order number 9397 750 00192)". This details the acceptance criteria

for all Q & R tests applied to the product.

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

DDD

digital supply voltage

0.3

+6.5

DDA

analog supply voltage

0.3

+6.5

i(max)

maximum input voltage (any input)

note 1

0.3

+ 0.5

o(max)

maximum output voltage (any output)

note 1

+ 0.5

o(max)

maximum output current (each output)

amb

operating ambient temperature

+70

stg

storage temperature

+125

ESD

electrostatic handling

human body model

note 2

2000

+2000

machine model

note 3

200

+200

2001 apr 05

Philips Semiconductors

Preliminary specification

DSP for CD and DVD-ROM systems

SAA7335

DC CHARACTERISTICS
V

DDD

= V

DDA

= 5 to 5.5 V; V

SSD

= V

SSA

= 0 V; T

amb

20 to +70

C; unless otherwise specified.

Note

1. These inputs are analog, V

and V

values are quoted as a guide for digital RGB users.

AC CHARACTERISTICS
V

DDD

= V

DDA

= 4.5 to 5.5 V; V

SSD

= V

SSA

= 0 V; T

amb

20 to +70

C; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies

DDD

digital supply voltage

4.5

5.5

DDA

analog supply voltage

4.5

5.5

DD(tot)

total supply current

at 25 MHz clock

Inputs

IGITAL INPUTS

(TTL

LEVEL

); note 1

LOW-level input voltage

0.8

HIGH-level input voltage

2.0

LOW-level output voltage

0.8

HIGH-level output voltage

2.4

NALOG INPUTS

I(max)(p-p)

maximum input voltage
(peak-to-peak value)

I(nom)(p-p)

nominal input voltage
(peak-to-peak value)

dynamic range

3 dB bandwidth

0 to 12 dB gain

MHz

12 to 20 dB gain

MHz

I(AGC)

AGC input current

I(ADC)

ADC input current

I(buf)

output buffer input current

I(tot)

total input current

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies

DDD

digital supply voltage

4.5

5.0

5.5

DDD

digital supply current

DDD

= 5 V

165

DDA

analog supply voltage

4.5

5.0

5.5

DDA

analog supply current

DDA

= 5 V

165

2001 apr 05

Philips Semiconductors

Preliminary specification

DSP for CD and DVD-ROM systems

SAA7335

Analog front-end (V

DDA

= 4.5 to 5.5 V); HFIN

chan

channel frequency

MHz

Digital inputs

LOW-level input voltage

0.8

HIGH-level input voltage

2.0

input leakage current

= 0 to V

DDD

+10

input capacitance

Open-drain output; pin INT

LOW-level output voltage

= 1 mA

0.4

LOW-level output current

load capacitance

o(f)

output fall time

= 20 pF; note 1

3-state outputs

LOW-level output voltage

= 0 mA

0.4

HIGH-level output voltage

8 mA

2.4

load capacitance

o(r)

output rise time

= 20 pF; note 1

o(f)

output fall time

= 20 pF; note 1

LI(Z)

3-state leakage current

= 0 to V

DDD

+10

3-state outputs; pins MOTO1, MOTO2 and DOBM

LOW-level output voltage

DDD

= 4.5 to 5.5 V;

= 10 mA

0.8

HIGH-level output voltage

DDD

= 4.5 to 5.5 V;

10 mA

+2.4

load capacitance

o(r)

output rise time

= 20 pF; note 1

o(f)

output fall time

= 20 pF; note 1

LI(Z)

3-state leakage current

= 0 to V

DDD

+10

Digital input/outputs (V

DDD

= 4.5 to 5.5 V)

NPUT

OUTPUT

: SDA (

INPUT

OPEN

DRAIN

C-

BUS OUTPUT

)

LOW-level input voltage

1.5

HIGH-level input voltage

3.0

LOW-level output voltage

= 2 mA;

sink

= 3 mA

0.4

LOW-level output current

SDA

serial data line capacitance

SCL

serial clock line capacitance

marL

LOW-level noise margin

0.1V

DDD

marH

HIGH-level noise margin

0.2V

DDD

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2001 apr 05

Philips Semiconductors

Preliminary specification

DSP for CD and DVD-ROM systems

SAA7335

series resistance on the SDA and
SCL lines

300

bus(max)

maximum bus capacitance

per wire

400

NPUT

: SCL (CMOS

INPUT

)

LOW-level input voltage

0.3

0.3V

DDD

HIGH-level input voltage

0.7V

DDD

+ 0.3 V

input leakage current

= 0

DDD

+10

input capacitance

Crystal oscillator input CRIN (external clock)

mutual conductance at start-up

output resistance at start-up

input capacitance

input leakage current

+10

Crystal oscillator output CROUT (see Figs 3 and 4)

xtal

crystal frequency

MHz

feedback capacitance

output capacitance

S-bus timing

LOCK OUTPUT

SCLK (see Fig.17)

output clock period

set by CLKPRE1
register

472.4

SCLKH

clock HIGH time

SCLKL

clock LOW time

su(SCLK)

set-up time

tbf

h(SCLK)

hold time

tbf

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2001 apr 05

Philips Semiconductors

Preliminary specification

DSP for CD and DVD-ROM systems

SAA7335

Notes

1. Timing reference voltage levels are 0.8 V and V

DDD

0.8 V.

2. Negative set-up time means that data may change after clock transition.

External RAM timing (see Figs 18 and 20)

AV-DV

address valid to data valid

tbf

OE-DV

output enable to data valid

tbf

W(W)

write pulse width

tbf

su(A)

address set-up before start of write

tbf

h(A)

address hold after end of write

tbf

su(D-EW)

data set-up to end of write

tbf

h(D-EW)

data hold after end of write

tbf

OE-DA

output enable to data active

tbf

OD-DI

output disable to data inactive

tbf

Microcontroller interface timing (see Figs 18 and 20)

NPUT

ALE

su(A-ALE)

address set-up before ALE LOW

h(A-ALE)

address hold after ALE LOW

ALEL

input LOW time

ADC

CLK + 15

ALEH

input HIGH time

ADC

CLK + 15

d(ALEL-WRL)

delay time ALE LOW to WR LOW

rise time

fall time

240

NPUTS

I AND

IL(R/W)

input LOW time

ADC

CLK + 15

IH(R/W)

input HIGH time

ADC

CLK + 15

rise time

fall time

240

EAD MODE

d(RLDV)

delay time RD LOW to DA0 to DA7
valid

ADC

CLK + 35

d(RHDX)

delay time RD HIGH to DA0 to DA7
high-impedance

RITE MODE

su(QVWX)

set-up time WR LOW to
DA0 to DA7

h(WHQX)

hold time WR HIGH to DA0 to DA7
3-state

ADC

CLK + 25

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2001 apr 05

Philips Semiconductors

Preliminary specification

DSP for CD and DVD-ROM systems

SAA7335

SOLDERING

Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"IC Package Databook" (order code 9398 652 90011).

Reflow soldering

Reflow soldering techniques are suitable for all LQFP
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45

Wave soldering

Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following
conditions must be observed:

A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.

The footprint must be at an angle of 45

to the board

direction and must incorporate solder thieves
downstream and at the side corners.

Even with these conditions, do not consider wave
soldering LQFP packages LQFP48 (SOT313-2),
LQFP64 (SOT314-2) or LQFP80 (SOT315-1).

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260

C, and

maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150

C within

6 seconds. Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300

C. When

using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320

2001 apr 05

Philips Semiconductors

Preliminary specification

DSP for CD and DVD-ROM systems

SAA7335

DATA SHEET STATUS

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was

published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

DATA SHEET STATUS

(1)

PRODUCT

STATUS

(2)

DEFINITIONS

Objective data

Development

This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.

Preliminary data

Qualification

This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.

Product data

Production

This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.

DEFINITIONS

Short-form specification

The data in a short-form

specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition

Limiting values given are in

accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.

Application information

Applications that are

described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.

DISCLAIMERS

Life support applications

These products are not

designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes

Philips Semiconductors

reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.

ICs with MPEG-2 functionality

Use of this product in

any manner that complies with the MPEG-2 Standard is
expressly prohibited without a license under applicable
patents in the MPEG-2 patent portfolio, which license is
available from MPEG LA, L.L.C., 250 Steele Street, Suite
300, Denver, Colorado 80206.

SCA

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

2001

Philips Semiconductors a worldwide company

For all other countries apply to: Philips Semiconductors,
Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN,
The Netherlands, Fax. +31 40 27 24825

Argentina: see South America

Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,
Tel. +61 2 9704 8141, Fax. +61 2 9704 8139

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
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220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773

Belgium: see The Netherlands

Brazil: see South America

Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
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Tel. +359 2 68 9211, Fax. +359 2 68 9102

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China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
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Colombia: see South America

Czech Republic: see Austria

Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,
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Finland: Sinikalliontie 3, FIN-02630 ESPOO,
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Middle East: see Italy

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Tel. +31 40 27 82785, Fax. +31 40 27 88399

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Tel. +64 9 849 4160, Fax. +64 9 849 7811

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Tel. +47 22 74 8000, Fax. +47 22 74 8341

Pakistan: see Singapore

Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

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Tel. +7 095 755 6918, Fax. +7 095 755 6919

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Tel. +65 350 2538, Fax. +65 251 6500

Slovakia: see Austria

Slovenia: see Italy

South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. +27 11 471 5401, Fax. +27 11 471 5398

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04547-130 SÃO PAULO, SP, Brazil,
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Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263

Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2451, Fax. +886 2 2134 2874

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60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260,
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ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087

Uruguay: see South America

Vietnam: see Singapore

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Tel. +381 11 3341 299, Fax.+381 11 3342 553

Printed in The Netherlands

753503/02/pp

Date of release:

2001 apr 05

Document order number:

9397 750 08202

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SAA7335HL/M1