July 1994

Philips Semiconductors

Preliminary specification

Shock absorbing RAM addresser

SAA7346

FEATURES

Absorbs shocks from x, y and z directions

Absorbs rotational shocks

Absorbs multiple shocks per second

Interfaces directly to compact disc decoders SAA7345,
SAA7347 and SAA7370

Multi-speed I

S-bus input with single-speed

S-bus output

Controls 1 or 4 MBit of external Dynamic Random
Access Memory (DRAM)

Easy serial interface for communication with common
microcontrollers

Software selectable shock detectors

By-pass/power-down mode

Kill interface for DAC deactivation

Can be used for:

`sampling' part of a disc

to reduce access pauses between jumps

to deliver a programmable delay

to generate a fixed audio rate from Constant Angular

Velocity (CAV) discs.

GENERAL DESCRIPTION

The SAA7346 can be used to make a CD player
insensitive to shocks. To do this, SAA7346 operates
closely with a standard 1 Mbit or 4 Mbit DRAM. Audio data
is stored inside the DRAM and during shocks the data of
the DRAM can be played. The SAA7346 functions as a
customized DRAM controller with serial I/O and on-board
shock detectors.

QUICK REFERENCE DATA

ORDERING INFORMATION

Note

1. When using reflow soldering it is recommended that the Dry Packing instructions in the

"Quality Reference

Pocketbook" are followed. The pocketbook can be ordered using the code 9398 510 34011.

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

supply voltage

3.3

5.0

5.5

supply current

clk

clock frequency

16.9344

MHz

i(clk)

S input word clock frequency

44.1

88.2

176.4

kHz

o(clk)

S output word clock frequency

44.1

88.2

176.4

kHz

amb

operating ambient temperature

+85

stg

storage temperature

+150

TYPE NUMBER

PACKAGE

PINS

PIN POSITION

MATERIAL

CODE

SAA7346H

QFP

(1)

plastic

SOT307-2

July 1994

Philips Semiconductors

Preliminary specification

Shock absorbing RAM addresser

SAA7346

PINNING

SYMBOL

PIN

DESCRIPTION

CFLG

correction flag input from CD decoder

KILL

kill input

SCLI

multi-speed I

S bit clock input

WCI

multi-speed I

S word clock input

SDI

multi-speed I

S data input

CONFIG

external DRAM select input; HIGH 4 Mbit, LOW 1 Mbit

CLKIN

16.9344 MHz system clock input

TMS

test mode select input; active HIGH

OTD

on/off track detector input

RCD2

DRAM read cycle divide-by-2 input; active HIGH

SSD

shock detected output; active HIGH when shock is detected

RSB

rotational shock busy output; active HIGH when rotational shock is detected

S_NSF

synthetic new subcode frame output

RESET

reset enable input; active LOW

SIDA

microcontroller interface input/output data line

SICL

microcontroller interface clock input

SILD

microcontroller interface read/write input

FILL

FIFO write enable output; active HIGH

KILLOUT

open drain output; active LOW; when in by-pass mode KILLOUT equals KILL

SDO

S data output

SCLO

S bit clock output

WCO

S word clock output

DD1

supply voltage 1

SS1

supply ground 1

DRAM address bus output 4

DRAM address bus output 3

DRAM address bus output 5

DRAM address bus output 2

DRAM address bus output 6

DRAM address bus output 1

DRAM address bus output 7

DRAM address bus output 0

DRAM address bus output 8

DRAM address bus output 9

DRAM enable output; active LOW

RAS

DRAM row address strobe output; active LOW

CAS

DRAM column address strobe output; active LOW

DRAM write enable output; active LOW

July 1994

Philips Semiconductors

Preliminary specification

Shock absorbing RAM addresser

SAA7346

D3 to D0

39 to 42

DRAM data bus inputs/outputs

SS2

supply ground 2

DD2

supply voltage 2

SYMBOL

PIN

DESCRIPTION

Fig.2 Pin configuration.

handbook, full pagewidth

MGB430

CFLG

RCD2

KILL

SCLI

WCI

SDI

CONFIG

CLKIN

TMS

OTD

SS1

SAA7346

WCO

S_NSF

RESET

SIDA

SICL

SILD

FILL

KILLOUT

SCLO

SDO

RSB

DD2

SS2

SSD

DD1

CAS

RAS

FUNCTIONAL DESCRIPTION

S input/output interfaces

The SAA7346 contains an asynchronous serial input and
a serial output interface. The serial operation of the
interfaces is under hardware control of the external
circuitry and uses the I

S protocol. The output presents a

continuous clock signal SCLO (typically 2.8224 MHz)
which is divided from the system clock, and a word select
signal WCO, typically 44.1 kHz (f

), which is used to

distinguish between right and left channels. When in
by-pass mode WCO and SCLO are the same as the input
interface signals WCI and SCLI, enabling data to pass
through the SAA7346. Since the serial input port is
asynchronous the device is independent of the CD

decoder clock speed and enables the word clock to vary
from 1.1

to 4

(typically 2

). This is a requirement

of any electronic shock absorbing system since the disc
must be rotating faster than usual to assure the FIFO is full
to absorb a shock. The falling edge of WCO indicates the
start of a new transfer. Data is exchanged over the
SDI and SDO pins. The SAA7346 is compatible with a
variety of DAC ICs.

New subcode frame regeneration

The SAA7346 has a digital phase-locked loop (PLL)
system which decodes the F1 and F6 flags, from the first
1-bit signal generated by the CD decoder correction flag
output shown in Fig.3. The F1 flag is the absolute time
sync signal of the New Subcode Frame (NSF). It relates

July 1994

Philips Semiconductors

Preliminary specification

Shock absorbing RAM addresser

SAA7346

the position of the subcode-sync to the audio data. This
signal determines the accuracy with which the SAA7346
sews audio data together after a shock. When the CD
decoder preforms a jump the NSF will be missed. The PLL
system will insert the missing pulse. The resulting signal is
the S_NSF which can be used as a time out for reading the

subcode from the decoder shown in Fig.4. The S_NSF is
available externally and the NSF flag can be read via the
serial microcontroller interface. The F6 flag indicates at
least one hold has occurred in the decoder's error
corrector and interpolator. The shock processor uses this
signal to evaluate whether a shock has occurred.

handbook, full pagewidth

11.3

45.4

MGA370

CFLG

Fig.3 CFLG input timing diagram.

handbook, full pagewidth

Variable

NSF is set until read

by the microcontroller

0.37 ms

6.6 ms

S_NSF

NSF

MGB431

Fig.4 S_NSF output timing diagram; n = 2.

Shock processor

The shock processor determines whether a shock has
occurred by processing all the shock detectors. The
SAA7346 will enter shock mode and set SSD when the:

· µ

Csd flag is set by the microcontroller in the command

OTD input is active while the jmp_bz flag is not set

RSB output is set while the e_rot_sd flag is set

NSF pulse is lost and the full flag is not read by the
microcontroller from the status register.

When the target position has been found the
microcontroller should set the PFB flag in the command
register. The SAA7346 will respond by clearing the SSD
flag and start refilling. If CFLG still indicates a hold, the

decoder is rolling out of its FIFO. RSB will be set which
sets SSD again thus the FIFO will not start refilling. The
microcontroller should jump one track back and look for
the correct target position again. When the motor speed is
stable and the decoder does not roll out of its FIFO, the
audio data will be glued together.

SSD will be reset whenever the microcontroller sets PFB
or the flush flags in the command register, or when the
FIFO empties while the echo flag is LOW. Note if the
microcontroller wants SSD to be clear for a while the shock
detectors should be inhibited.

FIFO controller and monitor

The SAA7346 uses a state machine to control and monitor
the conditions of the FIFO shown in Fig.5.

July 1994

Philips Semiconductors

Preliminary specification

Shock absorbing RAM addresser

SAA7346

Fig.5 State machine flow diagram.

handbook, full pagewidth

SHOCK

HOLD

first nibble

FILL

SSD

NSF +

S_NSF

SSD

RESET

reset and sow

flush + reset

flush + reset +

(empty and echo)

HOLD

first nibble

full

SSD

PFB

flush + reset

SSD and

(NSF + S_NSF)

MGB432

During normal operation the FIFO will fill up because
writing is carried out twice as fast as reading; this is the fill
mode. If the FIFO is full the monitor will detect and set the
full flag. At the same time the fill flag will be reset thus
preventing audio data from being written in to the FIFO.
When the microcontroller reads the full flag from the status
register, the servo control should jump back one track. The
microcontroller enters a wait loop until the same absolute
time subcode frame turns by again; this is the hold mode.
When the spot is found again the microcontroller should
set the PFB flag in the command register and the
SAA7346 will resume writing to the DRAM. While in fill
mode the write pointer address is saved at the end of each
subcode frame. When the player exists hold mode it
restores the saved address and continues writing after the
last sample.

When a shock is detected the SAA7346 will enter shock
mode. The shock mode will last until the PFB is set by the
microcontroller or the FIFO is flushed, reset or runs empty.

Microcontroller interface

The SAA7346 has a 3-line microcontroller interface which
is compatible with TDA1301, TDA1303 and SAA7345.

RITING DATA TO THE

SAA7346

The SAA7346 command register is shown in Table 1. This
can be written to via the microcontroller interface as shown
in Fig.6. The command register flags functions are shown
in Table 2.

Table 1

SAA7346 microcontroller interface registers.

REGISTER

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Command

flush

bypass

echo

jmp_bz

otd_p

e_rot_sd

Csd

PFB

Status

Lm1

FRM_ER

NSF

full

empty

SSD

fill

July 1994

Philips Semiconductors

Preliminary specification

Shock absorbing RAM addresser

SAA7346

Table 2

Command register flag functions.

COMMAND

DESCRIPTION

Flush

Flush, when set, will empty the FIFO, reset the read and write pointer addresses. Then writing will
resume to the FIFO. Flag reset automatically.

Bypass

Bypass, when set, will power down the SAA7346. The I

S interface passes input to output directly.

The parallel interface port controls RAS, CAS, WE and OE which are pulled HIGH. KILL passes
directly to KILLOUT. When exiting by-pass mode the FIFO is automatically flushed.

Echo

Echo, when set, will cause the FIFO contents to be continuously played until the correct position is
found again.

jmp_bz

Jump busy, when set, indicates a jump is being preformed. The OTD shock detector input will be
disabled. After the jump has finished the flag should be reset by a write.

otd_p

OTD polarity enable. Enables the polarity of the OTD input to be switched from active HIGH set,
active LOW not set.

e_rot_sd

Enable rotational shock detection, when set, will detect shocks whenever the decoder rolls out of its
internal FIFO.

Csd

Microcontroller shock detected is set when the microcontroller has detected a shock.

PFB

Position Found Back, when set, indicates that the microcontroller has found the absolute time frame
after a shock or hold cycle. The audio data will sew together and the flag reset automatically.

Fig.6 Microcontroller WRITE timing.

handbook, full pagewidth

SICL

SILD

SIDA

MGB433

Writing operation sequence:

SILD is held HIGH by the microcontroller.

Microcontroller data is clocked into the internal
command register on the LOW-to-HIGH clock transition
of SICL.

SILD is pulled LOW by the microcontroller to latch-in
data to the command register.

SICL and SILD are pulled HIGH by the microcontroller
to indicate that communications have finished.

EADING STATUS OF

SAA7346

The SAA7346 has a status register shown in Table 1. This
can be read via the microcontroller interface shown in
Fig.7. The internal status signals are made available on
the SIDA pin and are shown in Table 3.

July 1994

Philips Semiconductors

Preliminary specification

Shock absorbing RAM addresser

SAA7346

Table 3

Internal status signals.

Table 4

FIFO length as a function of CONFIG, Lm and Lm1.

STATUS

DESCRIPTION

Lm and Lm1

The two Most Significant Bits (MSB) of the FIFO. These can be used to display the FIFO length or
correct the subcode time information. The FIFO length is shown in Table 4.

FRM_ER

Framing error flag is set when:

1. The microcontroller did not accept the previous subcode flag on time. When this occurs the NSF

flag will be set together with FRM_ER.

2. The S_NSF generated signal does not coincide with the NSF signal generated by the decoder.

When this occurs there has been a FIFO overflow in the decoder or a jump.

Framing error flag is reset when status register is read.

NSF

New subcode frame is set when an absolute sync is recovered from the CFLG input. Reset when
status register is read. If the NSF is still set at the next occurrence of a subcode frame, FRM_ER will
be set indicating that the microcontroller has lost a frame.

Full

Full is set when the FIFO is full. When the flag is set the microcontroller must jump back to the
previous track. Reset when status register is read.

Empty

Empty is set when the FIFO is emptied during hold or shock modes. DRAM writing should resume
immediately unless echo is set in the command register. If set, writing can only resume when PFB or
flush are set in the command register. The latter will cause a discontinuity in music. Note when set
there is a complete word left in the FIFO giving the SAA7346 controller time to switch to fill mode.

SSD

Set shock detect is set when SAA7346 detects a shock.

Fill

Fill is set when writing data to the DRAM or by setting the command register flags PFB or flush. Reset
internally when full or SSD are set.

CONFIG

Lm1

FIFO LENGTH (s)

0.00 to 0.19

0.19 to 0.39

0.39 to 0.58

0.58 to 0.78

0.00 to 0.75

0.75 to 1.50

1.50 to 2.25

2.25 to 2.97

Fig.7 Microcontroller READ timing.

handbook, full pagewidth

SICL

SILD

SIDA

MGB434

July 1994

Philips Semiconductors

Preliminary specification

Shock absorbing RAM addresser

SAA7346

Read operation sequence:

SILD is held LOW by the microcontroller.

Status information is clocked from the internal status
register on the LOW-to-HIGH clock transition of SICL.

SICL and SILD are pulled HIGH by the microcontroller
to indicate that communications have finished.

DRAM interface

The SAA7346 may be connected to all standard 80 ns,
1M

4 bit or 256K

4 bit fast page mode DRAMs. The

best performance can be expected with the 4 Mbit DRAM.
The CONFIG input selects the DRAM configuration either
HIGH 4 Mbit or LOW 1 Mbit format. The SAA7346
converts audio data from serial to parallel and stores it as
4 bits. The addresses for read or write actions are
calculated by separate read and write pointers which are
multiplexed onto a 4 bits address bus. The control signal
outputs associated with the parallel inputs/outputs are
shown in Table 5.

Table 5

Command register flag functions.

When the SAA7346 leaves bypass mode where all parallel
Port control lines are pulled HIGH, the device initiates a
DRAM power-up routine in accordance with the JEDEC
standard.

COMMAND

DESCRIPTION

indicates write enable action

RAS

row address strobe

CAS

column address strobe

output buffer enable for external memory
during cycle.

System clock

The system clock input, CLKIN, recommended input signal
is 16.9344 MHz. The accuracy of this clock influences the
accuracy of the I

S output, therefore the performance of

the DAC and hence audio quality. The system clock is
divided by 384 to derive the I

S output word clock, WCO

divided by 8 to derive the I

S output bit clock, SCLO.

Therefore whatever clock jitter the user introduces on the
CLKIN signal will be reflected in the WCO and SCLO
outputs.

Reset

Reset should be applied for four system clock cycles.
Reset will:

Clear SSD

Clear the command register but leave the bypass flag
set.

After a reset has been applied the SAA7346 will start-up in
bypass mode.

Kill interface

The kill interface can be used to deactivate the DAC. The
kill input is passed directly to the KILLOUT output when the
bypass flag in the command register is set. When the flag
is not set KILLOUT is generated by the SAA7346. It is
LOW after leaving bypass mode, a reset or a FIFO flush. It
will be LOW until the first error free word is read from the
FIFO. The kill input has no effect or function when the
bypass flag is not set.

Read cycle divide (RCD2)

The RCD2 input enables the modes of operation shown in
Table 6. When RCD2 is HIGH the DRAM-read requests
are halved allowing I

S output speeds to vary. The factor

n is called the over-speed factor.

July 1994

Philips Semiconductors

Preliminary specification

Shock absorbing RAM addresser

SAA7346

Table 6

SAA7346 I

S output speeds.

Notes

1. CAV with n = 4 speed at outer edge of disc; n = 1.5 at inner edge of disc.

2. To build-up a delay, RCD2 should be made HIGH temporarily for twice the delay time.

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

THERMAL CHARACTERISTICS

CHARACTERISTICS

= 3.3 to 5.5 V; V

= 0 V; T

amb

40 to +85

C; unless otherwise specified.

RCD2

S INPUT

SPEED

S OUTPUT

SPEED

APPLICATION

LOW

CAV

(1)

n = 1

CAV CDROM player with standard audio speed

LOW

(2)

n = 1

delay line feature

LOW

n = 2

n = 1

shock proof CD player

LOW

n = 4

n = 1

high data rate CDROM/CDI player with standard audio speed

HIGH

n = 2

n =

musicians feature

HIGH

n = 4

n =

musicians feature

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

supply voltage

6.5

max

maximum power dissipation

500

stg

storage temperature

+125

amb

operating ambient temperature

+85

SYMBOL

PARAMETER

VALUE

UNIT

th j-a

thermal resistance from junction to ambient in free air

K/W

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply

supply voltage

3.3

5.0

5.5

supply current

= 5.0 V

DDb

bypass supply current

= 5.0 V;

bypass mode

DDq

quiescent supply current

100

Digital inputs

NPUTS

: WCI, SDI, CLKIN, OTD

AND

RCD2;

NORMAL

CMOS

LOW level input voltage

0.3

0.3V

HIGH level input voltage

0.7V

+ 0.3 V

input leakage current

= 0 V to V

+10

input capacitance

July 1994

Philips Semiconductors

Preliminary specification

Shock absorbing RAM addresser

SAA7346

NPUT

CLKIN

clk

system clock frequency

16.9344

MHz

system clock HIGH time

system clock rise time

0.8 V to (V

0.8 V)

system clock fall time

0.8 V) to 0.8 V

NPUTS

: CFLG, KILL, CONFIG

AND

SILD;

WITH PULL

LOW level input voltage

0.3

0.3V

HIGH level input voltage

0.7V

+ 0.3 V

input pull-up resistance

= 0 V

input capacitance

NPUT

TMS;

WITH PULL

DOWN

LOW level input voltage

0.3

0.3V

HIGH level input voltage

0.7V

+ 0.3 V

input pull-down resistance

= V

input capacitance

NPUTS

: RESET, SCLI

AND

SICL; S

CHMITT

TRIGGER

thr

switching threshold voltage rising

0.8V

thf

switching threshold voltage falling

0.2V

hys

hysteresis voltage

0.33V

input capacitance

NPUT

RESET

RESET pulse width; active LOW

236

Digital outputs

UTPUTS

: FILL, S_NSF, RSB

AND

SSD;

PUSH

PULL

LOW level output voltage

= 4 mA

0.4

HIGH level output voltage

4 mA

0.4

load capacitance

output rise time

0.8 V to (V

0.8 V);

= 50 pF

output fall time

0.8 V) to 0.8 V;

= 50 pF

UTPUTS

: SDO, SCLO, WCO, WE, OE, RAS, CAS, A0

A9;

SLEW RATE PUSH

PULL

LOW level output voltage

= 4 mA

0.4

HIGH level output voltage

4 mA

0.4

load capacitance

output rise time

0.8 V to (V

0.8 V);

= 50 pF

output fall time

0.8 V) to 0.8 V;

= 50 pF

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

July 1994

Philips Semiconductors

Preliminary specification

Shock absorbing RAM addresser

SAA7346

UTPUT

KILLOUT;

OPEN DRAIN

LOW level output voltage

= 2 mA

0.4

output current

load capacitance

output fall time

0.8 V) to 0.8 V;

= 50 pF

NPUTS

OUTPUTS

: D0

D3;

NORMAL

CMOS

WITH SLEW RATE CONTROLLED PUSH

PULL

LOW level input voltage

0.3

0.3V

HIGH level input voltage

0.7V

+ 0.3 V

input leakage current

= 0 V to V

+10

input capacitance

LOW level output voltage

= 4 mA

0.4

HIGH level output voltage

4 mA

0.4

load capacitance

output rise time

0.8 V to (V

0.8 V);

= 50 pF

output fall time

0.8 V) to 0.8 V;

= 50 pF

NPUT

OUTPUT

SIDA;

NORMAL

CMOS

WITH PUSH

PULL

LOW level input voltage

0.3

0.3V

HIGH level input voltage

0.7V

+ 0.3 V

input leakage current

= 0 V to V

+10

input capacitance

LOW level output voltage

= 4 mA

0.4

HIGH level output voltage

4 mA

0.4

load capacitance

output rise time

0.8 V to (V

0.8 V);

= 50 pF

output fall time

0.8 V) to 0.8 V;

= 50 pF

S timing

ECEIVER

(

SEE

.9)

Clock input SCLI

clock cycle time

118.1

(1)

236.2

(2)

472.4

(3)

clock HIGH time

41.3

(1)

clock LOW time

41.3

(1)

Inputs: SDI and WCI

set-up time

23.6

hold time

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

July 1994

Philips Semiconductors

Preliminary specification

Shock absorbing RAM addresser

SAA7346

Notes

1. n = 4.

2. n = 2.

3. n = 1.

4. n =

DRAM interface timing (see Figs 14 and 15)

read or write cycle time

160

CAC

access time from CAS

OAC

access time from OE

OE to data input hold time

RAS HIGH time

RAS LOW time

10000

RAS hold time

RAS hold time to OE LOW

CAS LOW time

10000

CAS hold time

CRd

delay time from CAS HIGH to RAS

RCd

delay time from RAS to CAS

RAS to column address delay time

su1

row address set-up time

RAh

row address hold time

su2

column address set-up time

CAh

column address hold time

column address hold time from RAS
LOW

column address to RAS lead time

RCh

read command hold time

RRh

read command hold time to RAS

Wsu

write command set-up time

Wh1

write command hold time

write command LOW time

Wh2

write command hold time from RAS

WCl

write command to CAS lead time

WRl

write command to RAS lead time

Dsu

data output set-up time

data output hold time

DRh

data output hold time from RAS

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

July 1994

Philips Semiconductors

Preliminary specification

Shock absorbing RAM addresser

SAA7346

SOLDERING

Plastic quad flat-packs

Y WAVE

During placement and before soldering, the component
must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.

Maximum permissible solder temperature is 260

C, and

maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150

C within 6 s.

Typical dwell time is 4 s at 250

A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.

Y SOLDER PASTE REFLOW

Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be

applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45

EPAIRING SOLDERED JOINTS

(

BY HAND

HELD SOLDERING

IRON OR PULSE

HEATED SOLDER TOOL

)

Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300

C. When using proper tools, all other pins can be

soldered in one operation within 2 to 5 s at between 270
and 320

C. (Pulse-heated soldering is not recommended

for SO packages.)

For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Philips Semiconductors

Philips Semiconductors a worldwide company

Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428)

BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. (02)805 4455, Fax. (02)805 4466

Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213,

Tel. (01)60 101-1236, Fax. (01)60 101-1211

Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands,

Tel. (31)40 783 749, Fax. (31)40 788 399

Brazil: Rua do Rocio 220 - 5

floor, Suite 51,

CEP: 04552-903-SÃO PAULO-SP, Brazil.
P.O. Box 7383 (01064-970).
Tel. (011)821-2327, Fax. (011)829-1849

Canada: INTEGRATED CIRCUITS:

Tel. (800)234-7381, Fax. (708)296-8556
DISCRETE SEMICONDUCTORS: 601 Milner Ave,
SCARBOROUGH, ONTARIO, M1B 1M8,
Tel. (0416)292 5161 ext. 2336, Fax. (0416)292 4477

Chile: Av. Santa Maria 0760, SANTIAGO,

Tel. (02)773 816, Fax. (02)777 6730

Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17,

77621 BOGOTA, Tel. (571)249 7624/(571)217 4609,
Fax. (571)217 4549

Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. (032)88 2636, Fax. (031)57 1949

Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. (9)0-50261, Fax. (9)0-520971

France: 4 Rue du Port-aux-Vins, BP317,

92156 SURESNES Cedex,
Tel. (01)4099 6161, Fax. (01)4099 6427

Germany: PHILIPS COMPONENTS UB der Philips G.m.b.H.,

P.O. Box 10 63 23, 20043 HAMBURG,
Tel. (040)3296-0, Fax. (040)3296 213.

Greece: No. 15, 25th March Street, GR 17778 TAVROS,

Tel. (01)4894 339/4894 911, Fax. (01)4814 240

Hong Kong: PHILIPS HONG KONG Ltd., Components Div.,

6/F Philips Ind. Bldg., 24-28 Kung Yip St., KWAI CHUNG, N.T.,
Tel. (852)424 5121, Fax. (852)428 6729

India: Philips INDIA Ltd, Components Dept,

Shivsagar Estate, A Block ,
Dr. Annie Besant Rd. Worli, Bombay 400 018
Tel. (022)4938 541, Fax. (022)4938 722

Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4,

P.O. Box 4252, JAKARTA 12950,
Tel. (021)5201 122, Fax. (021)5205 189

Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. (01)640 000, Fax. (01)640 200

Italy: PHILIPS COMPONENTS S.r.l.,

Viale F. Testi, 327, 20162 MILANO,
Tel. (02)6752.3302, Fax. (02)6752 3300.

Japan: Philips Bldg 13-37, Kohnan 2 -chome, Minato-ku, TOKYO 108,

Tel. (03)3740 5028, Fax. (03)3740 0580

Korea: (Republic of) Philips House, 260-199 Itaewon-dong,

Yongsan-ku, SEOUL, Tel. (02)794-5011, Fax. (02)798-8022

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA,

SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880

Mexico: Philips Components, 5900 Gateway East, Suite 200,

EL PASO, TX 79905, Tel. 9-5(800)234-7381, Fax. (708)296-8556

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB

Tel. (040)783749, Fax. (040)788399

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. (09)849-4160, Fax. (09)849-7811

Norway: Box 1, Manglerud 0612, OSLO,

Tel. (022)74 8000, Fax. (022)74 8341

Pakistan: Philips Electrical Industries of Pakistan Ltd.,

Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton,
KARACHI 75600, Tel. (021)587 4641-49,
Fax. (021)577035/5874546.

Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. (02)810 0161, Fax. (02)817 3474

Portugal: PHILIPS PORTUGUESA, S.A.,

Rua dr. António Loureiro Borges 5, Arquiparque - Miraflores,
Apartado 300, 2795 LINDA-A-VELHA,
Tel. (01)14163160/4163333, Fax. (01)14163174/4163366.

Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. (65)350 2000, Fax. (65)251 6500

South Africa: S.A. PHILIPS Pty Ltd., Components Division,

195-215 Main Road Martindale, 2092 JOHANNESBURG,
P.O. Box 7430 Johannesburg 2000,
Tel. (011)470-5911, Fax. (011)470-5494.

Spain: Balmes 22, 08007 BARCELONA,

Tel. (03)301 6312, Fax. (03)301 42 43

Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM,

Tel. (0)8-632 2000, Fax. (0)8-632 2745

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,

Tel. (01)488 2211, Fax. (01)481 77 30

Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West

Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978,
TAIPEI 100, Tel. (02)388 7666, Fax. (02)382 4382.

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

209/2 Sanpavuth-Bangna Road Prakanong,
Bangkok 10260, THAILAND,
Tel. (662)398-0141, Fax. (662)398-3319.

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,

Tel. (0 212)279 2770, Fax. (0212)269 3094

United Kingdom: Philips Semiconductors Limited, P.O. Box 65,

Philips House, Torrington Place, LONDON, WC1E 7HD,
Tel. (071)436 41 44, Fax. (071)323 03 42

United States: INTEGRATED CIRCUITS:

811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. (800)234-7381, Fax. (708)296-8556
DISCRETE SEMICONDUCTORS: 2001 West Blue Heron Blvd.,

P.O. Box 10330, RIVIERA BEACH, FLORIDA 33404,
Tel. (800)447-3762 and (407)881-3200, Fax. (407)881-3300

Uruguay: Coronel Mora 433, MONTEVIDEO,

Tel. (02)70-4044, Fax. (02)92 0601

For all other countries apply to: Philips Semiconductors,
International Marketing and Sales, Building BAF-1,
P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. +31-40-724825

SCD31

All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.

Printed in The Netherlands

513061/1500/01/pp24

Date of release: July 1994

Document order number:

9397 736 30011

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Document Outline

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